4
* Copyright (c) 2015 Chen Gang
6
* This library is free software; you can redistribute it and/or
7
* modify it under the terms of the GNU Lesser General Public
8
* License as published by the Free Software Foundation; either
9
* version 2.1 of the License, or (at your option) any later version.
11
* This library is distributed in the hope that it will be useful,
12
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14
* Lesser General Public License for more details.
16
* You should have received a copy of the GNU Lesser General Public
17
* License along with this library; if not, see
18
* <http://www.gnu.org/licenses/lgpl-2.1.html>
21
#include "qemu/osdep.h"
22
#include "qapi/error.h"
24
#include "qemu-common.h"
25
#include "hw/qdev-properties.h"
26
#include "migration/vmstate.h"
27
#include "linux-user/syscall_defs.h"
28
#include "exec/exec-all.h"
30
static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
31
fprintf_function cpu_fprintf, int flags)
33
static const char * const reg_names[TILEGX_R_COUNT] = {
34
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
35
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
36
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
37
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
38
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
39
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
40
"r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
43
TileGXCPU *cpu = TILEGX_CPU(cs);
44
CPUTLGState *env = &cpu->env;
47
for (i = 0; i < TILEGX_R_COUNT; i++) {
48
cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
49
reg_names[i], env->regs[i],
50
(i % 4) == 3 ? "\n" : " ");
52
cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
53
env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
56
TileGXCPU *cpu_tilegx_init(const char *cpu_model)
60
cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
62
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
67
static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
69
TileGXCPU *cpu = TILEGX_CPU(cs);
74
static bool tilegx_cpu_has_work(CPUState *cs)
79
static void tilegx_cpu_reset(CPUState *s)
81
TileGXCPU *cpu = TILEGX_CPU(s);
82
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
83
CPUTLGState *env = &cpu->env;
87
memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
90
static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
92
CPUState *cs = CPU(dev);
93
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
94
Error *local_err = NULL;
96
cpu_exec_realizefn(cs, &local_err);
97
if (local_err != NULL) {
98
error_propagate(errp, local_err);
105
tcc->parent_realize(dev, errp);
108
static void tilegx_cpu_initfn(Object *obj)
110
CPUState *cs = CPU(obj);
111
TileGXCPU *cpu = TILEGX_CPU(obj);
112
CPUTLGState *env = &cpu->env;
113
static bool tcg_initialized;
117
if (tcg_enabled() && !tcg_initialized) {
118
tcg_initialized = true;
123
static void tilegx_cpu_do_interrupt(CPUState *cs)
125
cs->exception_index = -1;
128
static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
131
TileGXCPU *cpu = TILEGX_CPU(cs);
133
/* The sigcode field will be filled in by do_signal in main.c. */
134
cs->exception_index = TILEGX_EXCP_SIGNAL;
135
cpu->env.excaddr = address;
136
cpu->env.signo = TARGET_SIGSEGV;
137
cpu->env.sigcode = 0;
142
static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
144
if (interrupt_request & CPU_INTERRUPT_HARD) {
145
tilegx_cpu_do_interrupt(cs);
151
static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
153
DeviceClass *dc = DEVICE_CLASS(oc);
154
CPUClass *cc = CPU_CLASS(oc);
155
TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
157
tcc->parent_realize = dc->realize;
158
dc->realize = tilegx_cpu_realizefn;
160
tcc->parent_reset = cc->reset;
161
cc->reset = tilegx_cpu_reset;
163
cc->has_work = tilegx_cpu_has_work;
164
cc->do_interrupt = tilegx_cpu_do_interrupt;
165
cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
166
cc->dump_state = tilegx_cpu_dump_state;
167
cc->set_pc = tilegx_cpu_set_pc;
168
cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
169
cc->gdb_num_core_regs = 0;
172
static const TypeInfo tilegx_cpu_type_info = {
173
.name = TYPE_TILEGX_CPU,
175
.instance_size = sizeof(TileGXCPU),
176
.instance_init = tilegx_cpu_initfn,
177
.class_size = sizeof(TileGXCPUClass),
178
.class_init = tilegx_cpu_class_init,
181
static void tilegx_cpu_register_types(void)
183
type_register_static(&tilegx_cpu_type_info);
186
type_init(tilegx_cpu_register_types)