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/* Copyright 2013 Freescale Semiconductor, Inc.
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* SPDX-License-Identifier: GPL-2.0+
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#include "../common/qixis.h"
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#include "b4860qds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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return CONFIG_SYS_L3_SIZE;
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unsigned long get_board_sys_clk(void)
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((sysclk_conf & 0x0C) >> 2) {
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unsigned long get_board_ddr_clk(void)
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch (ddrclk_conf & 0x03) {
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void board_init_f(ulong bootflag)
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u32 plat_ratio, sys_clk, uart_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
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/* Update GD pointer */
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
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/* compiler optimization barrier needed for GCC >= 3.4 */
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__asm__ __volatile__("" : : : "memory");
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/* initialize selected port with appropriate baud rate */
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sys_clk = get_board_sys_clk();
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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uart_clk = sys_clk * plat_ratio / 2;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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uart_clk / 16 / CONFIG_BAUDRATE);
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
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void board_init_r(gd_t *gd, ulong dest_addr)
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bd = (bd_t *)(gd + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
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bd->bi_memsize = CONFIG_SYS_L3_SIZE;
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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#ifndef CONFIG_SPL_NAND_BOOT
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/* relocate environment function pointers etc. */
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->ram_size = initdram(0);
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#ifdef CONFIG_SPL_NAND_BOOT