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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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/*
 
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 * (C) Copyright 2009 Faraday Technology
 
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 * Po-Yu Chuang <ratbert@faraday-tech.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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/*
 
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 * Timer
 
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 */
 
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#ifndef __FTTMR010_H
 
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#define __FTTMR010_H
 
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struct fttmr010 {
 
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        unsigned int    timer1_counter;         /* 0x00 */
 
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        unsigned int    timer1_load;            /* 0x04 */
 
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        unsigned int    timer1_match1;          /* 0x08 */
 
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        unsigned int    timer1_match2;          /* 0x0c */
 
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        unsigned int    timer2_counter;         /* 0x10 */
 
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        unsigned int    timer2_load;            /* 0x14 */
 
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        unsigned int    timer2_match1;          /* 0x18 */
 
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        unsigned int    timer2_match2;          /* 0x1c */
 
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        unsigned int    timer3_counter;         /* 0x20 */
 
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        unsigned int    timer3_load;            /* 0x24 */
 
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        unsigned int    timer3_match1;          /* 0x28 */
 
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        unsigned int    timer3_match2;          /* 0x2c */
 
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        unsigned int    cr;                     /* 0x30 */
 
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        unsigned int    interrupt_state;        /* 0x34 */
 
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        unsigned int    interrupt_mask;         /* 0x38 */
 
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};
 
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/*
 
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 * Timer Control Register
 
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 */
 
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#define FTTMR010_TM3_UPDOWN     (1 << 11)
 
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#define FTTMR010_TM2_UPDOWN     (1 << 10)
 
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#define FTTMR010_TM1_UPDOWN     (1 << 9)
 
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#define FTTMR010_TM3_OFENABLE   (1 << 8)
 
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#define FTTMR010_TM3_CLOCK      (1 << 7)
 
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#define FTTMR010_TM3_ENABLE     (1 << 6)
 
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#define FTTMR010_TM2_OFENABLE   (1 << 5)
 
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#define FTTMR010_TM2_CLOCK      (1 << 4)
 
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#define FTTMR010_TM2_ENABLE     (1 << 3)
 
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#define FTTMR010_TM1_OFENABLE   (1 << 2)
 
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#define FTTMR010_TM1_CLOCK      (1 << 1)
 
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#define FTTMR010_TM1_ENABLE     (1 << 0)
 
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/*
 
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 * Timer Interrupt State & Mask Registers
 
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 */
 
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#define FTTMR010_TM3_OVERFLOW   (1 << 8)
 
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#define FTTMR010_TM3_MATCH2     (1 << 7)
 
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#define FTTMR010_TM3_MATCH1     (1 << 6)
 
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#define FTTMR010_TM2_OVERFLOW   (1 << 5)
 
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#define FTTMR010_TM2_MATCH2     (1 << 4)
 
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#define FTTMR010_TM2_MATCH1     (1 << 3)
 
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#define FTTMR010_TM1_OVERFLOW   (1 << 2)
 
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#define FTTMR010_TM1_MATCH2     (1 << 1)
 
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#define FTTMR010_TM1_MATCH1     (1 << 0)
 
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#endif  /* __FTTMR010_H */