← Back to branch summary

~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

« back to all changes in this revision

Viewing changes to roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

Show diffs side-by-side

added added

removed removed

Lines of Context:
roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c
 
1
/*
 
2
 * Copyright (c) 2010 Samsung Electronics.
 
3
 * Minkyu Kang <mk7.kang@samsung.com>
 
4
 *
 
5
 * SPDX-License-Identifier:     GPL-2.0+
 
6
 */
 
7
 
 
8
#include <common.h>
 
9
#include <asm/io.h>
 
10
#include <asm/system.h>
 
11
 
 
12
enum l2_cache_params {
 
13
        CACHE_TAG_RAM_SETUP = (1 << 9),
 
14
        CACHE_DATA_RAM_SETUP = (1 << 5),
 
15
        CACHE_TAG_RAM_LATENCY = (2 << 6),
 
16
        CACHE_DATA_RAM_LATENCY = (2 << 0)
 
17
};
 
18
 
 
19
void reset_cpu(ulong addr)
 
20
{
 
21
        writel(0x1, samsung_get_base_swreset());
 
22
}
 
23
 
 
24
#ifndef CONFIG_SYS_DCACHE_OFF
 
25
void enable_caches(void)
 
26
{
 
27
        /* Enable D-cache. I-cache is already enabled in start.S */
 
28
        dcache_enable();
 
29
}
 
30
#endif
 
31
 
 
32
#ifndef CONFIG_SYS_L2CACHE_OFF
 
33
/*
 
34
 * Set L2 cache parameters
 
35
 */
 
36
static void exynos5_set_l2cache_params(void)
 
37
{
 
38
        unsigned int val = 0;
 
39
 
 
40
        asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
 
41
 
 
42
        val |= CACHE_TAG_RAM_SETUP |
 
43
                CACHE_DATA_RAM_SETUP |
 
44
                CACHE_TAG_RAM_LATENCY |
 
45
                CACHE_DATA_RAM_LATENCY;
 
46
 
 
47
        asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
 
48
}
 
49
 
 
50
/*
 
51
 * Sets L2 cache related parameters before enabling data cache
 
52
 */
 
53
void v7_outer_cache_enable(void)
 
54
{
 
55
        if (cpu_is_exynos5())
 
56
                exynos5_set_l2cache_params();
 
57
}
 
58
#endif