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Viewing changes to roms/u-boot/board/freescale/mpc8349emds/ddr.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/mpc8349emds/ddr.c
 
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/*
 
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 * Copyright 2011 Freescale Semiconductor, Inc.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <fsl_ddr_sdram.h>
 
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#include <fsl_ddr_dimm_params.h>
 
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struct board_specific_parameters {
 
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        u32 n_ranks;
 
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        u32 datarate_mhz_high;
 
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        u32 clk_adjust;
 
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        u32 cpo;
 
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        u32 write_data_delay;
 
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        u32 force_2t;
 
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};
 
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/*
 
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 * This table contains all valid speeds we want to override with board
 
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 * specific parameters. datarate_mhz_high values need to be in ascending order
 
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 * for each n_ranks group.
 
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 */
 
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static const struct board_specific_parameters udimm0[] = {
 
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        /*
 
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         * memory controller 0
 
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         *   num|  hi|  clk| cpo|wrdata|2T
 
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         * ranks| mhz|adjst|    | delay|
 
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         */
 
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        {2,  300,    4,   4,    2,  0},
 
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        {2,  365,    4,   6,    2,  0},
 
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        {2,  450,    4,   7,    2,  0},
 
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        {2,  850,    4,  31,    2,  0},
 
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        {1,  300,    4,   4,    2,  0},
 
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        {1,  365,    4,   6,    2,  0},
 
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        {1,  450,    4,   7,    2,  0},
 
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        {1,  850,    4,  31,    2,  0},
 
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        {}
 
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};
 
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void fsl_ddr_board_options(memctl_options_t *popts,
 
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                                dimm_params_t *pdimm,
 
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                                unsigned int ctrl_num)
 
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{
 
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        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 
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        unsigned int i;
 
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        ulong ddr_freq;
 
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        if (ctrl_num != 0)      /* we have only one controller */
 
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                return;
 
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        for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 
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                if (pdimm[i].n_ranks)
 
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                        break;
 
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        }
 
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        if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)    /* no DIMM */
 
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                return;
 
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        pbsp = udimm0;
 
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        /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 
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         * freqency and n_banks specified in board_specific_parameters table.
 
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         */
 
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        ddr_freq = get_ddr_freq(0) / 1000000;
 
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        while (pbsp->datarate_mhz_high) {
 
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                if (pbsp->n_ranks ==  pdimm[i].n_ranks) {
 
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                        if (ddr_freq <= pbsp->datarate_mhz_high) {
 
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                                popts->clk_adjust = pbsp->clk_adjust;
 
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                                popts->cpo_override = pbsp->cpo;
 
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                                popts->write_data_delay =
 
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                                        pbsp->write_data_delay;
 
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                                popts->twot_en = pbsp->force_2t;
 
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                                goto found;
 
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                        }
 
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                        pbsp_highest = pbsp;
 
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                }
 
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                pbsp++;
 
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        }
 
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        if (pbsp_highest) {
 
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                printf("Error: board specific timing not found "
 
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                        "for data rate %lu MT/s!\n"
 
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                        "Trying to use the highest speed (%u) parameters\n",
 
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                        ddr_freq, pbsp_highest->datarate_mhz_high);
 
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                popts->clk_adjust = pbsp_highest->clk_adjust;
 
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                popts->cpo_override = pbsp_highest->cpo;
 
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                popts->write_data_delay = pbsp_highest->write_data_delay;
 
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                popts->twot_en = pbsp_highest->force_2t;
 
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        } else {
 
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                panic("DIMM is not supported by this board");
 
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        }
 
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found:
 
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        /*
 
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         * Factors to consider for half-strength driver enable:
 
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         *      - number of DIMMs installed
 
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         */
 
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        popts->half_strength_driver_enable = 0;
 
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        popts->dqs_config = 0;  /* only true DQS signal is used on board */
 
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}