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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/Marvell/rd6281a/rd6281a.c
 
1
/*
 
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 * (C) Copyright 2009
 
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 * Marvell Semiconductor <www.marvell.com>
 
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 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <miiphy.h>
 
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#include <netdev.h>
 
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#include <asm/arch/cpu.h>
 
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#include <asm/arch/kirkwood.h>
 
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#include <asm/arch/mpp.h>
 
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#include "rd6281a.h"
 
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DECLARE_GLOBAL_DATA_PTR;
 
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int board_early_init_f(void)
 
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{
 
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        /*
 
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         * default gpio configuration
 
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         * There are maximum 64 gpios controlled through 2 sets of registers
 
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         * the  below configuration configures mainly initial LED status
 
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         */
 
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        kw_config_gpio(RD6281A_OE_VAL_LOW,
 
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                        RD6281A_OE_VAL_HIGH,
 
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                        RD6281A_OE_LOW, RD6281A_OE_HIGH);
 
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        /* Multi-Purpose Pins Functionality configuration */
 
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        static const u32 kwmpp_config[] = {
 
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                MPP0_NF_IO2,
 
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                MPP1_NF_IO3,
 
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                MPP2_NF_IO4,
 
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                MPP3_NF_IO5,
 
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                MPP4_NF_IO6,
 
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                MPP5_NF_IO7,
 
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                MPP6_SYSRST_OUTn,
 
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                MPP7_GPO,
 
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                MPP8_TW_SDA,
 
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                MPP9_TW_SCK,
 
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                MPP10_UART0_TXD,
 
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                MPP11_UART0_RXD,
 
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                MPP12_SD_CLK,
 
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                MPP13_SD_CMD,
 
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                MPP14_SD_D0,
 
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                MPP15_SD_D1,
 
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                MPP16_SD_D2,
 
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                MPP17_SD_D3,
 
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                MPP18_NF_IO0,
 
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                MPP19_NF_IO1,
 
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                MPP20_GE1_0,
 
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                MPP21_GE1_1,
 
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                MPP22_GE1_2,
 
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                MPP23_GE1_3,
 
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                MPP24_GE1_4,
 
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                MPP25_GE1_5,
 
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                MPP26_GE1_6,
 
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                MPP27_GE1_7,
 
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                MPP28_GPIO,
 
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                MPP29_GPIO,
 
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                MPP30_GE1_10,
 
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                MPP31_GE1_11,
 
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                MPP32_GE1_12,
 
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                MPP33_GE1_13,
 
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                MPP34_GE1_14,
 
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                MPP35_GPIO,
 
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                MPP36_AUDIO_SPDIFI,
 
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                MPP37_AUDIO_SPDIFO,
 
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                MPP38_GPIO,
 
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                MPP39_TDM_SPI_CS0,
 
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                MPP40_TDM_SPI_SCK,
 
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                MPP41_TDM_SPI_MISO,
 
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                MPP42_TDM_SPI_MOSI,
 
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                MPP43_TDM_CODEC_INTn,
 
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                MPP44_GPIO,
 
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                MPP45_TDM_PCLK,
 
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                MPP46_TDM_FS,
 
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                MPP47_TDM_DRX,
 
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                MPP48_TDM_DTX,
 
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                MPP49_GPIO,
 
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                0
 
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        };
 
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        kirkwood_mpp_conf(kwmpp_config, NULL);
 
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        return 0;
 
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}
 
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int board_init(void)
 
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{
 
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        /*
 
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         * arch number of board
 
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         */
 
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        gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
 
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        /* adress of boot parameters */
 
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        gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
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        return 0;
 
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}
 
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void mv_phy_88e1116_init(char *name)
 
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{
 
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        u16 reg;
 
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        u16 devadr;
 
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        if (miiphy_set_current_dev(name))
 
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                return;
 
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        /* command to read PHY dev address */
 
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        if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 
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                printf("Err..%s could not read PHY dev address\n",
 
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                        __FUNCTION__);
 
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                return;
 
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        }
 
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        /*
 
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         * Enable RGMII delay on Tx and Rx for CPU port
 
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         * Ref: sec 4.7.2 of chip datasheet
 
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         */
 
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        miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 
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        miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 
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        reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 
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        miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 
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        miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 
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        /* reset the phy */
 
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        if (miiphy_read (name, devadr, MII_BMCR, &reg) != 0) {
 
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                printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
 
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                return;
 
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        }
 
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        if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
 
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                printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
 
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                return;
 
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        }
 
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        printf("88E1116 Initialized on %s\n", name);
 
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}
 
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/* Configure and enable Switch and PHY */
 
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void reset_phy(void)
 
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{
 
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        /* configure and initialize switch */
 
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        struct mv88e61xx_config swcfg = {
 
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                .name = "egiga0",
 
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                .vlancfg = MV88E61XX_VLANCFG_ROUTER,
 
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                .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
 
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                .led_init = MV88E61XX_LED_INIT_EN,
 
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                .portstate = MV88E61XX_PORTSTT_FORWARDING,
 
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                .cpuport = (1 << 5),
 
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                .ports_enabled = 0x3f,
 
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        };
 
152
 
 
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        mv88e61xx_switch_initialize(&swcfg);
 
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        /* configure and initialize PHY */
 
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        mv_phy_88e1116_init("egiga1");
 
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}