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/* Copyright 2013-2014 IBM Corp.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* See the License for the specific language governing permissions and
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* limitations under the License.
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/*************************************/
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/* Register addresses and bit fields */
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/*************************************/
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#define NX_P7_SAT(sat, offset) XSCOM_SAT(0x1, sat, offset)
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#define NX_P8_SAT(sat, offset) XSCOM_SAT(0xc, sat, offset)
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/* Random Number Generator */
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#define NX_P7_RNG_BAR NX_P7_SAT(0x2, 0x0c)
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#define NX_P8_RNG_BAR NX_P8_SAT(0x2, 0x0d)
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#define NX_P7_RNG_BAR_ADDR PPC_BITMASK(18, 51)
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#define NX_P8_RNG_BAR_ADDR PPC_BITMASK(14, 51)
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#define NX_RNG_BAR_SIZE PPC_BITMASK(53, 55)
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#define NX_RNG_BAR_ENABLE PPC_BIT(52)
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#define NX_P7_RNG_CFG NX_P7_SAT(0x2, 0x12)
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#define NX_P8_RNG_CFG NX_P8_SAT(0x2, 0x12)
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#define NX_RNG_CFG_ENABLE PPC_BIT(63)
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/* Symmetric Crypto */
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#define NX_P7_SYM_CFG NX_P7_SAT(0x2, 0x09)
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#define NX_P8_SYM_CFG NX_P8_SAT(0x2, 0x0a)
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#define NX_SYM_CFG_CI PPC_BITMASK(2, 14)
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#define NX_SYM_CFG_CT PPC_BITMASK(18, 23)
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#define NX_SYM_CFG_FC_ENABLE PPC_BITMASK(32, 39)
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#define NX_SYM_CFG_ENABLE PPC_BIT(63)
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/* Asymmetric Crypto */
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#define NX_P7_ASYM_CFG NX_P7_SAT(0x2, 0x0a)
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#define NX_P8_ASYM_CFG NX_P8_SAT(0x2, 0x0b)
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#define NX_ASYM_CFG_CI PPC_BITMASK(2, 14)
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#define NX_ASYM_CFG_CT PPC_BITMASK(18, 23)
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#define NX_ASYM_CFG_FC_ENABLE PPC_BITMASK(32, 52)
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#define NX_ASYM_CFG_ENABLE PPC_BIT(63)
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#define NX_P7_842_CFG NX_P7_SAT(0x2, 0x0b)
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#define NX_P8_842_CFG NX_P8_SAT(0x2, 0x0c)
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#define NX_842_CFG_CI PPC_BITMASK(2, 14)
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#define NX_842_CFG_CT PPC_BITMASK(18, 23)
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#define NX_842_CFG_FC_ENABLE PPC_BITMASK(32, 36)
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#define NX_842_CFG_ENABLE PPC_BIT(63)
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#define NX_P7_DMA_CFG NX_P7_SAT(0x1, 0x02)
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#define NX_P8_DMA_CFG NX_P8_SAT(0x1, 0x02)
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#define NX_P8_DMA_CFG_842_COMPRESS_PREFETCH PPC_BIT(23)
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#define NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH PPC_BIT(24)
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#define NX_DMA_CFG_AES_SHA_MAX_RR PPC_BITMASK(25, 28)
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#define NX_DMA_CFG_AMF_MAX_RR PPC_BITMASK(29, 32)
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#define NX_DMA_CFG_842_COMPRESS_MAX_RR PPC_BITMASK(33, 36)
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#define NX_DMA_CFG_842_DECOMPRESS_MAX_RR PPC_BITMASK(37, 40)
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#define NX_DMA_CFG_AES_SHA_CSB_WR PPC_BITMASK(41, 42)
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#define NX_DMA_CFG_AES_SHA_COMPLETION_MODE PPC_BITMASK(43, 44)
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#define NX_DMA_CFG_AES_SHA_CPB_WR PPC_BITMASK(45, 46)
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#define NX_DMA_CFG_AES_SHA_OUTPUT_DATA_WR PPC_BIT(47)
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#define NX_DMA_CFG_AMF_CSB_WR PPC_BITMASK(49, 50)
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#define NX_DMA_CFG_AMF_COMPLETION_MODE PPC_BITMASK(51, 52)
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#define NX_DMA_CFG_AMF_CPB_WR PPC_BITMASK(53, 54)
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#define NX_DMA_CFG_AMF_OUTPUT_DATA_WR PPC_BIT(55)
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#define NX_DMA_CFG_842_SPBC PPC_BIT(56)
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#define NX_DMA_CFG_842_CSB_WR PPC_BITMASK(57, 58)
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#define NX_DMA_CFG_842_COMPLETION_MODE PPC_BITMASK(59, 60)
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#define NX_DMA_CFG_842_CPB_WR PPC_BITMASK(61, 62)
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#define NX_DMA_CFG_842_OUTPUT_DATA_WR PPC_BIT(63)
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/* Engine Enable Register */
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#define NX_P7_EE_CFG NX_P7_SAT(0x1, 0x01)
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#define NX_P8_EE_CFG NX_P8_SAT(0x1, 0x01)
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#define NX_EE_CFG_EFUSE PPC_BIT(0)
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#define NX_EE_CFG_CH7 PPC_BIT(53) /* AMF */
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#define NX_EE_CFG_CH6 PPC_BIT(54) /* AMF */
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#define NX_EE_CFG_CH5 PPC_BIT(55) /* AMF */
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#define NX_EE_CFG_CH4 PPC_BIT(56) /* P7: SYM, P8: AMF */
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#define NX_EE_CFG_CH3 PPC_BIT(57) /* SYM */
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#define NX_EE_CFG_CH2 PPC_BIT(58) /* SYM */
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#define NX_EE_CFG_CH1 PPC_BIT(62) /* 842 */
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#define NX_EE_CFG_CH0 PPC_BIT(63) /* 842 */
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/* PowerBus Registers */
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#define NX_P7_CRB_IQ NX_P7_SAT(0x2, 0x0e)
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#define NX_P8_CRB_IQ NX_P8_SAT(0x2, 0x0f)
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#define NX_CRB_IQ_SYM PPC_BITMASK(0, 2)
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#define NX_CRB_IQ_ASYM PPC_BITMASK(3, 5)
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/* NX Status Register */
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#define NX_P7_STATUS NX_P7_SAT(0x1, 0x00)
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#define NX_P8_STATUS NX_P8_SAT(0x1, 0x00)
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#define NX_STATUS_HMI_ACTIVE PPC_BIT(54)
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#define NX_STATUS_PBI_IDLE PPC_BIT(55)
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#define NX_STATUS_DMA_CH0_IDLE PPC_BIT(56)
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#define NX_STATUS_DMA_CH1_IDLE PPC_BIT(57)
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#define NX_STATUS_DMA_CH2_IDLE PPC_BIT(58)
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#define NX_STATUS_DMA_CH3_IDLE PPC_BIT(59)
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#define NX_STATUS_DMA_CH4_IDLE PPC_BIT(60)
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#define NX_STATUS_DMA_CH5_IDLE PPC_BIT(61)
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#define NX_STATUS_DMA_CH6_IDLE PPC_BIT(62)
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#define NX_STATUS_DMA_CH7_IDLE PPC_BIT(63)
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/* Channel Status Registers */
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#define NX_P7_CH_CRB(ch) NX_P7_SAT(0x1, 0x03 + ((ch) * 2))
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#define NX_P8_CH_CRB(ch) NX_P8_SAT(0x1, 0x03 + ((ch) * 2))
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#define NX_P7_CH_STATUS(ch) NX_P7_SAT(0x1, 0x04 + ((ch) * 2))
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#define NX_P8_CH_STATUS(ch) NX_P8_SAT(0x1, 0x04 + ((ch) * 2))
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#define NX_CH_STATUS_ABORT PPC_BIT(0)
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#define NX_CH_STATUS_CCB_VALID PPC_BIT(4)
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#define NX_CH_STATUS_CCB_CM PPC_BITMASK(5, 7)
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#define NX_CH_STATUS_CCB_PRIO PPC_BITMASK(8, 15)
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#define NX_CH_STATUS_CCB_SN PPC_BITMASK(16, 31)
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#define NX_CH_STATUS_VALID PPC_BIT(32)
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#define NX_CH_STATUS_LPID PPC_BITMASK(38, 47)
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#define NX_CH_STATUS_CCB_ISN PPC_BITMASK(50, 63)
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#define NX_CH_STATUS_CRB_SJT PPC_BITMASK(50, 63)
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#define NX_P7_CRB_KILL NX_P7_SAT(0x1, 0x13)
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#define NX_P8_CRB_KILL NX_P8_SAT(0x1, 0x13)
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#define NX_CRB_KILL_LPID_KILL PPC_BIT(0)
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#define NX_CRB_KILL_LPID PPC_BITMASK(6, 15)
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#define NX_CRB_KILL_ISN_KILL PPC_BIT(16)
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#define NX_CRB_KILL_SJT_KILL PPC_BIT(17)
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#define NX_CRB_KILL_ISN PPC_BITMASK(18, 31)
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#define NX_CRB_KILL_SJT PPC_BITMASK(18, 31)
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#define NX_CRB_KILL_DONE PPC_BIT(32)
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#define NX_CRB_KILL_PBI_LOC PPC_BITMASK(40, 47)
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#define NX_CRB_KILL_PREFETCH_CH PPC_BITMASK(48, 55)
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#define NX_CRB_KILL_ALG_CH PPC_BITMASK(56, 63)
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/* Fault Isolation Registers (FIR) */
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#define NX_P7_DE_FIR_DATA NX_P7_SAT(0x4, 0x00)
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#define NX_P8_DE_FIR_DATA NX_P8_SAT(0x4, 0x00)
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#define NX_P7_DE_FIR_DATA_CLR NX_P7_SAT(0x4, 0x01)
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#define NX_P8_DE_FIR_DATA_CLR NX_P8_SAT(0x4, 0x01)
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#define NX_P7_DE_FIR_DATA_SET NX_P7_SAT(0x4, 0x02)
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#define NX_P8_DE_FIR_DATA_SET NX_P8_SAT(0x4, 0x02)
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#define NX_P7_DE_FIR_MASK NX_P7_SAT(0x4, 0x06)
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#define NX_P8_DE_FIR_MASK NX_P8_SAT(0x4, 0x03)
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#define NX_P7_DE_FIR_MASK_CLR NX_P7_SAT(0x4, 0x07)
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#define NX_P8_DE_FIR_MASK_CLR NX_P8_SAT(0x4, 0x04)
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#define NX_P7_DE_FIR_MASK_SET NX_P7_SAT(0x4, 0x08)
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#define NX_P8_DE_FIR_MASK_SET NX_P8_SAT(0x4, 0x05)
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#define NX_P7_DE_FIR_ACTION0 NX_P7_SAT(0x4, 0x03)
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#define NX_P8_DE_FIR_ACTION0 NX_P8_SAT(0x4, 0x06)
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#define NX_P7_DE_FIR_ACTION1 NX_P7_SAT(0x4, 0x04)
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#define NX_P8_DE_FIR_ACTION1 NX_P8_SAT(0x4, 0x07)
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#define NX_P7_DE_FIR_WOF NX_P7_SAT(0x4, 0x05)
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#define NX_P8_DE_FIR_WOF NX_P8_SAT(0x4, 0x08)
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#define NX_P7_PB_FIR_DATA NX_P7_SAT(0x2, 0x00)
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#define NX_P8_PB_FIR_DATA NX_P8_SAT(0x2, 0x00)
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#define NX_P7_PB_FIR_DATA_CLR NX_P7_SAT(0x2, 0x01)
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#define NX_P8_PB_FIR_DATA_CLR NX_P8_SAT(0x2, 0x01)
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#define NX_P7_PB_FIR_DATA_SET NX_P7_SAT(0x2, 0x02)
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#define NX_P8_PB_FIR_DATA_SET NX_P8_SAT(0x2, 0x02)
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#define NX_P7_PB_FIR_MASK NX_P7_SAT(0x2, 0x06)
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#define NX_P8_PB_FIR_MASK NX_P8_SAT(0x2, 0x03)
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#define NX_P7_PB_FIR_MASK_CLR NX_P7_SAT(0x2, 0x07)
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#define NX_P8_PB_FIR_MASK_CLR NX_P8_SAT(0x2, 0x04)
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#define NX_P7_PB_FIR_MASK_SET NX_P7_SAT(0x2, 0x08)
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#define NX_P8_PB_FIR_MASK_SET NX_P8_SAT(0x2, 0x05)
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#define NX_P7_PB_FIR_ACTION0 NX_P7_SAT(0x2, 0x03)
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#define NX_P8_PB_FIR_ACTION0 NX_P8_SAT(0x2, 0x06)
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#define NX_P7_PB_FIR_ACTION1 NX_P7_SAT(0x2, 0x04)
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#define NX_P8_PB_FIR_ACTION1 NX_P8_SAT(0x2, 0x07)
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#define NX_P7_PB_FIR_WOF NX_P7_SAT(0x2, 0x05)
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#define NX_P8_PB_FIR_WOF NX_P8_SAT(0x2, 0x08)
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#define NX_FIR_MCD_PB_CMD_HANG PPC_BIT(0) /* P7 only */
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#define NX_FIR_SHM_INV PPC_BIT(1)
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#define NX_FIR_MCD_ARRAY_ECC_CE PPC_BIT(2) /* P7 only */
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#define NX_FIR_MCD_ARRAY_ECC_UE PPC_BIT(3) /* P7 only */
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#define NX_FIR_CH0_ECC_CE PPC_BIT(4)
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#define NX_FIR_CH0_ECC_UE PPC_BIT(5)
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#define NX_FIR_CH1_ECC_CE PPC_BIT(6)
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#define NX_FIR_CH1_ECC_UE PPC_BIT(7)
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#define NX_FIR_DMA_NZ_CSB_CC PPC_BIT(8) /* lab use only */
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#define NX_FIR_DMA_ARRAY_ECC_CE PPC_BIT(9)
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#define NX_FIR_DMA_RW_ECC_CE PPC_BIT(10)
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#define NX_FIR_CH5_ECC_CE PPC_BIT(11)
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#define NX_FIR_CH6_ECC_CE PPC_BIT(12)
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#define NX_FIR_CH7_ECC_CE PPC_BIT(13)
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#define NX_FIR_OTHER_SCOM_ERR PPC_BIT(14)
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#define NX_FIR_DMA_INV_STATE PPC_BITMASK(15, 16)
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#define NX_FIR_DMA_ARRAY_ECC_UE PPC_BIT(17)
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#define NX_FIR_DMA_RW_ECC_UE PPC_BIT(18)
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#define NX_FIR_HYP PPC_BIT(19) /* for HYP to force HMI */
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#define NX_FIR_CH0_INV_STATE PPC_BIT(20)
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#define NX_FIR_CH1_INV_STATE PPC_BIT(21)
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#define NX_FIR_CH2_INV_STATE PPC_BIT(22)
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#define NX_FIR_CH3_INV_STATE PPC_BIT(23)
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#define NX_FIR_CH4_INV_STATE PPC_BIT(24)
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#define NX_FIR_CH5_INV_STATE PPC_BIT(25)
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#define NX_FIR_CH6_INV_STATE PPC_BIT(26)
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#define NX_FIR_CH7_INV_STATE PPC_BIT(27)
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#define NX_FIR_CH5_ECC_UE PPC_BIT(28)
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#define NX_FIR_CH6_ECC_UE PPC_BIT(29)
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#define NX_FIR_CH7_ECC_UE PPC_BIT(30)
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#define NX_FIR_CRB_UE PPC_BIT(31)
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#define NX_FIR_CRB_SUE PPC_BIT(32)
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#define NX_FIR_DMA_RW_ECC_SUE PPC_BIT(33)
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#define NX_FIR_MCD_CFG_REG_PARITY PPC_BIT(34) /* P7 only */
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#define NX_FIR_MCD_RECOVERY_INV_STATE PPC_BIT(35) /* P7 only */
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#define NX_FIR_P7_PARITY PPC_BIT(36) /* P7 only */
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#define NX_FIR_CH4_ECC_CE PPC_BIT(36) /* P8 only */
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#define NX_FIR_CH5_ECC_UE_2 PPC_BIT(37) /* P8 only */
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#define NX_FIR_P8_PARITY PPC_BITMASK(48, 49)
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/**************************************/
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/* Register field values/restrictions */
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/**************************************/
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/* Arbitrary Coprocessor Type values */
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#define NX_CT_SYM (1)
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#define NX_CT_ASYM (2)
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#define NX_CT_842 (3)
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/* Coprocessor Instance counter
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* NX workbook, section 5.5.1
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* "Assigning <CT,CI> Values"
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#define NX_SYM_CFG_CI_MAX (511)
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#define NX_SYM_CFG_CI_LSHIFT (2)
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#define NX_ASYM_CFG_CI_MAX (127)
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#define NX_ASYM_CFG_CI_LSHIFT (4)
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#define NX_842_CFG_CI_MAX (511)
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#define NX_842_CFG_CI_LSHIFT (2)
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/* DMA configuration values
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* NX workbook, section 5.2.3, table 5-4
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* "DMA Configuration Register Bits"
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* These values can be used for the AES/SHA, AMF, and 842 DMA
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* configuration fields in the DMA configuration register.
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* Abbreviations used below:
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* pDMA - "partial DMA write"
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* fDMA - "full DMA write"
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/* NX_DMA_CSB_WR values:
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* 0 = Always perform 8 or 16 byte pDMA
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* 1 = Do 128 byte CI if CSB at end of cache line, else pDMA
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* 2 = Do 128 byte fDMA if CSB at end of cache line, else pDMA
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#define NX_DMA_CSB_WR_PDMA (0)
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#define NX_DMA_CSB_WR_CI (1)
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#define NX_DMA_CSB_WR_FDMA (2)
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/* NX_DMA_COMPLETION_MODE values:
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* 0 = Always perform 8 byte pDMA
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* 1 = Do 128 byte CI, replicating 8 bytes across entire 128 byte cache line
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* 2 = Do 128 byte fDMA, replicating 8 bytes across entire 128 byte cache line
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#define NX_DMA_COMPLETION_MODE_PDMA (0)
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#define NX_DMA_COMPLETION_MODE_CI (1)
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#define NX_DMA_COMPLETION_MODE_FDMA (2)
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/* NX_DMA_CPB_WR values:
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* 0 = Always do pDMA or fDMA, based on number of bytes and alignment
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* 1 = Always do pDMA on non-aligned cache lines, fDMA on aligned cache lines
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* (may store dummy data at the end of the aligned data)
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* 2 = Do 128 byte CI when writing 128 aligned bytes, else pDMA
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* 3 = Do 128 byte CI when writing aligned cache lines, else pDMA
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* (may store dummy data at the end of the aligned data)
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#define NX_DMA_CPB_WR_DMA_NOPAD (0)
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#define NX_DMA_CPB_WR_DMA_PAD (1)
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#define NX_DMA_CPB_WR_CI_NOPAD (2)
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#define NX_DMA_CPB_WR_CI_PAD (3)
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/* NX_DMA_OUTPUT_DATA_WR values:
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* 0 = Always do pDMA or fDMA, based on number of bytes and alignment
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* 1 = Do 128 byte CI when writing 128 aligned bytes, else pDMA
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#define NX_DMA_OUTPUT_DATA_WR_DMA (0)
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#define NX_DMA_OUTPUT_DATA_WR_CI (1)
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/******************************/
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/* NX node creation functions */
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/******************************/
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extern void nx_create_rng_node(struct dt_node *);
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extern void nx_create_crypto_node(struct dt_node *);
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extern void nx_create_842_node(struct dt_node *);
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extern void nx_init(void);