← Back to branch summary

~pmdj/ubuntu/trusty/qemu/2.9+applesmc+fadtv3

« back to all changes in this revision

Viewing changes to roms/u-boot/include/configs/SIMPC8313.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

Show diffs side-by-side

added added

removed removed

Lines of Context:
roms/u-boot/include/configs/SIMPC8313.h
 
1
/*
 
2
 * Copyright (C) Sheldon Instruments, Inc. 2008
 
3
 *
 
4
 * SPDX-License-Identifier:     GPL-2.0+
 
5
 */
 
6
/*
 
7
 * simpc8313 board configuration file
 
8
 */
 
9
 
 
10
#ifndef __CONFIG_H
 
11
#define __CONFIG_H
 
12
 
 
13
/*
 
14
 * High Level Configuration Options
 
15
 */
 
16
#define CONFIG_NAND_U_BOOT
 
17
 
 
18
#define CONFIG_E300                     1
 
19
#define CONFIG_MPC831x                  1
 
20
#define CONFIG_MPC8313                  1
 
21
 
 
22
#define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)
 
23
#define CONFIG_SYS_NAND_U_BOOT_DST      0x00100000
 
24
#define CONFIG_SYS_NAND_U_BOOT_START    0x00100100
 
25
#define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
 
26
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
27
 
 
28
#define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
 
29
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
 
30
 
 
31
#ifdef CONFIG_NAND_SPL
 
32
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 
33
#else
 
34
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
35
#endif
 
36
 
 
37
#define CONFIG_PCI
 
38
#define CONFIG_PCI_INDIRECT_BRIDGE
 
39
#define CONFIG_FSL_ELBC                 1
 
40
 
 
41
#define CONFIG_MISC_INIT_R
 
42
 
 
43
/*
 
44
 * On-board devices
 
45
 *
 
46
 * TSEC1 is Marvell PHY 88E1118
 
47
 */
 
48
 
 
49
#define CONFIG_SYS_33MHZ
 
50
 
 
51
#define CONFIG_83XX_CLKIN               33333333        /* in Hz */
 
52
 
 
53
#define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
 
54
 
 
55
#define CONFIG_SYS_IMMR                 0xE0000000
 
56
 
 
57
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 
58
#define CONFIG_DEFAULT_IMMR             CONFIG_SYS_IMMR
 
59
#endif
 
60
 
 
61
#define CONFIG_SYS_MEMTEST_START        0x00001000
 
62
#define CONFIG_SYS_MEMTEST_END          0x07f00000
 
63
 
 
64
#define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 
65
#define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 
66
 
 
67
/*
 
68
 * Device configurations
 
69
 */
 
70
#define CONFIG_TSEC1
 
71
 
 
72
/*
 
73
 * DDR Setup
 
74
 */
 
75
                                        /* DDR is system memory*/
 
76
#define CONFIG_SYS_DDR_BASE             0x00000000
 
77
#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 
78
#define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 
79
 
 
80
#define CONFIG_VERY_BIG_RAM
 
81
#define CONFIG_MAX_MEM_MAPPED           (512 << 20)
 
82
 
 
83
#define CONFIG_SYS_DDRCDR               (DDRCDR_EN \
 
84
                                        | DDRCDR_PZ_NOMZ \
 
85
                                        | DDRCDR_NZ_NOMZ \
 
86
                                        | DDRCDR_M_ODR)
 
87
                                        /* 0x73000002 TODO ODR & DRN ? */
 
88
 
 
89
/*
 
90
 * FLASH on the Local Bus
 
91
 */
 
92
#define CONFIG_SYS_NO_FLASH
 
93
 
 
94
#if !defined(CONFIG_NAND_SPL)
 
95
#define CONFIG_SYS_RAMBOOT
 
96
#endif
 
97
 
 
98
#define CONFIG_SYS_INIT_RAM_LOCK        1
 
99
#define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 
100
#define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 
101
 
 
102
#define CONFIG_SYS_GBL_DATA_OFFSET      \
 
103
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
104
#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 
105
 
 
106
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 
107
#define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 
108
#define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 
109
 
 
110
/*
 
111
 * Local Bus LCRR and LBCR regs
 
112
 */
 
113
#define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 
114
#define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 
115
#define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 
116
#define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 
117
                                | (0xFF << LBCR_BMT_SHIFT) \
 
118
                                | 0xF)  /* 0x0004ff0f */
 
119
 
 
120
                                /* LB refresh timer prescal, 266MHz/32 */
 
121
#define CONFIG_SYS_LBC_MRTPR    0x20000000
 
122
 
 
123
/* drivers/mtd/nand/nand.c */
 
124
#ifdef CONFIG_NAND_SPL
 
125
#define CONFIG_SYS_NAND_BASE            0xFFF00000
 
126
#else
 
127
#define CONFIG_SYS_NAND_BASE            0xE2800000
 
128
#endif
 
129
#define CONFIG_SYS_FPGA_BASE            0xFF000000
 
130
 
 
131
#define CONFIG_CMD_NAND
 
132
#define CONFIG_SYS_MAX_NAND_DEVICE      1
 
133
#define CONFIG_MTD_NAND_VERIFY_WRITE
 
134
#define CONFIG_NAND_FSL_ELBC            1
 
135
 
 
136
#define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 
137
                                | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 
138
                                | BR_PS_8               /* 8 bit Port */ \
 
139
                                | BR_MS_FCM             /* MSEL = FCM */ \
 
140
                                | BR_V)                 /* valid */
 
141
 
 
142
#ifdef CONFIG_NAND_SP
 
143
#define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 
144
                                        | OR_FCM_CSCT \
 
145
                                        | OR_FCM_CST \
 
146
                                        | OR_FCM_CHT \
 
147
                                        | OR_FCM_SCY_1 \
 
148
                                        | OR_FCM_TRLX \
 
149
                                        | OR_FCM_EHTR)
 
150
#define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 
151
#define CONFIG_SYS_NAND_PAGE_SIZE       512     /* NAND chip page size */
 
152
                                        /* NAND chip block size */
 
153
#define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)
 
154
#define NAND_CACHE_PAGES                32
 
155
#elif defined(CONFIG_NAND_LP)
 
156
#define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_256KB \
 
157
                                        | OR_FCM_PGS \
 
158
                                        | OR_FCM_CSCT \
 
159
                                        | OR_FCM_CST \
 
160
                                        | OR_FCM_CHT \
 
161
                                        | OR_FCM_SCY_1 \
 
162
                                        | OR_FCM_TRLX \
 
163
                                        | OR_FCM_EHTR)
 
164
#define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 
165
#define CONFIG_SYS_NAND_PAGE_SIZE       2048    /* NAND chip page size */
 
166
                                        /* NAND chip block size */
 
167
#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 
168
#define NAND_CACHE_PAGES                64
 
169
#else
 
170
#error Page size of NAND not defined.
 
171
#endif /* CONFIG_NAND_SP */
 
172
 
 
173
#define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SYS_NAND_BLOCK_SIZE
 
174
 
 
175
#define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_NAND_BR_PRELIM
 
176
#define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_NAND_OR_PRELIM
 
177
 
 
178
#define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_NAND_BASE
 
179
 
 
180
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
 
181
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR0_PRELIM
 
182
 
 
183
#define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_FPGA_BASE \
 
184
                                        | BR_PS_16 \
 
185
                                        | BR_MS_UPMA \
 
186
                                        | BR_V)
 
187
#define CONFIG_SYS_OR1_PRELIM           (OR_AM_2MB \
 
188
                                        | OR_UPM_BCTLD)
 
189
 
 
190
#define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA_BASE
 
191
#define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_2MB)
 
192
 
 
193
/*
 
194
 * JFFS2 configuration
 
195
 */
 
196
#define CONFIG_JFFS2_NAND
 
197
#define CONFIG_JFFS2_DEV        "nand0"
 
198
 
 
199
/* mtdparts command line support */
 
200
#define CONFIG_CMD_MTDPARTS
 
201
#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 
202
#define MTDIDS_DEFAULT          "nand0=nand0"
 
203
#define MTDPARTS_DEFAULT        "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 
204
 
 
205
/* pass open firmware flat tree */
 
206
#define CONFIG_OF_LIBFDT                1
 
207
#define CONFIG_OF_BOARD_SETUP           1
 
208
#define CONFIG_OF_STDOUT_VIA_ALIAS      1
 
209
 
 
210
/*
 
211
 * Serial Port
 
212
 */
 
213
#define CONFIG_CONS_INDEX               1
 
214
#define CONFIG_SYS_NS16550
 
215
#define CONFIG_SYS_NS16550_SERIAL
 
216
#define CONFIG_SYS_NS16550_REG_SIZE     1
 
217
#ifdef CONFIG_NAND_SPL
 
218
#define CONFIG_NS16550_MIN_FUNCTIONS
 
219
#endif
 
220
 
 
221
#define CONFIG_SYS_BAUDRATE_TABLE       \
 
222
                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
223
 
 
224
#define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR+0x4500)
 
225
#define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR+0x4600)
 
226
 
 
227
/* Use the HUSH parser */
 
228
#define CONFIG_SYS_HUSH_PARSER
 
229
 
 
230
/* I2C */
 
231
#define CONFIG_SYS_I2C
 
232
#define CONFIG_SYS_I2C_FSL
 
233
#define CONFIG_SYS_FSL_I2C_SPEED        400000
 
234
#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 
235
#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 
236
#define CONFIG_SYS_FSL_I2C2_SPEED       400000
 
237
#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 
238
#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 
239
#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 
240
 
 
241
/*
 
242
 * General PCI
 
243
 * Addresses are mapped 1-1.
 
244
 */
 
245
#define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 
246
#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 
247
#define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 
248
#define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 
249
#define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 
250
#define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 
251
#define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 
252
#define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 
253
#define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 
254
 
 
255
#define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 
256
#define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1057  /* Motorola */
 
257
 
 
258
/*
 
259
 * TSEC
 
260
 */
 
261
#define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 
262
 
 
263
#define CONFIG_GMII                     /* MII PHY management */
 
264
 
 
265
#ifdef CONFIG_TSEC1
 
266
#define CONFIG_HAS_ETH0
 
267
#define CONFIG_TSEC1_NAME               "TSEC0"
 
268
#define CONFIG_SYS_TSEC1_OFFSET         0x24000
 
269
#define TSEC1_PHY_ADDR                  0x0
 
270
#define TSEC1_FLAGS                     TSEC_GIGABIT
 
271
#define TSEC1_PHYIDX                    0
 
272
#endif
 
273
 
 
274
#ifdef CONFIG_TSEC2
 
275
#define CONFIG_HAS_ETH1
 
276
#define CONFIG_TSEC2_NAME               "TSEC1"
 
277
#define CONFIG_SYS_TSEC2_OFFSET         0x25000
 
278
#define TSEC2_PHY_ADDR                  4
 
279
#define TSEC2_FLAGS                     TSEC_GIGABIT
 
280
#define TSEC2_PHYIDX                    0
 
281
#endif
 
282
 
 
283
 
 
284
/* Options are: TSEC[0-1] */
 
285
#define CONFIG_ETHPRIME                 "TSEC1"
 
286
 
 
287
/*
 
288
 * Configure on-board RTC
 
289
 */
 
290
#define CONFIG_RTC_DS1337
 
291
#define CONFIG_SYS_I2C_RTC_ADDR         0x68
 
292
 
 
293
/*
 
294
 * Environment
 
295
 */
 
296
#if defined(CONFIG_NAND_U_BOOT)
 
297
        #define CONFIG_ENV_IS_IN_NAND   1
 
298
        #define CONFIG_ENV_OFFSET       (768 * 1024)
 
299
        #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 
300
        #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 
301
        #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 
302
        #define CONFIG_ENV_RANGE        (CONFIG_ENV_SECT_SIZE * 4)
 
303
        #define CONFIG_ENV_OFFSET_REDUND        \
 
304
                                        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 
305
#elif !defined(CONFIG_SYS_RAMBOOT)
 
306
        #define CONFIG_ENV_IS_IN_FLASH  1
 
307
        #define CONFIG_ENV_ADDR         \
 
308
                        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
309
        #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 
310
        #define CONFIG_ENV_SIZE         0x2000
 
311
 
 
312
/* Address and size of Redundant Environment Sector */
 
313
#else
 
314
        #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 
315
        #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 
316
        #define CONFIG_ENV_SIZE         0x2000
 
317
#endif
 
318
 
 
319
#define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 
320
#define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 
321
 
 
322
/*
 
323
 * BOOTP options
 
324
 */
 
325
#define CONFIG_BOOTP_BOOTFILESIZE
 
326
#define CONFIG_BOOTP_BOOTPATH
 
327
#define CONFIG_BOOTP_GATEWAY
 
328
#define CONFIG_BOOTP_HOSTNAME
 
329
 
 
330
 
 
331
/*
 
332
 * Command line configuration.
 
333
 */
 
334
#include <config_cmd_default.h>
 
335
#undef CONFIG_CMD_IMLS
 
336
#undef CONFIG_CMD_FLASH
 
337
 
 
338
#define CONFIG_CMD_PING
 
339
#define CONFIG_CMD_DHCP
 
340
#define CONFIG_CMD_I2C
 
341
#define CONFIG_CMD_MII
 
342
#define CONFIG_CMD_DATE
 
343
#define CONFIG_CMD_PCI
 
344
#define CONFIG_CMD_JFFS2
 
345
 
 
346
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 
347
        #undef CONFIG_CMD_SAVEENV
 
348
        #undef CONFIG_CMD_LOADS
 
349
#endif
 
350
 
 
351
#define CONFIG_CMDLINE_EDITING  1
 
352
#define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 
353
 
 
354
/*
 
355
 * Miscellaneous configurable options
 
356
 */
 
357
#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 
358
#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 
359
#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 
360
 
 
361
#define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE              \
 
362
                                + sizeof(CONFIG_SYS_PROMPT)     \
 
363
                                + 16)   /* Print Buffer Size */
 
364
#define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 
365
                                /* Boot Argument Buffer Size */
 
366
#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 
367
 
 
368
/*
 
369
 * For booting Linux, the board info and command line data
 
370
 * have to be in the first 256 MB of memory, since this is
 
371
 * the maximum mapped by the Linux kernel during initialization.
 
372
 */
 
373
                                /* Initial Memory map for Linux*/
 
374
#define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 
375
 
 
376
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST */
 
377
 
 
378
#define CONFIG_SYS_HRCW_LOW     (HRCWL_LCL_BUS_TO_SCB_CLK_1X1   \
 
379
                                | 0x20000000 /* reserved */     \
 
380
                                | HRCWL_DDR_TO_SCB_CLK_2X1      \
 
381
                                | HRCWL_CSB_TO_CLKIN_4X1        \
 
382
                                | HRCWL_CORE_TO_CSB_2_5X1)
 
383
 
 
384
#define CONFIG_SYS_NS16550_CLK  (CONFIG_83XX_CLKIN * 4)
 
385
 
 
386
#define CONFIG_SYS_HRCW_HIGH_BASE       (HRCWH_PCI_HOST \
 
387
                                | HRCWH_PCI1_ARBITER_ENABLE     \
 
388
                                | HRCWH_CORE_ENABLE             \
 
389
                                | HRCWH_BOOTSEQ_DISABLE         \
 
390
                                | HRCWH_SW_WATCHDOG_DISABLE     \
 
391
                                | HRCWH_TSEC1M_IN_RGMII         \
 
392
                                | HRCWH_TSEC2M_IN_RGMII         \
 
393
                                | HRCWH_BIG_ENDIAN              \
 
394
                                | HRCWH_LALE_NORMAL)
 
395
 
 
396
#ifdef CONFIG_NAND_LP
 
397
#define CONFIG_SYS_HRCW_HIGH    (CONFIG_SYS_HRCW_HIGH_BASE      \
 
398
                                | HRCWH_FROM_0XFFF00100         \
 
399
                                | HRCWH_ROM_LOC_NAND_LP_8BIT    \
 
400
                                | HRCWH_RL_EXT_NAND)
 
401
#else
 
402
#define CONFIG_SYS_HRCW_HIGH    (CONFIG_SYS_HRCW_HIGH_BASE      \
 
403
                                | HRCWH_FROM_0XFFF00100         \
 
404
                                | HRCWH_ROM_LOC_NAND_SP_8BIT    \
 
405
                                | HRCWH_RL_EXT_NAND)
 
406
#endif
 
407
 
 
408
/* System IO Config */
 
409
#define CONFIG_SYS_SICRH        (SICRH_ETSEC2_B \
 
410
                                | SICRH_ETSEC2_C        \
 
411
                                | SICRH_ETSEC2_D        \
 
412
                                | SICRH_ETSEC2_E        \
 
413
                                | SICRH_ETSEC2_F        \
 
414
                                | SICRH_ETSEC2_G        \
 
415
                                | SICRH_TSOBI1          \
 
416
                                | SICRH_TSOBI2)
 
417
#define CONFIG_SYS_SICRL        (SICRL_LBC              \
 
418
                                | SICRL_USBDR_10        \
 
419
                                | SICRL_ETSEC2_A)
 
420
 
 
421
#define CONFIG_SYS_HID0_INIT    0x000000000
 
422
#define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 
423
                                | HID0_ENABLE_INSTRUCTION_CACHE \
 
424
                                | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 
425
 
 
426
#define CONFIG_SYS_HID2         HID2_HBE
 
427
 
 
428
#define CONFIG_HIGH_BATS        1       /* High BATs supported */
 
429
 
 
430
/* DDR @ 0x00000000 */
 
431
#define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 
432
#define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 
433
                                | BATU_BL_256M \
 
434
                                | BATU_VS \
 
435
                                | BATU_VP)
 
436
#define CONFIG_SYS_IBAT1L       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
 
437
                                | BATL_PP_RW)
 
438
#define CONFIG_SYS_IBAT1U       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
 
439
                                | BATU_BL_256M \
 
440
                                | BATU_VS \
 
441
                                | BATU_VP)
 
442
 
 
443
/* PCI @ 0x80000000 */
 
444
#define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 
445
#define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MEM_BASE \
 
446
                                | BATU_BL_256M \
 
447
                                | BATU_VS \
 
448
                                | BATU_VP)
 
449
#define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MMIO_BASE \
 
450
                                | BATL_PP_RW \
 
451
                                | BATL_CACHEINHIBIT \
 
452
                                | BATL_GUARDEDSTORAGE)
 
453
#define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MMIO_BASE \
 
454
                                | BATU_BL_256M \
 
455
                                | BATU_VS \
 
456
                                | BATU_VP)
 
457
 
 
458
/* PCI2 not supported on 8313 */
 
459
#define CONFIG_SYS_IBAT4L       (0)
 
460
#define CONFIG_SYS_IBAT4U       (0)
 
461
 
 
462
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 
463
#define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 
464
                                | BATL_PP_RW \
 
465
                                | BATL_CACHEINHIBIT \
 
466
                                | BATL_GUARDEDSTORAGE)
 
467
#define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 
468
                                | BATU_BL_256M \
 
469
                                | BATU_VS \
 
470
                                | BATU_VP)
 
471
 
 
472
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 
473
#define CONFIG_SYS_IBAT6L       (0xF0000000 \
 
474
                                | BATL_PP_RW \
 
475
                                | BATL_GUARDEDSTORAGE)
 
476
#define CONFIG_SYS_IBAT6U       (0xF0000000 \
 
477
                                | BATU_BL_256M \
 
478
                                | BATU_VS \
 
479
                                | BATU_VP)
 
480
 
 
481
#define CONFIG_SYS_IBAT7L       (0)
 
482
#define CONFIG_SYS_IBAT7U       (0)
 
483
 
 
484
#define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 
485
#define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 
486
#define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 
487
#define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 
488
#define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 
489
#define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 
490
#define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 
491
#define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 
492
#define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 
493
#define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 
494
#define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 
495
#define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 
496
#define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 
497
#define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 
498
#define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 
499
#define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 
500
 
 
501
/*
 
502
 * Environment Configuration
 
503
 */
 
504
#define CONFIG_ENV_OVERWRITE
 
505
 
 
506
#define CONFIG_NETDEV           "eth1"
 
507
 
 
508
#define CONFIG_HOSTNAME         simpc8313
 
509
#define CONFIG_ROOTPATH         "/tftpboot/"
 
510
#define CONFIG_BOOTFILE         "/tftpboot/uImage"
 
511
                                /* U-Boot image on TFTP server */
 
512
#define CONFIG_UBOOTPATH        "u-boot-nand.bin"
 
513
#define CONFIG_FDTFILE          "simpc8313.dtb"
 
514
 
 
515
                                /* default location for tftp and bootm */
 
516
#define CONFIG_LOADADDR         500000
 
517
#define CONFIG_BOOTDELAY        5       /* 5 second delay */
 
518
#define CONFIG_BAUDRATE         115200
 
519
 
 
520
#define CONFIG_BOOTCOMMAND      "nand read $loadaddr kernel 600000;" \
 
521
                                        "bootm $loadaddr - $fdtaddr"
 
522
 
 
523
#define CONFIG_EXTRA_ENV_SETTINGS \
 
524
        "netdev=" CONFIG_NETDEV "\0"                                    \
 
525
        "ethprime=TSEC1\0"                                              \
 
526
        "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 
527
        "tftpflash=tftpboot $loadaddr $uboot; "                         \
 
528
                "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 
529
                        " +$filesize; " \
 
530
                "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 
531
                        " +$filesize; " \
 
532
                "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 
533
                        " $filesize; "  \
 
534
                "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 
535
                        " +$filesize; " \
 
536
                "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 
537
                        " $filesize\0"  \
 
538
        "fdtaddr=ae0000\0"                                              \
 
539
        "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 
540
        "console=ttyS0\0"                                               \
 
541
        "setbootargs=setenv bootargs "                                  \
 
542
                "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 
543
        "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 
544
                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 
545
                                                        "$netdev:off "  \
 
546
                "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 
547
        "load_uboot=tftp 100000 u-boot-nand.bin\0"                      \
 
548
        "burn_uboot=nand erase u-boot 80000; "                          \
 
549
                "nand write 100000 u-boot $filesize\0"                  \
 
550
        "update_uboot=run load_uboot;run burn_uboot\0"                  \
 
551
        "mtdids=nand0=nand0\0"                                          \
 
552
        "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"      \
 
553
        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 
554
                "nfsroot=${serverip}:${rootpath}\0"                     \
 
555
        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 
556
        "addip=setenv bootargs ${bootargs} "                            \
 
557
                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 
558
                ":${hostname}:${netdev}:off panic=1\0"                  \
 
559
        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 
560
        "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "             \
 
561
                "console=ttyS0,115200\0"                                \
 
562
        ""
 
563
 
 
564
#define CONFIG_NFSBOOTCOMMAND                                           \
 
565
        "setenv rootdev /dev/nfs;"                                      \
 
566
        "run setbootargs;"                                              \
 
567
        "run setipargs;"                                                \
 
568
        "tftp $loadaddr $bootfile;"                                     \
 
569
        "tftp $fdtaddr $fdtfile;"                                       \
 
570
        "bootm $loadaddr - $fdtaddr"
 
571
 
 
572
#define CONFIG_RAMBOOTCOMMAND                                           \
 
573
        "setenv rootdev /dev/ram;"                                      \
 
574
        "run setbootargs;"                                              \
 
575
        "tftp $ramdiskaddr $ramdiskfile;"                               \
 
576
        "tftp $loadaddr $bootfile;"                                     \
 
577
        "tftp $fdtaddr $fdtfile;"                                       \
 
578
        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 
579
 
 
580
#endif  /* __CONFIG_H */