96
97
#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
static XICSState *try_create_xics(const char *type, int nr_servers,
99
int nr_irqs, Error **errp)
99
static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics,
100
const char *type_icp, int nr_servers,
101
int nr_irqs, Error **errp)
103
XICSFabric *xi = XICS_FABRIC(spapr);
104
Error *err = NULL, *local_err = NULL;
105
ICSState *ics = NULL;
104
dev = qdev_create(NULL, type);
105
qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106
qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
107
object_property_set_bool(OBJECT(dev), true, "realized", &err);
108
ics = ICS_SIMPLE(object_new(type_ics));
109
object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL);
110
object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err);
111
object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL);
112
object_property_set_bool(OBJECT(ics), true, "realized", &local_err);
113
error_propagate(&err, local_err);
109
error_propagate(errp, err);
110
object_unparent(OBJECT(dev));
113
return XICS_COMMON(dev);
118
spapr->icps = g_malloc0(nr_servers * sizeof(ICPState));
119
spapr->nr_servers = nr_servers;
121
for (i = 0; i < nr_servers; i++) {
122
ICPState *icp = &spapr->icps[i];
124
object_initialize(icp, sizeof(*icp), type_icp);
125
object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL);
126
object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL);
127
object_property_set_bool(OBJECT(icp), true, "realized", &err);
131
object_unref(OBJECT(icp));
138
error_propagate(errp, err);
140
object_unparent(OBJECT(ics));
116
static XICSState *xics_system_init(MachineState *machine,
117
int nr_servers, int nr_irqs, Error **errp)
145
static int xics_system_init(MachineState *machine,
146
int nr_servers, int nr_irqs, Error **errp)
119
XICSState *xics = NULL;
121
150
if (kvm_enabled()) {
122
151
Error *err = NULL;
124
if (machine_kernel_irqchip_allowed(machine)) {
125
xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
153
if (machine_kernel_irqchip_allowed(machine) &&
154
!xics_kvm_init(SPAPR_MACHINE(machine), errp)) {
155
rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM,
156
TYPE_KVM_ICP, nr_servers, nr_irqs, &err);
128
if (machine_kernel_irqchip_required(machine) && !xics) {
158
if (machine_kernel_irqchip_required(machine) && rc < 0) {
129
159
error_reportf_err(err,
130
160
"kernel_irqchip requested but unavailable: ");
356
388
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
357
389
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
358
390
0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
391
/* Currently we don't advertise any of the "new" ISAv3.00 functionality */
392
uint8_t pa_features_300[] = { 64, 0,
393
0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
394
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
395
0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
396
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
397
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
398
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
399
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
400
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
401
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
402
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
403
0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */
359
405
uint8_t *pa_features;
362
switch (env->mmu_model) {
363
case POWERPC_MMU_2_06:
364
case POWERPC_MMU_2_06a:
408
switch (POWERPC_MMU_VER(env->mmu_model)) {
409
case POWERPC_MMU_VER_2_06:
365
410
pa_features = pa_features_206;
366
411
pa_size = sizeof(pa_features_206);
368
case POWERPC_MMU_2_07:
369
case POWERPC_MMU_2_07a:
413
case POWERPC_MMU_VER_2_07:
370
414
pa_features = pa_features_207;
371
415
pa_size = sizeof(pa_features_207);
417
case POWERPC_MMU_VER_3_00:
418
pa_features = pa_features_300;
419
pa_size = sizeof(pa_features_300);
1052
1108
spapr->htab_fd = -1;
1111
static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1113
sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1115
return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1118
static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1121
sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1122
hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1126
* HTAB is controlled by KVM. Fetch into temporary buffer
1128
ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1129
kvmppc_read_hptes(hptes, ptex, n);
1134
* HTAB is controlled by QEMU. Just point to the internally
1137
return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1140
static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1141
const ppc_hash_pte64_t *hptes,
1144
sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1147
g_free((void *)hptes);
1150
/* Nothing to do for qemu managed HPT */
1153
static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1154
uint64_t pte0, uint64_t pte1)
1156
sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1157
hwaddr offset = ptex * HASH_PTE_SIZE_64;
1160
kvmppc_write_hpte(ptex, pte0, pte1);
1162
stq_p(spapr->htab + offset, pte0);
1163
stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1055
1167
static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1896
/* find cpu slot in machine->possible_cpus by core_id */
1897
static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1899
int index = id / smp_threads;
1901
if (index >= ms->possible_cpus->len) {
1907
return &ms->possible_cpus->cpus[index];
1910
static void spapr_init_cpus(sPAPRMachineState *spapr)
1912
MachineState *machine = MACHINE(spapr);
1913
MachineClass *mc = MACHINE_GET_CLASS(machine);
1914
char *type = spapr_get_cpu_core_type(machine->cpu_model);
1915
int smt = kvmppc_smt_threads();
1916
const CPUArchIdList *possible_cpus;
1917
int boot_cores_nr = smp_cpus / smp_threads;
1921
error_report("Unable to find sPAPR CPU Core definition");
1925
possible_cpus = mc->possible_cpu_arch_ids(machine);
1926
if (mc->has_hotpluggable_cpus) {
1927
if (smp_cpus % smp_threads) {
1928
error_report("smp_cpus (%u) must be multiple of threads (%u)",
1929
smp_cpus, smp_threads);
1932
if (max_cpus % smp_threads) {
1933
error_report("max_cpus (%u) must be multiple of threads (%u)",
1934
max_cpus, smp_threads);
1938
if (max_cpus != smp_cpus) {
1939
error_report("This machine version does not support CPU hotplug");
1942
boot_cores_nr = possible_cpus->len;
1945
for (i = 0; i < possible_cpus->len; i++) {
1946
int core_id = i * smp_threads;
1948
if (mc->has_hotpluggable_cpus) {
1949
sPAPRDRConnector *drc =
1950
spapr_dr_connector_new(OBJECT(spapr),
1951
SPAPR_DR_CONNECTOR_TYPE_CPU,
1952
(core_id / smp_threads) * smt);
1954
qemu_register_reset(spapr_drc_reset, drc);
1957
if (i < boot_cores_nr) {
1958
Object *core = object_new(type);
1959
int nr_threads = smp_threads;
1961
/* Handle the partially filled core for older machine types */
1962
if ((i + 1) * smp_threads >= smp_cpus) {
1963
nr_threads = smp_cpus - i * smp_threads;
1966
object_property_set_int(core, nr_threads, "nr-threads",
1968
object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1970
object_property_set_bool(core, true, "realized", &error_fatal);
1756
1976
/* pSeries LPAR / sPAPR hardware init */
1757
1977
static void ppc_spapr_init(MachineState *machine)
1759
1979
sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1760
MachineClass *mc = MACHINE_GET_CLASS(machine);
1761
1980
sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1762
1981
const char *kernel_filename = machine->kernel_filename;
1763
1982
const char *initrd_filename = machine->initrd_filename;
1867
2068
ppc_cpu_parse_features(machine->cpu_model);
1869
if (mc->query_hotpluggable_cpus) {
1870
char *type = spapr_get_cpu_core_type(machine->cpu_model);
1873
error_report("Unable to find sPAPR CPU Core definition");
1877
spapr->cores = g_new0(Object *, spapr_max_cores);
1878
for (i = 0; i < spapr_max_cores; i++) {
1879
int core_id = i * smp_threads;
1880
sPAPRDRConnector *drc =
1881
spapr_dr_connector_new(OBJECT(spapr),
1882
SPAPR_DR_CONNECTOR_TYPE_CPU,
1883
(core_id / smp_threads) * smt);
1885
qemu_register_reset(spapr_drc_reset, drc);
1887
if (i < spapr_cores) {
1888
Object *core = object_new(type);
1889
object_property_set_int(core, smp_threads, "nr-threads",
1891
object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1893
object_property_set_bool(core, true, "realized", &error_fatal);
1898
for (i = 0; i < smp_cpus; i++) {
1899
PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1901
error_report("Unable to find PowerPC CPU definition");
1904
spapr_cpu_init(spapr, cpu, &error_fatal);
2070
spapr_init_cpus(spapr);
1908
2072
if (kvm_enabled()) {
1909
2073
/* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2650
static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2653
MachineState *ms = MACHINE(qdev_get_machine());
2654
CPUCore *cc = CPU_CORE(dev);
2655
CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2657
core_slot->cpu = NULL;
2658
object_unparent(OBJECT(dev));
2661
static void spapr_core_release(DeviceState *dev, void *opaque)
2663
HotplugHandler *hotplug_ctrl;
2665
hotplug_ctrl = qdev_get_hotplug_handler(dev);
2666
hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2670
void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2674
sPAPRDRConnector *drc;
2675
sPAPRDRConnectorClass *drck;
2676
Error *local_err = NULL;
2677
CPUCore *cc = CPU_CORE(dev);
2678
int smt = kvmppc_smt_threads();
2680
if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2681
error_setg(errp, "Unable to find CPU core with core-id: %d",
2686
error_setg(errp, "Boot CPU core may not be unplugged");
2690
drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2693
drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2694
drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
2696
error_propagate(errp, local_err);
2700
spapr_hotplug_req_remove_by_index(drc);
2703
static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2706
sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2707
MachineClass *mc = MACHINE_GET_CLASS(spapr);
2708
sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2709
CPUCore *cc = CPU_CORE(dev);
2710
CPUState *cs = CPU(core->threads);
2711
sPAPRDRConnector *drc;
2712
Error *local_err = NULL;
2715
int smt = kvmppc_smt_threads();
2716
CPUArchId *core_slot;
2719
core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2721
error_setg(errp, "Unable to find CPU core with core-id: %d",
2725
drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2727
g_assert(drc || !mc->has_hotpluggable_cpus);
2730
* Setup CPU DT entries only for hotplugged CPUs. For boot time or
2731
* coldplugged CPUs DT entries are setup in spapr_build_fdt().
2733
if (dev->hotplugged) {
2734
fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2738
sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2739
drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2742
error_propagate(errp, local_err);
2747
if (dev->hotplugged) {
2749
* Send hotplug notification interrupt to the guest only in case
2750
* of hotplugged CPUs.
2752
spapr_hotplug_req_add_by_index(drc);
2755
* Set the right DRC states for cold plugged CPU.
2758
sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2759
drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2760
drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2763
core_slot->cpu = OBJECT(dev);
2766
static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2769
MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2770
MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2771
Error *local_err = NULL;
2772
CPUCore *cc = CPU_CORE(dev);
2773
char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2774
const char *type = object_get_typename(OBJECT(dev));
2775
CPUArchId *core_slot;
2778
if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2779
error_setg(&local_err, "CPU hotplug not supported for this machine");
2783
if (strcmp(base_core_type, type)) {
2784
error_setg(&local_err, "CPU core type should be %s", base_core_type);
2788
if (cc->core_id % smp_threads) {
2789
error_setg(&local_err, "invalid core id %d", cc->core_id);
2793
if (cc->nr_threads != smp_threads) {
2794
error_setg(errp, "invalid nr-threads %d, must be %d",
2795
cc->nr_threads, smp_threads);
2799
core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2801
error_setg(&local_err, "core id %d out of range", cc->core_id);
2805
if (core_slot->cpu) {
2806
error_setg(&local_err, "core %d already populated", cc->core_id);
2811
g_free(base_core_type);
2812
error_propagate(errp, local_err);
2459
2815
static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2460
2816
DeviceState *dev, Error **errp)
2578
2934
return cpu_index / smp_threads / smp_cores;
2581
static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2937
static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
2584
HotpluggableCPUList *head = NULL;
2585
sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2586
2940
int spapr_max_cores = max_cpus / smp_threads;
2588
for (i = 0; i < spapr_max_cores; i++) {
2589
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2590
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2591
CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2593
cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2594
cpu_item->vcpus_count = smp_threads;
2595
cpu_props->has_core_id = true;
2596
cpu_props->core_id = i * smp_threads;
2941
MachineClass *mc = MACHINE_GET_CLASS(machine);
2943
if (!mc->has_hotpluggable_cpus) {
2944
spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
2946
if (machine->possible_cpus) {
2947
assert(machine->possible_cpus->len == spapr_max_cores);
2948
return machine->possible_cpus;
2951
machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2952
sizeof(CPUArchId) * spapr_max_cores);
2953
machine->possible_cpus->len = spapr_max_cores;
2954
for (i = 0; i < machine->possible_cpus->len; i++) {
2955
int core_id = i * smp_threads;
2957
machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
2958
machine->possible_cpus->cpus[i].arch_id = core_id;
2959
machine->possible_cpus->cpus[i].props.has_core_id = true;
2960
machine->possible_cpus->cpus[i].props.core_id = core_id;
2597
2961
/* TODO: add 'has_node/node' here to describe
2598
2962
to which node core belongs */
2600
cpu_item->props = cpu_props;
2601
if (spapr->cores[i]) {
2602
cpu_item->has_qom_path = true;
2603
cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2605
list_item->value = cpu_item;
2606
list_item->next = head;
2964
return machine->possible_cpus;
2612
2967
static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2659
3016
*mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3019
static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3021
sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3023
return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3026
static void spapr_ics_resend(XICSFabric *dev)
3028
sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3030
ics_resend(spapr->ics);
3033
static ICPState *spapr_icp_get(XICSFabric *xi, int server)
3035
sPAPRMachineState *spapr = SPAPR_MACHINE(xi);
3037
return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL;
3040
static void spapr_pic_print_info(InterruptStatsProvider *obj,
3043
sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3046
for (i = 0; i < spapr->nr_servers; i++) {
3047
icp_pic_print_info(&spapr->icps[i], mon);
3050
ics_pic_print_info(spapr->ics, mon);
2662
3053
static void spapr_machine_class_init(ObjectClass *oc, void *data)
2664
3055
MachineClass *mc = MACHINE_CLASS(oc);
2689
3083
hc->plug = spapr_machine_device_plug;
2690
3084
hc->unplug = spapr_machine_device_unplug;
2691
3085
mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
3086
mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
2692
3087
hc->unplug_request = spapr_machine_device_unplug_request;
2694
3089
smc->dr_lmb_enabled = true;
2695
3090
smc->tcg_default_cpu = "POWER8";
2696
mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
3091
mc->has_hotpluggable_cpus = true;
2697
3092
fwc->get_dev_path = spapr_get_fw_dev_path;
2698
3093
nc->nmi_monitor_handler = spapr_nmi;
2699
3094
smc->phb_placement = spapr_phb_placement;
3095
vhc->hypercall = emulate_spapr_hypercall;
3096
vhc->hpt_mask = spapr_hpt_mask;
3097
vhc->map_hptes = spapr_map_hptes;
3098
vhc->unmap_hptes = spapr_unmap_hptes;
3099
vhc->store_hpte = spapr_store_hpte;
3100
vhc->get_patbe = spapr_get_patbe;
3101
xic->ics_get = spapr_ics_get;
3102
xic->ics_resend = spapr_ics_resend;
3103
xic->icp_get = spapr_icp_get;
3104
ispc->print_info = spapr_pic_print_info;
3105
/* Force NUMA node memory size to be a multiple of
3106
* SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3107
* in which LMBs are represented and hot-added
3109
mc->numa_mem_align_shift = 28;
2702
3112
static const TypeInfo spapr_machine_info = {
2745
3158
type_init(spapr_machine_register_##suffix)
3163
static void spapr_machine_2_9_instance_options(MachineState *machine)
3167
static void spapr_machine_2_9_class_options(MachineClass *mc)
3169
/* Defaults for the latest behaviour inherited from the base class */
3172
DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
3177
#define SPAPR_COMPAT_2_8 \
3180
.driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3181
.property = "pcie-extended-configuration-space", \
2750
3185
static void spapr_machine_2_8_instance_options(MachineState *machine)
3187
spapr_machine_2_9_instance_options(machine);
2754
3190
static void spapr_machine_2_8_class_options(MachineClass *mc)
2756
/* Defaults for the latest behaviour inherited from the base class */
3192
spapr_machine_2_9_class_options(mc);
3193
SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3194
mc->numa_mem_align_shift = 23;
2759
DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
3197
DEFINE_SPAPR_MACHINE(2_8, "2.8", false);