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// Support for generating ACPI tables (on emulators)
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// DO NOT ADD NEW FEATURES HERE. (See paravirt.c / biostables.c instead.)
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// Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2006 Fabrice Bellard
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "byteorder.h" // cpu_to_le16
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#include "config.h" // CONFIG_*
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#include "hw/pcidevice.h" // pci_find_init_device
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#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
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#include "hw/pci_regs.h" // PCI_INTERRUPT_LINE
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#include "malloc.h" // free
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#include "output.h" // dprintf
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#include "paravirt.h" // RamSize
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#include "romfile.h" // romfile_loadint
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#include "std/acpi.h" // struct rsdp_descriptor
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#include "string.h" // memset
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#include "util.h" // MaxCountCPUs
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#include "x86.h" // readl
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#include "fw/acpi-dsdt.hex"
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build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
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h->signature = cpu_to_le32(sig);
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h->length = cpu_to_le32(len);
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memcpy(h->oem_id, BUILD_APPNAME6, 6);
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memcpy(h->oem_table_id, BUILD_APPNAME4, 4);
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memcpy(h->oem_table_id + 4, (void*)&sig, 4);
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h->oem_revision = cpu_to_le32(1);
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memcpy(h->asl_compiler_id, BUILD_APPNAME4, 4);
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h->asl_compiler_revision = cpu_to_le32(1);
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h->checksum -= checksum(h, len);
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static void piix4_fadt_setup(struct pci_device *pci, void *arg)
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struct fadt_descriptor_rev1 *fadt = arg;
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fadt->sci_int = cpu_to_le16(PIIX_PM_INTRRUPT);
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fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
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fadt->acpi_enable = PIIX_ACPI_ENABLE;
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fadt->acpi_disable = PIIX_ACPI_DISABLE;
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fadt->pm1a_evt_blk = cpu_to_le32(acpi_pm_base);
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fadt->pm1a_cnt_blk = cpu_to_le32(acpi_pm_base + 0x04);
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fadt->pm_tmr_blk = cpu_to_le32(acpi_pm_base + 0x08);
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fadt->gpe0_blk = cpu_to_le32(PIIX_GPE0_BLK);
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->gpe0_blk_len = PIIX_GPE0_BLK_LEN;
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fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
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fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
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fadt->flags = cpu_to_le32(ACPI_FADT_F_WBINVD |
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ACPI_FADT_F_SLP_BUTTON |
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ACPI_FADT_F_USE_PLATFORM_CLOCK);
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/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
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static void ich9_lpc_fadt_setup(struct pci_device *dev, void *arg)
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struct fadt_descriptor_rev1 *fadt = arg;
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fadt->sci_int = cpu_to_le16(9);
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fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
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fadt->acpi_enable = ICH9_ACPI_ENABLE;
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fadt->acpi_disable = ICH9_ACPI_DISABLE;
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fadt->pm1a_evt_blk = cpu_to_le32(acpi_pm_base);
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fadt->pm1a_cnt_blk = cpu_to_le32(acpi_pm_base + 0x04);
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fadt->pm_tmr_blk = cpu_to_le32(acpi_pm_base + 0x08);
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fadt->gpe0_blk = cpu_to_le32(acpi_pm_base + ICH9_PMIO_GPE0_STS);
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN;
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fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
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fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
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fadt->flags = cpu_to_le32(ACPI_FADT_F_WBINVD |
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ACPI_FADT_F_SLP_BUTTON |
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ACPI_FADT_F_USE_PLATFORM_CLOCK);
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static const struct pci_device_id fadt_init_tbl[] = {
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/* PIIX4 Power Management device (for ACPI) */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
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ich9_lpc_fadt_setup),
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static void fill_dsdt(struct fadt_descriptor_rev1 *fadt, void *dsdt)
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free((void *)le32_to_cpu(fadt->dsdt));
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fadt->dsdt = cpu_to_le32((u32)dsdt);
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fadt->checksum -= checksum(fadt, sizeof(*fadt));
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dprintf(1, "ACPI DSDT=%p\n", dsdt);
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build_fadt(struct pci_device *pci)
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struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
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struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
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if (!fadt || !facs) {
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memset(facs, 0, sizeof(*facs));
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facs->signature = cpu_to_le32(FACS_SIGNATURE);
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facs->length = cpu_to_le32(sizeof(*facs));
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memset(fadt, 0, sizeof(*fadt));
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fadt->firmware_ctrl = cpu_to_le32((u32)facs);
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fadt->dsdt = 0; /* dsdt will be filled later in acpi_setup()
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pci_init_device(fadt_init_tbl, pci, fadt);
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build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
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int madt_size = (sizeof(struct multiple_apic_table)
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+ sizeof(struct madt_processor_apic) * MaxCountCPUs
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+ sizeof(struct madt_io_apic)
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+ sizeof(struct madt_intsrcovr) * 16
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+ sizeof(struct madt_local_nmi));
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struct multiple_apic_table *madt = malloc_high(madt_size);
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memset(madt, 0, madt_size);
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madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
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madt->flags = cpu_to_le32(1);
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struct madt_processor_apic *apic = (void*)&madt[1];
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for (i=0; i<MaxCountCPUs; i++) {
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apic->type = APIC_PROCESSOR;
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apic->length = sizeof(*apic);
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apic->processor_id = i;
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apic->local_apic_id = i;
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if (apic_id_is_present(apic->local_apic_id))
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apic->flags = cpu_to_le32(1);
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apic->flags = cpu_to_le32(0);
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struct madt_io_apic *io_apic = (void*)apic;
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io_apic->type = APIC_IO;
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io_apic->length = sizeof(*io_apic);
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io_apic->io_apic_id = BUILD_IOAPIC_ID;
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io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
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io_apic->interrupt = cpu_to_le32(0);
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struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
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if (romfile_loadint("etc/irq0-override", 0)) {
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memset(intsrcovr, 0, sizeof(*intsrcovr));
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intsrcovr->type = APIC_XRUPT_OVERRIDE;
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intsrcovr->length = sizeof(*intsrcovr);
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intsrcovr->source = 0;
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intsrcovr->gsi = cpu_to_le32(2);
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intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
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for (i = 1; i < 16; i++) {
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if (!(BUILD_PCI_IRQS & (1 << i)))
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/* No need for a INT source override structure. */
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memset(intsrcovr, 0, sizeof(*intsrcovr));
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intsrcovr->type = APIC_XRUPT_OVERRIDE;
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intsrcovr->length = sizeof(*intsrcovr);
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intsrcovr->source = i;
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intsrcovr->gsi = cpu_to_le32(i);
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intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
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struct madt_local_nmi *local_nmi = (void*)intsrcovr;
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local_nmi->type = APIC_LOCAL_NMI;
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local_nmi->length = sizeof(*local_nmi);
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local_nmi->processor_id = 0xff; /* all processors */
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local_nmi->flags = cpu_to_le16(0);
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local_nmi->lint = 1; /* LINT1 */
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build_header((void*)madt, APIC_SIGNATURE, (void*)local_nmi - (void*)madt, 1);
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// Encode a hex value
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static inline char getHex(u32 val) {
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return (val <= 9) ? ('0' + val) : ('A' + val - 10);
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// Encode a length in an SSDT.
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encodeLen(u8 *ssdt_ptr, int length, int bytes)
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case 4: ssdt_ptr[3] = ((length >> 20) & 0xff);
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case 3: ssdt_ptr[2] = ((length >> 12) & 0xff);
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case 2: ssdt_ptr[1] = ((length >> 4) & 0xff);
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ssdt_ptr[0] = (((bytes-1) & 0x3) << 6) | (length & 0x0f);
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case 1: ssdt_ptr[0] = length & 0x3f;
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return ssdt_ptr + bytes;
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#include "fw/ssdt-proc.hex"
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/* 0x5B 0x83 ProcessorOp PkgLength NameString ProcID */
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#define PROC_OFFSET_CPUHEX (*ssdt_proc_name - *ssdt_proc_start + 2)
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#define PROC_OFFSET_CPUID1 (*ssdt_proc_name - *ssdt_proc_start + 4)
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#define PROC_OFFSET_CPUID2 (*ssdt_proc_id - *ssdt_proc_start)
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#define PROC_SIZEOF (*ssdt_proc_end - *ssdt_proc_start)
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#define PROC_AML (ssdp_proc_aml + *ssdt_proc_start)
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/* 0x5B 0x82 DeviceOp PkgLength NameString */
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#define PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
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#define PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
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#define PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
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#define PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
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#define PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
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#define PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
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#define SSDT_SIGNATURE 0x54445353 // SSDT
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#define SSDT_HEADER_LENGTH 36
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#include "fw/ssdt-misc.hex"
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#include "fw/ssdt-pcihp.hex"
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#define PCI_RMV_BASE 0xae0c
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build_notify(u8 *ssdt_ptr, const char *name, int skip, int count,
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const char *target, int ofs)
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*(ssdt_ptr++) = 0x14; // MethodOp
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ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*count), 2);
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memcpy(ssdt_ptr, name, 4);
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*(ssdt_ptr++) = 0x02; // MethodOp
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for (i = skip; count-- > 0; i++) {
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*(ssdt_ptr++) = 0xA0; // IfOp
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ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
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*(ssdt_ptr++) = 0x93; // LEqualOp
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*(ssdt_ptr++) = 0x68; // Arg0Op
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*(ssdt_ptr++) = 0x0A; // BytePrefix
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*(ssdt_ptr++) = 0x86; // NotifyOp
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memcpy(ssdt_ptr, target, 4);
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ssdt_ptr[ofs] = getHex(i >> 4);
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ssdt_ptr[ofs + 1] = getHex(i);
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*(ssdt_ptr++) = 0x69; // Arg1Op
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static void patch_pcihp(int slot, u8 *ssdt_ptr, u32 eject)
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ssdt_ptr[PCIHP_OFFSET_HEX] = getHex(slot >> 4);
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ssdt_ptr[PCIHP_OFFSET_HEX+1] = getHex(slot);
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ssdt_ptr[PCIHP_OFFSET_ID] = slot;
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ssdt_ptr[PCIHP_OFFSET_ADR + 2] = slot;
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/* Runtime patching of EJ0: to disable hotplug for a slot,
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* replace the method name: _EJ0 by EJ0_. */
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if (memcmp(ssdt_ptr + PCIHP_OFFSET_EJ0, "_EJ0", 4)) {
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warn_internalerror();
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memcpy(ssdt_ptr + PCIHP_OFFSET_EJ0, "EJ0_", 4);
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int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
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int length = (sizeof(ssdp_misc_aml) // _S3_ / _S4_ / _S5_
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+ (1+3+4) // Scope(_SB_)
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+ (acpi_cpus * PROC_SIZEOF) // procs
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+ (1+2+5+(12*acpi_cpus)) // NTFY
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+ (6+2+1+(1*acpi_cpus)) // CPON
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+ (1+3+4) // Scope(PCI0)
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+ ((PCI_SLOTS - 1) * PCIHP_SIZEOF) // slots
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+ (1+2+5+(12*(PCI_SLOTS - 1)))); // PCNT
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u8 *ssdt = malloc_high(length);
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// Copy header and encode fwcfg values in the S3_ / S4_ / S5_ packages
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char *sys_states = romfile_loadfile("etc/system-states", &sys_state_size);
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if (!sys_states || sys_state_size != 6)
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sys_states = (char[]){128, 0, 0, 129, 128, 128};
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memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
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if (!(sys_states[3] & 128))
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ssdt_ptr[acpi_s3_name[0]] = 'X';
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if (!(sys_states[4] & 128))
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ssdt_ptr[acpi_s4_name[0]] = 'X';
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ssdt_ptr[acpi_s4_pkg[0] + 1] = ssdt[acpi_s4_pkg[0] + 3] = sys_states[4] & 127;
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// store pci io windows
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*(u32*)&ssdt_ptr[acpi_pci32_start[0]] = cpu_to_le32(pcimem_start);
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*(u32*)&ssdt_ptr[acpi_pci32_end[0]] = cpu_to_le32(pcimem_end - 1);
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if (pcimem64_start) {
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ssdt_ptr[acpi_pci64_valid[0]] = 1;
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*(u64*)&ssdt_ptr[acpi_pci64_start[0]] = cpu_to_le64(pcimem64_start);
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*(u64*)&ssdt_ptr[acpi_pci64_end[0]] = cpu_to_le64(pcimem64_end - 1);
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*(u64*)&ssdt_ptr[acpi_pci64_length[0]] = cpu_to_le64(
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pcimem64_end - pcimem64_start);
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ssdt_ptr[acpi_pci64_valid[0]] = 0;
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int pvpanic_port = romfile_loadint("etc/pvpanic-port", 0x0);
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*(u16 *)(ssdt_ptr + *ssdt_isa_pest) = pvpanic_port;
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ssdt_ptr += sizeof(ssdp_misc_aml);
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// build Scope(_SB_) header
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*(ssdt_ptr++) = 0x10; // ScopeOp
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ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 3);
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// build Processor object for each processor
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for (i=0; i<acpi_cpus; i++) {
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memcpy(ssdt_ptr, PROC_AML, PROC_SIZEOF);
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ssdt_ptr[PROC_OFFSET_CPUHEX] = getHex(i >> 4);
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ssdt_ptr[PROC_OFFSET_CPUHEX+1] = getHex(i);
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ssdt_ptr[PROC_OFFSET_CPUID1] = i;
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ssdt_ptr[PROC_OFFSET_CPUID2] = i;
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ssdt_ptr += PROC_SIZEOF;
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// build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}"
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// Arg0 = Processor ID = APIC ID
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ssdt_ptr = build_notify(ssdt_ptr, "NTFY", 0, acpi_cpus, "CP00", 2);
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// build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
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*(ssdt_ptr++) = 0x08; // NameOp
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*(ssdt_ptr++) = 0x12; // PackageOp
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ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2);
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*(ssdt_ptr++) = acpi_cpus;
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for (i=0; i<acpi_cpus; i++)
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*(ssdt_ptr++) = (apic_id_is_present(i)) ? 0x01 : 0x00;
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// build Scope(PCI0) opcode
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*(ssdt_ptr++) = 0x10; // ScopeOp
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ssdt_ptr = encodeLen(ssdt_ptr, length - (ssdt_ptr - ssdt), 3);
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// build Device object for each slot
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u32 rmvc_pcrm = inl(PCI_RMV_BASE);
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for (i=1; i<PCI_SLOTS; i++) {
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u32 eject = rmvc_pcrm & (0x1 << i);
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memcpy(ssdt_ptr, PCIHP_AML, PCIHP_SIZEOF);
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patch_pcihp(i, ssdt_ptr, eject != 0);
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ssdt_ptr += PCIHP_SIZEOF;
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ssdt_ptr = build_notify(ssdt_ptr, "PCNT", 1, PCI_SLOTS, "S00_", 1);
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build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
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//hexdump(ssdt, ssdt_ptr - ssdt);
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#define HPET_ID 0x000
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#define HPET_PERIOD 0x004
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struct acpi_20_hpet *hpet;
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const void *hpet_base = (void *)BUILD_HPET_ADDRESS;
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u32 hpet_vendor = readl(hpet_base + HPET_ID) >> 16;
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u32 hpet_period = readl(hpet_base + HPET_PERIOD);
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if (hpet_vendor == 0 || hpet_vendor == 0xffff ||
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hpet_period == 0 || hpet_period > 100000000)
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hpet = malloc_high(sizeof(*hpet));
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memset(hpet, 0, sizeof(*hpet));
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/* Note timer_block_id value must be kept in sync with value advertised by
449
hpet->timer_block_id = cpu_to_le32(0x8086a201);
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hpet->addr.address = cpu_to_le64(BUILD_HPET_ADDRESS);
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build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
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acpi_build_srat_memory(struct srat_memory_affinity *numamem,
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u64 base, u64 len, int node, int enabled)
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numamem->type = SRAT_MEMORY;
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numamem->length = sizeof(*numamem);
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memset(numamem->proximity, 0, 4);
463
numamem->proximity[0] = node;
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numamem->flags = cpu_to_le32(!!enabled);
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numamem->base_addr = cpu_to_le64(base);
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numamem->range_length = cpu_to_le64(len);
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int numadatasize, numacpusize;
473
u64 *numadata = romfile_loadfile("etc/numa-nodes", &numadatasize);
474
u64 *numacpumap = romfile_loadfile("etc/numa-cpu-map", &numacpusize);
475
if (!numadata || !numacpumap)
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int max_cpu = numacpusize / sizeof(u64);
478
int nb_numa_nodes = numadatasize / sizeof(u64);
480
struct system_resource_affinity_table *srat;
481
int srat_size = sizeof(*srat) +
482
sizeof(struct srat_processor_affinity) * max_cpu +
483
sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
485
srat = malloc_high(srat_size);
491
memset(srat, 0, srat_size);
492
srat->reserved1=cpu_to_le32(1);
493
struct srat_processor_affinity *core = (void*)(srat + 1);
497
for (i = 0; i < max_cpu; ++i) {
498
core->type = SRAT_PROCESSOR;
499
core->length = sizeof(*core);
500
core->local_apic_id = i;
501
curnode = *numacpumap++;
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core->proximity_lo = curnode;
503
memset(core->proximity_hi, 0, 3);
504
core->local_sapic_eid = 0;
505
if (apic_id_is_present(i))
506
core->flags = cpu_to_le32(1);
508
core->flags = cpu_to_le32(0);
513
/* the memory map is a bit tricky, it contains at least one hole
514
* from 640k-1M and possibly another one from 3.5G-4G.
516
struct srat_memory_affinity *numamem = (void*)core;
518
u64 mem_len, mem_base, next_base = 0;
520
acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
521
next_base = 1024 * 1024;
524
for (i = 1; i < nb_numa_nodes + 1; ++i) {
525
mem_base = next_base;
526
mem_len = *numadata++;
528
mem_len -= 1024 * 1024;
529
next_base = mem_base + mem_len;
531
/* Cut out the PCI hole */
532
if (mem_base <= RamSize && next_base > RamSize) {
533
mem_len -= next_base - RamSize;
535
acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
539
mem_base = 1ULL << 32;
540
mem_len = next_base - RamSize;
541
next_base += (1ULL << 32) - RamSize;
543
acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
547
for (; slots < nb_numa_nodes + 2; slots++) {
548
acpi_build_srat_memory(numamem, 0, 0, 0, 0);
552
build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
566
struct acpi_table_mcfg *mcfg;
568
int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
569
mcfg = malloc_high(len);
574
memset(mcfg, 0, len);
575
mcfg->allocation[0].address = cpu_to_le64(Q35_HOST_BRIDGE_PCIEXBAR_ADDR);
576
mcfg->allocation[0].pci_segment = cpu_to_le16(Q35_HOST_PCIE_PCI_SEGMENT);
577
mcfg->allocation[0].start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER;
578
mcfg->allocation[0].end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER;
580
build_header((void *)mcfg, MCFG_SIGNATURE, len, 1);
584
static const struct pci_device_id acpi_find_tbl[] = {
585
/* PIIX4 Power Management device. */
586
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
587
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, NULL),
591
#define MAX_ACPI_TABLES 20
598
dprintf(3, "init ACPI tables\n");
600
// This code is hardcoded for PIIX4 Power Management device.
601
struct pci_device *pci = pci_find_init_device(acpi_find_tbl, NULL);
607
u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
609
#define ACPI_INIT_TABLE(X) \
611
tables[tbl_idx] = cpu_to_le32((u32)(X)); \
612
if (le32_to_cpu(tables[tbl_idx])) \
616
struct fadt_descriptor_rev1 *fadt = build_fadt(pci);
617
ACPI_INIT_TABLE(fadt);
618
ACPI_INIT_TABLE(build_ssdt());
619
ACPI_INIT_TABLE(build_madt());
620
ACPI_INIT_TABLE(build_hpet());
621
ACPI_INIT_TABLE(build_srat());
622
if (pci->device == PCI_DEVICE_ID_INTEL_ICH9_LPC)
623
ACPI_INIT_TABLE(build_mcfg_q35());
625
struct romfile_s *file = NULL;
627
file = romfile_findprefix("acpi/", file);
630
struct acpi_table_header *table = malloc_high(file->size);
635
int ret = file->copy(file, table, file->size);
636
if (ret <= sizeof(*table))
638
if (table->signature == DSDT_SIGNATURE) {
640
fill_dsdt(fadt, table);
643
ACPI_INIT_TABLE(table);
645
if (tbl_idx == MAX_ACPI_TABLES) {
651
if (CONFIG_ACPI_DSDT && fadt && !fadt->dsdt) {
653
struct acpi_table_header *dsdt = malloc_high(sizeof(AmlCode));
658
memcpy(dsdt, AmlCode, sizeof(AmlCode));
659
fill_dsdt(fadt, dsdt);
660
/* Strip out compiler-generated header if any */
661
memset(dsdt, 0, sizeof *dsdt);
662
build_header(dsdt, DSDT_SIGNATURE, sizeof(AmlCode), 1);
665
// Build final rsdt table
666
struct rsdt_descriptor_rev1 *rsdt;
667
size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
668
rsdt = malloc_high(rsdt_len);
673
memset(rsdt, 0, rsdt_len);
674
memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
675
build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
677
// Build rsdp pointer table
678
struct rsdp_descriptor rsdp;
679
memset(&rsdp, 0, sizeof(rsdp));
680
rsdp.signature = cpu_to_le64(RSDP_SIGNATURE);
681
memcpy(rsdp.oem_id, BUILD_APPNAME6, 6);
682
rsdp.rsdt_physical_address = cpu_to_le32((u32)rsdt);
683
rsdp.checksum -= checksum(&rsdp, 20);
684
copy_acpi_rsdp(&rsdp);