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Viewing changes to roms/u-boot/board/freescale/mx53smd/mx53smd.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/mx53smd/mx53smd.c
 
1
/*
 
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 * (C) Copyright 2011 Freescale Semiconductor, Inc.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/io.h>
 
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#include <asm/arch/imx-regs.h>
 
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#include <asm/arch/sys_proto.h>
 
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#include <asm/arch/crm_regs.h>
 
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#include <asm/arch/clock.h>
 
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#include <asm/arch/iomux-mx53.h>
 
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#include <asm/errno.h>
 
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#include <netdev.h>
 
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#include <mmc.h>
 
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#include <fsl_esdhc.h>
 
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#include <asm/gpio.h>
 
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DECLARE_GLOBAL_DATA_PTR;
 
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int dram_init(void)
 
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{
 
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        u32 size1, size2;
 
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        size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 
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        size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 
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        gd->ram_size = size1 + size2;
 
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        return 0;
 
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}
 
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void dram_init_banksize(void)
 
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{
 
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        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 
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        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
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        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 
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        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 
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}
 
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#define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 
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                         PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 
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static void setup_iomux_uart(void)
 
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{
 
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        static const iomux_v3_cfg_t uart_pads[] = {
 
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                NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
 
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                NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
 
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        };
 
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        imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 
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}
 
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static void setup_iomux_fec(void)
 
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{
 
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        static const iomux_v3_cfg_t fec_pads[] = {
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
 
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                        PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 
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                                PAD_CTL_HYS | PAD_CTL_PKE),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 
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                                PAD_CTL_HYS | PAD_CTL_PKE),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 
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                                PAD_CTL_HYS | PAD_CTL_PKE),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 
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                                PAD_CTL_HYS | PAD_CTL_PKE),
 
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                NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 
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                                PAD_CTL_HYS | PAD_CTL_PKE),
 
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        };
 
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        imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
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}
 
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#ifdef CONFIG_FSL_ESDHC
 
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
 
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        {MMC_SDHC1_BASE_ADDR},
 
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};
 
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int board_mmc_getcd(struct mmc *mmc)
 
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{
 
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        imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 
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        gpio_direction_input(IMX_GPIO_NR(3, 13));
 
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        return !gpio_get_value(IMX_GPIO_NR(3, 13));
 
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}
 
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#define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 
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                                 PAD_CTL_PUS_100K_UP)
 
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#define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 
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                                 PAD_CTL_DSE_HIGH)
 
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int board_mmc_init(bd_t *bis)
 
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{
 
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        static const iomux_v3_cfg_t sd1_pads[] = {
 
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                NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 
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                NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 
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                NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 
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                NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 
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                NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 
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                NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 
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                MX53_PAD_EIM_DA13__GPIO3_13,
 
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        };
 
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        u32 index;
 
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        s32 status = 0;
 
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        esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 
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        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 
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                switch (index) {
 
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                case 0:
 
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                        imx_iomux_v3_setup_multiple_pads(sd1_pads,
 
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                                                         ARRAY_SIZE(sd1_pads));
 
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                        break;
 
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                default:
 
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                        printf("Warning: you configured more ESDHC controller"
 
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                                "(%d) as supported by the board(1)\n",
 
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                                CONFIG_SYS_FSL_ESDHC_NUM);
 
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                        return status;
 
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                }
 
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                status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 
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        }
 
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        return status;
 
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}
 
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#endif
 
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int board_early_init_f(void)
 
134
{
 
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        setup_iomux_uart();
 
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        setup_iomux_fec();
 
137
 
 
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        return 0;
 
139
}
 
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int board_init(void)
 
142
{
 
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        /* address of boot parameters */
 
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        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
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146
        return 0;
 
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}
 
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int checkboard(void)
 
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{
 
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        puts("Board: MX53SMD\n");
 
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        return 0;
 
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}