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Viewing changes to roms/u-boot/board/freescale/mpc8568mds/tlb.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/mpc8568mds/tlb.c
 
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/*
 
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 * Copyright 2008 Freescale Semiconductor, Inc.
 
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 *
 
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 * (C) Copyright 2000
 
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 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/mmu.h>
 
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struct fsl_e_tlb_entry tlb_table[] = {
 
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        /* TLB 0 - for temp stack in cache */
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 0, BOOKE_PAGESZ_4K, 0),
 
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        /* TLB 1 Initializations */
 
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        /*
 
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         * TLBe 0:      16M     Non-cacheable, guarded
 
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         * 0xff000000   16M     FLASH (upper half)
 
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         * Out of reset this entry is only 4K.
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 0, BOOKE_PAGESZ_16M, 1),
 
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        /*
 
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         * TLBe 1:      16M     Non-cacheable, guarded
 
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         * 0xfe000000   16M     FLASH (lower half)
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 1, BOOKE_PAGESZ_16M, 1),
 
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        /*
 
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         * TLBe 2:      1G      Non-cacheable, guarded
 
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         * 0x80000000   512M    PCI1 MEM
 
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         * 0xa0000000   512M    PCIe MEM
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 2, BOOKE_PAGESZ_1G, 1),
 
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        /*
 
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         * TLBe 3:      64M     Non-cacheable, guarded
 
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         * 0xe000_0000  1M      CCSRBAR
 
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         * 0xe200_0000  8M      PCI1 IO
 
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         * 0xe280_0000  8M      PCIe IO
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 3, BOOKE_PAGESZ_64M, 1),
 
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        /*
 
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         * TLBe 4:      64M     Cacheable, non-guarded
 
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         * 0xf000_0000  64M     LBC SDRAM
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                      0, 4, BOOKE_PAGESZ_64M, 1),
 
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        /*
 
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         * TLBe 5:      256K    Non-cacheable, guarded
 
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         * 0xf8000000   32K BCSR
 
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         * 0xf8008000   32K PIB (CS4)
 
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         * 0xf8010000   32K PIB (CS5)
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
 
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                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                      0, 5, BOOKE_PAGESZ_256K, 1),
 
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};
 
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int num_tlb_entries = ARRAY_SIZE(tlb_table);