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Viewing changes to roms/u-boot/board/freescale/t208xqds/ddr.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/t208xqds/ddr.c
 
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/*
 
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 * Copyright 2013 Freescale Semiconductor, Inc.
 
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 *
 
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 * This program is free software; you can redistribute it and/or
 
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 * modify it under the terms of the GNU General Public License
 
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 * Version 2 or later as published by the Free Software Foundation.
 
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 */
 
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#include <common.h>
 
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#include <i2c.h>
 
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#include <hwconfig.h>
 
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#include <asm/mmu.h>
 
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#include <fsl_ddr_sdram.h>
 
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#include <fsl_ddr_dimm_params.h>
 
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#include <asm/fsl_law.h>
 
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#include "ddr.h"
 
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DECLARE_GLOBAL_DATA_PTR;
 
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void fsl_ddr_board_options(memctl_options_t *popts,
 
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                                dimm_params_t *pdimm,
 
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                                unsigned int ctrl_num)
 
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{
 
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        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 
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        ulong ddr_freq;
 
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        if (ctrl_num > 1) {
 
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                printf("Not supported controller number %d\n", ctrl_num);
 
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                return;
 
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        }
 
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        if (!pdimm->n_ranks)
 
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                return;
 
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        /*
 
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         * we use identical timing for all slots. If needed, change the code
 
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         * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
 
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         */
 
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        if (popts->registered_dimm_en)
 
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                pbsp = rdimms[0];
 
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        else
 
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                pbsp = udimms[0];
 
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        /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
 
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         * freqency and n_banks specified in board_specific_parameters table.
 
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         */
 
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        ddr_freq = get_ddr_freq(0) / 1000000;
 
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        while (pbsp->datarate_mhz_high) {
 
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                if (pbsp->n_ranks == pdimm->n_ranks &&
 
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                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
 
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                        if (ddr_freq <= pbsp->datarate_mhz_high) {
 
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                                popts->clk_adjust = pbsp->clk_adjust;
 
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                                popts->wrlvl_start = pbsp->wrlvl_start;
 
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                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 
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                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 
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                                goto found;
 
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                        }
 
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                        pbsp_highest = pbsp;
 
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                }
 
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                pbsp++;
 
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        }
 
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        if (pbsp_highest) {
 
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                printf("Error: board specific timing not found");
 
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                printf("for data rate %lu MT/s\n", ddr_freq);
 
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                printf("Trying to use the highest speed (%u) parameters\n",
 
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                       pbsp_highest->datarate_mhz_high);
 
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                popts->clk_adjust = pbsp_highest->clk_adjust;
 
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                popts->wrlvl_start = pbsp_highest->wrlvl_start;
 
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                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 
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                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 
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        } else {
 
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                panic("DIMM is not supported by this board");
 
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        }
 
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found:
 
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        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
 
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                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
 
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                "wrlvl_ctrl_3 0x%x\n",
 
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                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 
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                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 
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                pbsp->wrlvl_ctl_3);
 
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        /*
 
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         * Factors to consider for half-strength driver enable:
 
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         *      - number of DIMMs installed
 
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         */
 
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        popts->half_strength_driver_enable = 0;
 
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        /*
 
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         * Write leveling override
 
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         */
 
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        popts->wrlvl_override = 1;
 
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        popts->wrlvl_sample = 0xf;
 
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        /*
 
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         * Rtt and Rtt_WR override
 
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         */
 
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        popts->rtt_override = 0;
 
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        /* Enable ZQ calibration */
 
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        popts->zq_en = 1;
 
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        /* DHC_EN =1, ODT = 75 Ohm */
 
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        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 
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        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 
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}
 
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phys_size_t initdram(int board_type)
 
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{
 
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        phys_size_t dram_size;
 
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 
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        puts("Initializing....using SPD\n");
 
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        dram_size = fsl_ddr_sdram();
 
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        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 
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        dram_size *= 0x100000;
 
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#else
 
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        /* DDR has been initialised by first stage boot loader */
 
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        dram_size =  fsl_ddr_sdram_size();
 
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#endif
 
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        return dram_size;
 
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}