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Viewing changes to hw/arm/stm32f205_soc.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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Lines of Context:
hw/arm/stm32f205_soc.c
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    STM32F205State *s = STM32F205_SOC(obj);
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    int i;
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    object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
 
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    qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
 
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    object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
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    qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
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static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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    STM32F205State *s = STM32F205_SOC(dev_soc);
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    DeviceState *dev, *nvic;
 
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    DeviceState *dev, *armv7m;
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    SysBusDevice *busdev;
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    Error *err = NULL;
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    int i;
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    vmstate_register_ram_global(sram);
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    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
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    nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
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                       s->kernel_filename, s->cpu_model);
 
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    armv7m = DEVICE(&s->armv7m);
 
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    qdev_prop_set_uint32(armv7m, "num-irq", 96);
 
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    qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
 
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    object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
 
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                                     "memory", &error_abort);
 
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    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
 
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    if (err != NULL) {
 
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        error_propagate(errp, err);
 
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        return;
 
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    }
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    /* System configuration controller */
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    dev = DEVICE(&s->syscfg);
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    }
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    busdev = SYS_BUS_DEVICE(dev);
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    sysbus_mmio_map(busdev, 0, 0x40013800);
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    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
 
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    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
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    /* Attach UART (uses USART registers) and USART controllers */
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    for (i = 0; i < STM_NUM_USARTS; i++) {
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        }
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        busdev = SYS_BUS_DEVICE(dev);
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        sysbus_mmio_map(busdev, 0, usart_addr[i]);
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        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
 
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        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
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    }
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    /* Timer 2 to 5 */
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        }
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        busdev = SYS_BUS_DEVICE(dev);
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        sysbus_mmio_map(busdev, 0, timer_addr[i]);
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        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
 
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        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
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    }
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    /* ADC 1 to 3 */
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        return;
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    }
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    qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
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                          qdev_get_gpio_in(nvic, ADC_IRQ));
 
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                          qdev_get_gpio_in(armv7m, ADC_IRQ));
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    for (i = 0; i < STM_NUM_ADCS; i++) {
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        dev = DEVICE(&(s->adc[i]));
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        }
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        busdev = SYS_BUS_DEVICE(dev);
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        sysbus_mmio_map(busdev, 0, spi_addr[i]);
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        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
 
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        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
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    }
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}
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static Property stm32f205_soc_properties[] = {
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    DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
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    DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
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    DEFINE_PROP_END_OF_LIST(),
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};