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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/freescale/p2020come/tlb.c
 
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/*
 
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 * Copyright 2011 Freescale Semiconductor, Inc.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/mmu.h>
 
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struct fsl_e_tlb_entry tlb_table[] = {
 
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        /* TLB 0 - for temp stack in cache */
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
 
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                        CONFIG_SYS_INIT_RAM_ADDR_PHYS,
 
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                        MAS3_SW|MAS3_SR, 0,
 
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                        0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
 
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                        CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 
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                        MAS3_SW|MAS3_SR, 0,
 
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                        0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
 
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                        CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 
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                        MAS3_SW|MAS3_SR, 0,
 
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                        0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
 
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                        CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 
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                        MAS3_SW|MAS3_SR, 0,
 
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                        0, 0, BOOKE_PAGESZ_4K, 0),
 
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        /* TLB 1 */
 
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        /* *I*** - Covers boot page */
 
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        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 
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                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 0, BOOKE_PAGESZ_4K, 1),
 
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        /* *I*G* - CCSRBAR */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 
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                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 1, BOOKE_PAGESZ_1M, 1),
 
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#if defined(CONFIG_PCI)
 
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        /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
 
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                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 2, BOOKE_PAGESZ_1G, 1),
 
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        /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
 
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                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 3, BOOKE_PAGESZ_256M, 1),
 
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        /* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
 
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                        CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
 
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                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 4, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * *I*G* - PCI I/O
 
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         *
 
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         * PCI3 => 0xFFC10000
 
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         * PCI2 => 0xFFC2,0000
 
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         * PCI1 => 0xFFC3,0000
 
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         */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
 
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                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 5, BOOKE_PAGESZ_256K, 1),
 
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#endif /* #if defined(CONFIG_PCI) */
 
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 
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        /* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
 
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                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 6, BOOKE_PAGESZ_256K, 1),
 
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        /*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
 
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        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
 
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                        CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
 
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                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                        0, 7, BOOKE_PAGESZ_256K, 1),
 
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#endif
 
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};
 
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int num_tlb_entries = ARRAY_SIZE(tlb_table);