2
* Copyright (C) 2012 Samsung Electronics
3
* R. Chandrasekar <rcsekar@samsung.com>
5
* SPDX-License-Identifier: GPL-2.0+
8
#include <asm/arch/clk.h>
9
#include <asm/arch/pinmux.h>
10
#include <asm/arch/i2s-regs.h>
16
#define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
17
#define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
18
#define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
19
#define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
20
#define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
22
#define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
25
* Sets the frame size for I2S LR clock
27
* @param i2s_reg i2s regiter address
28
* @param rfs Frame Size
30
static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
32
unsigned int mod = readl(&i2s_reg->mod);
34
mod &= ~MOD_RCLK_MASK;
38
mod |= MOD_RCLK_768FS;
41
mod |= MOD_RCLK_512FS;
44
mod |= MOD_RCLK_384FS;
47
mod |= MOD_RCLK_256FS;
51
writel(mod, &i2s_reg->mod);
55
* Sets the i2s transfer control
57
* @param i2s_reg i2s regiter address
58
* @param on 1 enable tx , 0 disable tx transfer
60
static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
62
unsigned int con = readl(&i2s_reg->con);
63
unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
67
con &= ~CON_TXCH_PAUSE;
69
con |= CON_TXCH_PAUSE;
73
writel(mod, &i2s_reg->mod);
74
writel(con, &i2s_reg->con);
78
* set the bit clock frame size (in multiples of LRCLK)
80
* @param i2s_reg i2s regiter address
81
* @param bfs bit Frame Size
83
static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
85
unsigned int mod = readl(&i2s_reg->mod);
87
mod &= ~MOD_BCLK_MASK;
100
mod |= MOD_BCLK_16FS;
105
writel(mod, &i2s_reg->mod);
109
* flushes the i2stx fifo
111
* @param i2s_reg i2s regiter address
112
* @param flush Tx fifo flush command (0x00 - do not flush
113
* 0x80 - flush tx fifo)
115
void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
118
setbits_le32(&i2s_reg->fic, flush);
119
clrbits_le32(&i2s_reg->fic, flush);
123
* Set System Clock direction
125
* @param i2s_reg i2s regiter address
126
* @param dir Clock direction
128
* @return int value 0 for success, -1 in case of error
130
int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
132
unsigned int mod = readl(&i2s_reg->mod);
134
if (dir == SND_SOC_CLOCK_IN)
137
mod &= ~MOD_CDCLKCON;
139
writel(mod, &i2s_reg->mod);
145
* Sets I2S Clcok format
147
* @param fmt i2s clock properties
148
* @param i2s_reg i2s regiter address
150
* @return int value 0 for success, -1 in case of error
152
int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
154
unsigned int mod = readl(&i2s_reg->mod);
155
unsigned int tmp = 0;
156
unsigned int ret = 0;
158
/* Format is priority */
159
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
160
case SND_SOC_DAIFMT_RIGHT_J:
164
case SND_SOC_DAIFMT_LEFT_J:
168
case SND_SOC_DAIFMT_I2S:
172
debug("%s: Invalid format priority [0x%x]\n", __func__,
173
(fmt & SND_SOC_DAIFMT_FORMAT_MASK));
178
* INV flag is relative to the FORMAT flag - if set it simply
179
* flips the polarity specified by the Standard
181
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
182
case SND_SOC_DAIFMT_NB_NF:
184
case SND_SOC_DAIFMT_NB_IF:
185
if (tmp & MOD_LR_RLOW)
191
debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
192
(fmt & SND_SOC_DAIFMT_INV_MASK));
196
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
197
case SND_SOC_DAIFMT_CBS_CFS:
200
case SND_SOC_DAIFMT_CBM_CFM:
201
/* Set default source clock in Master mode */
202
ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
204
debug("%s:set i2s clock direction failed\n", __func__);
209
debug("%s: Invalid master selection [0x%x]\n", __func__,
210
(fmt & SND_SOC_DAIFMT_MASTER_MASK));
214
mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
216
writel(mod, &i2s_reg->mod);
222
* Sets the sample width in bits
224
* @param blc samplewidth (size of sample in bits)
225
* @param i2s_reg i2s regiter address
227
* @return int value 0 for success, -1 in case of error
229
int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
231
unsigned int mod = readl(&i2s_reg->mod);
233
mod &= ~MOD_BLCP_MASK;
234
mod &= ~MOD_BLC_MASK;
238
mod |= MOD_BLCP_8BIT;
242
mod |= MOD_BLCP_16BIT;
243
mod |= MOD_BLC_16BIT;
246
mod |= MOD_BLCP_24BIT;
247
mod |= MOD_BLC_24BIT;
250
debug("%s: Invalid sample size input [0x%x]\n",
254
writel(mod, &i2s_reg->mod);
259
int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data,
260
unsigned long data_size)
264
struct i2s_reg *i2s_reg =
265
(struct i2s_reg *)pi2s_tx->base_address;
267
if (data_size < FIFO_LENGTH) {
268
debug("%s : Invalid data size\n", __func__);
269
return -1; /* invalid pcm data size */
272
/* fill the tx buffer before stating the tx transmit */
273
for (i = 0; i < FIFO_LENGTH; i++)
274
writel(*data++, &i2s_reg->txd);
276
data_size -= FIFO_LENGTH;
277
i2s_txctrl(i2s_reg, I2S_TX_ON);
279
while (data_size > 0) {
280
start = get_timer(0);
281
if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
282
writel(*data++, &i2s_reg->txd);
285
if (get_timer(start) > TIMEOUT_I2S_TX) {
286
i2s_txctrl(i2s_reg, I2S_TX_OFF);
287
debug("%s: I2S Transfer Timeout\n", __func__);
292
i2s_txctrl(i2s_reg, I2S_TX_OFF);
297
int i2s_tx_init(struct i2stx_info *pi2s_tx)
300
struct i2s_reg *i2s_reg =
301
(struct i2s_reg *)pi2s_tx->base_address;
302
if (pi2s_tx->id == 0) {
303
/* Initialize GPIO for I2S-0 */
304
exynos_pinmux_config(PERIPH_ID_I2S0, 0);
307
ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
308
} else if (pi2s_tx->id == 1) {
309
/* Initialize GPIO for I2S-1 */
310
exynos_pinmux_config(PERIPH_ID_I2S1, 0);
313
ret = set_epll_clk(pi2s_tx->audio_pll_clk);
315
debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id);
320
debug("%s: epll clock set rate failed\n", __func__);
324
/* Select Clk Source for Audio 0 or 1 */
325
ret = set_i2s_clk_source(pi2s_tx->id);
327
debug("%s: unsupported clock for i2s-%d\n", __func__,
332
if (pi2s_tx->id == 0) {
333
/*Reset the i2s module */
334
writel(CON_RESET, &i2s_reg->con);
336
writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
337
/* set i2s prescaler */
338
writel(PSREN | PSVAL, &i2s_reg->psr);
340
/* Set Prescaler to get MCLK */
341
ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
342
(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
346
debug("%s: unsupported prescalar for i2s-%d\n", __func__,
351
/* Configure I2s format */
352
ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
353
SND_SOC_DAIFMT_CBM_CFM));
355
i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
356
ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
358
debug("%s:set sample rate failed\n", __func__);
362
i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
363
/* disable i2s transfer flag and flush the fifo */
364
i2s_txctrl(i2s_reg, I2S_TX_OFF);
365
i2s_fifo(i2s_reg, FIC_TXFLUSH);
367
debug("%s: failed\n", __func__);