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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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* SPDX-License-Identifier: GPL-2.0+
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#include <asm/arch/imx-regs.h>
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1 << 15) /* Software reset */
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#define GPTCR_FRR (1 << 8) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
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#define GPTCR_TEN 1 /* Timer enable */
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DECLARE_GLOBAL_DATA_PTR;
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#define timestamp (gd->arch.tbl)
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#define lastinc (gd->arch.lastinc)
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* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
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* "tick" is internal timer period
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#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
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/* ~0.4% error - measured with stop-watch on 100s boot-delay */
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static inline unsigned long long tick_to_time(unsigned long long tick)
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tick *= CONFIG_SYS_HZ;
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do_div(tick, CONFIG_MX27_CLK32);
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static inline unsigned long long time_to_tick(unsigned long long time)
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time *= CONFIG_MX27_CLK32;
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do_div(time, CONFIG_SYS_HZ);
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static inline unsigned long long us_to_tick(unsigned long long us)
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us = us * CONFIG_MX27_CLK32 + 999999;
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#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
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#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
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static inline unsigned long long tick_to_time(unsigned long long tick)
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do_div(tick, TICK_PER_TIME);
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static inline unsigned long long time_to_tick(unsigned long long time)
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return time * TICK_PER_TIME;
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static inline unsigned long long us_to_tick(unsigned long long us)
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us += US_PER_TICK - 1;
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do_div(us, US_PER_TICK);
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/* nothing really to do with interrupts, just starts up a counter. */
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/* The 32768Hz 32-bit timer overruns in 131072 seconds */
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struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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/* setup GP Timer 1 */
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writel(GPTCR_SWR, ®s->gpt_tctl);
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writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
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writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
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for (i = 0; i < 100; i++)
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writel(0, ®s->gpt_tctl); /* We have no udelay by now */
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writel(0, ®s->gpt_tprer); /* 32Khz */
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/* Freerun Mode, PERCLK1 input */
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writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
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writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl);
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unsigned long long get_ticks(void)
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struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
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ulong now = readl(®s->gpt_tcn); /* current tick value */
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if (now >= lastinc) {
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* normal mode (non roll)
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* move stamp forward with absolut diff ticks
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timestamp += (now - lastinc);
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/* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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ulong get_timer_masked(void)
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* get_ticks() returns a long long (64 bit), it wraps in
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* 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
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* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
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* 5 * 10^6 days - long enough.
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return tick_to_time(get_ticks());
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ulong get_timer(ulong base)
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return get_timer_masked() - base;
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/* delay x useconds AND preserve advance timstamp value */
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void __udelay(unsigned long usec)
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unsigned long long tmp;
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tmo = us_to_tick(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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ulong get_tbclk(void)
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return CONFIG_MX27_CLK32;