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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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* SPDX-License-Identifier: GPL-2.0+
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#include <asm/processor.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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* Low Power Divider specifications
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#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
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#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
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#define CLOCK_PLL_FVCO_MAX 540000000
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#define CLOCK_PLL_FVCO_MIN 300000000
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#define CLOCK_PLL_FSYS_MAX 266666666
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#define CLOCK_PLL_FSYS_MIN 100000000
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void clock_enter_limp(int lpdiv)
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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/* Check bounds of divider */
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if (lpdiv < CLOCK_LPD_MIN)
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lpdiv = CLOCK_LPD_MIN;
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if (lpdiv > CLOCK_LPD_MAX)
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lpdiv = CLOCK_LPD_MAX;
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/* Round divider down to nearest power of two */
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for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
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#ifdef CONFIG_MCF5445x
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/* Apply the divider to the system clock */
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clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
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/* Enable Limp Mode */
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setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
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* brief Exit Limp mode
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* warning The PLL should be set and locked prior to exiting Limp mode
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void clock_exit_limp(void)
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
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/* Wait for the PLL to lock */
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while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
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#ifdef CONFIG_MCF5441x
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void setup_5441x_clocks(void)
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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int temp, vco = 0, bootmod_ccr, pdr;
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bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
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switch (bootmod_ccr) {
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out_be32(&pll->pcr, 0x00000013);
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out_be32(&pll->pdr, 0x00e70c61);
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/*Change frequency for Modelo SER1 USB host*/
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#ifdef CONFIG_LOW_MCFCLK
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temp = in_be32(&pll->pcr);
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out_be32(&pll->pcr, temp);
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temp = in_be32(&pll->pdr);
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out_be32(&pll->pdr, temp);
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setbits_be16(&ccm->misccr2, 0x02);
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vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
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CONFIG_SYS_INPUT_CLKSRC;
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gd->arch.vco_clk = vco;
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gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
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pdr = in_be32(&pll->pdr);
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temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
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gd->cpu_clk = vco / temp; /* cpu clock */
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gd->arch.flb_clk = vco / temp; /* FlexBus clock */
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gd->arch.flb_clk >>= 1;
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if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
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gd->arch.flb_clk >>= 1;
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temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
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gd->bus_clk = vco / temp; /* bus clock */
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#ifdef CONFIG_MCF5445x
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void setup_5445x_clocks(void)
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
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int pllmult_pci[] = { 12, 6, 16, 8 };
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int vco = 0, temp, fbtemp, pcrvalue;
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int *pPllmult = NULL;
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#ifdef CONFIG_M54455EVB
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u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
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/* To determine PCI is present or not */
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if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
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((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
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pPllmult = &pllmult_pci[0];
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fbpll_mask = 3; /* 11b */
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pPllmult = &pllmult_nopci[0];
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fbpll_mask = 7; /* 111b */
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#ifdef CONFIG_M54455EVB
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bootmode = (in_8(cpld) & 0x03);
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/* Temporary read from CCR- fixed fb issue, must be the same clock
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as pci or input clock, causing cpld/fpga read inconsistancy */
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fbtemp = pPllmult[ccm->ccr & fbpll_mask];
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/* Break down into small pieces, code still in flex bus */
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pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
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pcrvalue |= PLL_PCR_OUTDIV3(temp);
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out_be32(&pll->pcr, pcrvalue);
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#ifdef CONFIG_M54451EVB
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/* No external logic to read the bootmode, hard coded from built */
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/* default value is 16 mul, set to 20 mul */
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pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
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out_be32(&pll->pcr, pcrvalue);
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while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
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vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
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if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
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/* invaild range, re-set in PCR */
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int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
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j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
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for (i = j; i < 0xFF; i++) {
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vco = i * CONFIG_SYS_INPUT_CLKSRC;
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if (vco >= CLOCK_PLL_FVCO_MIN) {
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if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
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pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
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fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
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pcrvalue |= ((i << 24) | fbtemp);
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out_be32(&pll->pcr, pcrvalue);
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gd->arch.vco_clk = vco; /* Vco clock */
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} else if (bootmode == 2) {
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vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
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if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
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pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
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pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
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out_be32(&pll->pcr, pcrvalue);
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vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
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gd->arch.vco_clk = vco; /* Vco clock */
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} else if (bootmode == 3) {
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vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
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gd->arch.vco_clk = vco; /* Vco clock */
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if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
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gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
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temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
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gd->cpu_clk = vco / temp; /* cpu clock */
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temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
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gd->bus_clk = vco / temp; /* bus clock */
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temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
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gd->arch.flb_clk = vco / temp; /* FlexBus clock */
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temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
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gd->pci_clk = vco / temp; /* PCI clock */
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
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#ifdef CONFIG_MCF5441x
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setup_5441x_clocks();
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#ifdef CONFIG_MCF5445x
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setup_5445x_clocks();
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#ifdef CONFIG_SYS_FSL_I2C
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gd->arch.i2c1_clk = gd->bus_clk;