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/* Copyright 2013-2014 IBM Corp.
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* http://www.apache.org/licenses/LICENSE-2.0
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* See the License for the specific language governing permissions and
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* limitations under the License.
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#include <interrupts.h>
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#include <ccan/str/str.h>
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#define ICP_XIRR 0x4 /* 32-bit access */
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#define ICP_CPPR 0x4 /* 8-bit access */
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#define ICP_MFRR 0xc /* 8-bit access */
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static LIST_HEAD(irq_sources);
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static struct lock irq_lock = LOCK_UNLOCKED;
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void __register_irq_source(struct irq_source *is)
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struct irq_source *is1;
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prlog(PR_DEBUG, "IRQ: Registering %04x..%04x ops @%p (data %p)\n",
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is->start, is->end - 1, is->ops, is->data);
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list_for_each(&irq_sources, is1, link) {
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if (is->end > is1->start && is->start < is1->end) {
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prerror("register IRQ source overlap !\n");
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prerror(" new: %x..%x old: %x..%x\n",
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is->start, is->end - 1,
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is1->start, is1->end - 1);
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list_add_tail(&irq_sources, &is->link);
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void register_irq_source(const struct irq_source_ops *ops, void *data,
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uint32_t start, uint32_t count)
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struct irq_source *is;
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is = zalloc(sizeof(struct irq_source));
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is->end = start + count;
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__register_irq_source(is);
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void unregister_irq_source(uint32_t start, uint32_t count)
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struct irq_source *is;
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list_for_each(&irq_sources, is, link) {
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if (start >= is->start && start < is->end) {
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if (start != is->start ||
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count != (is->end - is->start)) {
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prerror("unregister IRQ source mismatch !\n");
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prerror("start:%x, count: %x match: %x..%x\n",
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start, count, is->start, is->end);
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/* XXX Add synchronize / RCU */
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prerror("unregister IRQ source not found !\n");
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prerror("start:%x, count: %x\n", start, count);
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static struct irq_source *irq_find_source(uint32_t isn)
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struct irq_source *is;
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list_for_each(&irq_sources, is, link) {
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if (isn >= is->start && isn < is->end) {
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void adjust_irq_source(struct irq_source *is, uint32_t new_count)
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struct irq_source *is1;
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uint32_t new_end = is->start + new_count;
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prlog(PR_DEBUG, "IRQ: Adjusting %04x..%04x to %04x..%04x\n",
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is->start, is->end - 1, is->start, new_end - 1);
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list_for_each(&irq_sources, is1, link) {
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if (new_end > is1->start && is->start < is1->end) {
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prerror("adjust IRQ source overlap !\n");
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prerror(" new: %x..%x old: %x..%x\n",
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is->start, new_end - 1,
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is1->start, is1->end - 1);
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* This takes a 6-bit chip id and returns a 20 bit value representing
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* the PSI interrupt. This includes all the fields above, ie, is a
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* global interrupt number.
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* For P8, this returns the base of the 8-interrupts block for PSI
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uint32_t get_psi_interrupt(uint32_t chip_id)
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/* Get the chip ID into position, it already has
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* the T bit so all we need is room for the GX
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* bit, 9 bit BUID and 4 bit level
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irq = chip_id << (1 + 9 + 4);
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/* Add in the BUID */
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irq |= P7_PSI_IRQ_BUID << 4;
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irq = p8_chip_irq_block_base(chip_id, P8_IRQ_BLOCK_MISC);
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irq += P8_IRQ_MISC_PSI_BASE;
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struct dt_node *add_ics_node(void)
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struct dt_node *ics = dt_new_addr(dt_root, "interrupt-controller", 0);
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dt_add_property_cells(ics, "reg", 0, 0, 0, 0);
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dt_add_property_strings(ics, "compatible", "IBM,ppc-xics",
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dt_add_property_cells(ics, "#address-cells", 0);
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dt_add_property_cells(ics, "#interrupt-cells", 2);
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dt_add_property_string(ics, "device_type",
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"PowerPC-Interrupt-Source-Controller");
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dt_add_property(ics, "interrupt-controller", NULL, 0);
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uint32_t get_ics_phandle(void)
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for (i = dt_first(dt_root); i; i = dt_next(dt_root, i)) {
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if (streq(i->name, "interrupt-controller@0")) {
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void add_opal_interrupts(void)
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struct irq_source *is;
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unsigned int i, count = 0;
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uint32_t *irqs = NULL, isn;
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list_for_each(&irq_sources, is, link) {
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* Add a source to opal-interrupts if it has an
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* ->interrupt callback
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if (!is->ops->interrupt)
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for (isn = is->start; isn < is->end; isn++) {
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irqs = realloc(irqs, 4 * count);
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/* The opal-interrupts property has one cell per interrupt,
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* it is not a standard interrupt property.
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* Note: Even if empty, create it, otherwise some bogus error
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* handling in Linux can cause problems.
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dt_add_property(opal_node, "opal-interrupts", irqs, count * 4);
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* This is called at init time (and one fast reboot) to sanitize the
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* ICP. We set our priority to 0 to mask all interrupts and make sure
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* no IPI is on the way.
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void reset_cpu_icp(void)
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void *icp = this_cpu()->icp_regs;
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/* Clear pending IPIs */
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out_8(icp + ICP_MFRR, 0xff);
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/* Set priority to max, ignore all incoming interrupts, EOI IPIs */
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out_be32(icp + ICP_XIRR, 2);
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/* Used by the PSI code to send an EOI during reset. This will also
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* set the CPPR to 0 which should already be the case anyway
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void icp_send_eoi(uint32_t interrupt)
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void *icp = this_cpu()->icp_regs;
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/* Set priority to max, ignore all incoming interrupts */
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out_be32(icp + ICP_XIRR, interrupt & 0xffffff);
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/* This is called before winkle, we clear pending IPIs and set our priority
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* to 1 to mask all but the IPI
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void icp_prep_for_rvwinkle(void)
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void *icp = this_cpu()->icp_regs;
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/* Clear pending IPIs */
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out_8(icp + ICP_MFRR, 0xff);
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/* Set priority to 1, ignore all incoming interrupts, EOI IPIs */
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out_be32(icp + ICP_XIRR, 0x01000002);
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/* This is called to wakeup somebody from winkle */
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void icp_kick_cpu(struct cpu_thread *cpu)
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void *icp = cpu->icp_regs;
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/* Send high priority IPI */
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out_8(icp + ICP_MFRR, 0);
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/* Returns the number of chip ID bits used for interrupt numbers */
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static uint32_t p8_chip_id_bits(uint32_t chip)
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struct proc_chip *proc_chip = get_chip(chip);
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switch (proc_chip->type) {
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case PROC_CHIP_P8_MURANO:
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case PROC_CHIP_P8_VENICE:
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case PROC_CHIP_P8_NAPLES:
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/* This shouldn't be called on non-P8 based systems */
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/* The chip id mask is the upper p8_chip_id_bits of the irq number */
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static uint32_t chip_id_mask(uint32_t chip)
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uint32_t chip_id_bits = p8_chip_id_bits(chip);
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uint32_t chip_id_mask;
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chip_id_mask = ((1 << chip_id_bits) - 1);
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chip_id_mask <<= P8_IRQ_BITS - chip_id_bits;
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/* The block mask is what remains of the 19 bit irq number after
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* removing the upper 5 or 6 bits for the chip# and the lower 11 bits
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* for the number of bits per block. */
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static uint32_t block_mask(uint32_t chip)
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uint32_t chip_id_bits = p8_chip_id_bits(chip);
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uint32_t irq_block_mask;
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irq_block_mask = P8_IRQ_BITS - chip_id_bits - P8_IVE_BITS;
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irq_block_mask = ((1 << irq_block_mask) - 1) << P8_IVE_BITS;
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return irq_block_mask;
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uint32_t p8_chip_irq_block_base(uint32_t chip, uint32_t block)
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assert(chip < (1 << p8_chip_id_bits(chip)));
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irq = SETFIELD(chip_id_mask(chip), 0, chip);
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irq = SETFIELD(block_mask(chip), irq, block);
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uint32_t p8_chip_irq_phb_base(uint32_t chip, uint32_t phb)
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assert(chip < (1 << p8_chip_id_bits(chip)));
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return p8_chip_irq_block_base(chip, phb + P8_IRQ_BLOCK_PHB_BASE);
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uint32_t p8_irq_to_chip(uint32_t irq)
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/* This assumes we only have one type of cpu in a system,
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* which should be ok. */
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return GETFIELD(chip_id_mask(this_cpu()->chip_id), irq);
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uint32_t p8_irq_to_block(uint32_t irq)
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return GETFIELD(block_mask(this_cpu()->chip_id), irq);
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uint32_t p8_irq_to_phb(uint32_t irq)
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return p8_irq_to_block(irq) - P8_IRQ_BLOCK_PHB_BASE;
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bool irq_source_eoi(uint32_t isn)
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struct irq_source *is = irq_find_source(isn);
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if (!is || !is->ops->eoi)
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is->ops->eoi(is, isn);
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static int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority)
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struct irq_source *is = irq_find_source(isn);
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if (!is || !is->ops->set_xive)
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return OPAL_PARAMETER;
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return is->ops->set_xive(is, isn, server, priority);
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opal_call(OPAL_SET_XIVE, opal_set_xive, 3);
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static int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority)
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struct irq_source *is = irq_find_source(isn);
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if (!is || !is->ops->get_xive)
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return OPAL_PARAMETER;
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return is->ops->get_xive(is, isn, server, priority);
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opal_call(OPAL_GET_XIVE, opal_get_xive, 3);
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static int64_t opal_handle_interrupt(uint32_t isn, __be64 *outstanding_event_mask)
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struct irq_source *is = irq_find_source(isn);
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int64_t rc = OPAL_SUCCESS;
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/* No source ? return */
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if (!is || !is->ops->interrupt) {
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is->ops->interrupt(is, isn);
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/* Check timers if SLW timer isn't working */
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/* Update output events */
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if (outstanding_event_mask)
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*outstanding_event_mask = cpu_to_be64(opal_pending_events);
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opal_call(OPAL_HANDLE_INTERRUPT, opal_handle_interrupt, 2);
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void init_interrupts(void)
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const struct dt_property *sranges;
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struct cpu_thread *cpu;
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dt_for_each_compatible(dt_root, icp, "ibm,ppc-xicp") {
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sranges = dt_require_property(icp,
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"ibm,interrupt-server-ranges",
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base = dt_get_number(sranges->prop, 1);
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count = dt_get_number(sranges->prop + 4, 1);
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for (i = 0; i < count; i++) {
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addr = dt_get_address(icp, i, &size);
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cpu = find_cpu_by_server(base + i);
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cpu->icp_regs = (void *)addr;