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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/atmel/at91sam9rlek/at91sam9rlek.c
 
1
/*
 
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 * (C) Copyright 2007-2008
 
3
 * Stelian Pop <stelian@popies.net>
 
4
 * Lead Tech Design <www.leadtechdesign.com>
 
5
 *
 
6
 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
8
 
 
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#include <common.h>
 
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#include <asm/io.h>
 
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#include <asm/arch/at91sam9rl.h>
 
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#include <asm/arch/at91sam9rl_matrix.h>
 
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#include <asm/arch/at91sam9_smc.h>
 
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#include <asm/arch/at91_common.h>
 
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#include <asm/arch/at91_pmc.h>
 
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#include <asm/arch/at91_rstc.h>
 
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#include <asm/arch/clk.h>
 
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#include <asm/arch/gpio.h>
 
19
 
 
20
#include <lcd.h>
 
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#include <atmel_lcdc.h>
 
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 
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#include <net.h>
 
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#endif
 
25
 
 
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DECLARE_GLOBAL_DATA_PTR;
 
27
 
 
28
/* ------------------------------------------------------------------------- */
 
29
/*
 
30
 * Miscelaneous platform dependent initialisations
 
31
 */
 
32
 
 
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#ifdef CONFIG_CMD_NAND
 
34
static void at91sam9rlek_nand_hw_init(void)
 
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{
 
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        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 
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        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 
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        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
39
        unsigned long csa;
 
40
 
 
41
        /* Enable CS3 */
 
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        csa = readl(&matrix->ebicsa);
 
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        csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
 
44
 
 
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        writel(csa, &matrix->ebicsa);
 
46
 
 
47
        /* Configure SMC CS3 for NAND/SmartMedia */
 
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        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
 
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                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 
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                &smc->cs[3].setup);
 
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        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
 
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                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
 
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                &smc->cs[3].pulse);
 
54
        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
 
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                &smc->cs[3].cycle);
 
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        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 
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                AT91_SMC_MODE_EXNW_DISABLE |
 
58
#ifdef CONFIG_SYS_NAND_DBW_16
 
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                AT91_SMC_MODE_DBW_16 |
 
60
#else /* CONFIG_SYS_NAND_DBW_8 */
 
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                AT91_SMC_MODE_DBW_8 |
 
62
#endif
 
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                AT91_SMC_MODE_TDF_CYCLE(2),
 
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                &smc->cs[3].mode);
 
65
 
 
66
        writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
 
67
 
 
68
        /* Configure RDY/BSY */
 
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        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
70
 
 
71
        /* Enable NandFlash */
 
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        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 
73
 
 
74
        at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
 
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        at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
 
76
}
 
77
#endif
 
78
 
 
79
#ifdef CONFIG_LCD
 
80
vidinfo_t panel_info = {
 
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        vl_col:         240,
 
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        vl_row:         320,
 
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        vl_clk:         4965000,
 
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        vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 
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                        ATMEL_LCDC_INVFRAME_INVERTED,
 
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        vl_bpix:        3,
 
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        vl_tft:         1,
 
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        vl_hsync_len:   5,
 
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        vl_left_margin: 1,
 
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        vl_right_margin:33,
 
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        vl_vsync_len:   1,
 
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        vl_upper_margin:1,
 
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        vl_lower_margin:0,
 
94
        mmio:           ATMEL_BASE_LCDC,
 
95
};
 
96
 
 
97
void lcd_enable(void)
 
98
{
 
99
        at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
 
100
}
 
101
 
 
102
void lcd_disable(void)
 
103
{
 
104
        at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 
105
}
 
106
static void at91sam9rlek_lcd_hw_init(void)
 
107
{
 
108
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
109
 
 
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        at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 
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        at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 
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        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 
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        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 
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        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 
115
        at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 
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        at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 
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        at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 
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        at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 
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        at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 
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        at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 
121
        at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 
122
        at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 
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        at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 
124
        at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 
125
        at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 
126
        at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 
127
        at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 
128
        at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 
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        at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 
130
        at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 
131
 
 
132
        writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 
133
}
 
134
 
 
135
#ifdef CONFIG_LCD_INFO
 
136
#include <nand.h>
 
137
#include <version.h>
 
138
 
 
139
void lcd_show_board_info(void)
 
140
{
 
141
        ulong dram_size, nand_size;
 
142
        int i;
 
143
        char temp[32];
 
144
 
 
145
        lcd_printf ("%s\n", U_BOOT_VERSION);
 
146
        lcd_printf ("(C) 2008 ATMEL Corp\n");
 
147
        lcd_printf ("at91support@atmel.com\n");
 
148
        lcd_printf ("%s CPU at %s MHz\n",
 
149
                ATMEL_CPU_NAME,
 
150
                strmhz(temp, get_cpu_clk_rate()));
 
151
 
 
152
        dram_size = 0;
 
153
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 
154
                dram_size += gd->bd->bi_dram[i].size;
 
155
        nand_size = 0;
 
156
        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 
157
                nand_size += nand_info[i].size;
 
158
        lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 
159
                dram_size >> 20,
 
160
                nand_size >> 20 );
 
161
}
 
162
#endif /* CONFIG_LCD_INFO */
 
163
#endif
 
164
 
 
165
int board_early_init_f(void)
 
166
{
 
167
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
168
 
 
169
        /* Enable clocks for all PIOs */
 
170
        writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 
171
                (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
 
172
                &pmc->pcer);
 
173
 
 
174
        return 0;
 
175
}
 
176
 
 
177
int board_init(void)
 
178
{
 
179
        /* arch number of AT91SAM9RLEK-Board */
 
180
        gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 
181
        /* adress of boot parameters */
 
182
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
183
 
 
184
        at91_seriald_hw_init();
 
185
#ifdef CONFIG_CMD_NAND
 
186
        at91sam9rlek_nand_hw_init();
 
187
#endif
 
188
#ifdef CONFIG_HAS_DATAFLASH
 
189
        at91_spi0_hw_init(1 << 0);
 
190
#endif
 
191
#ifdef CONFIG_LCD
 
192
        at91sam9rlek_lcd_hw_init();
 
193
#endif
 
194
        return 0;
 
195
}
 
196
 
 
197
int dram_init(void)
 
198
{
 
199
        gd->ram_size = get_ram_size(
 
200
                (void *)CONFIG_SYS_SDRAM_BASE,
 
201
                CONFIG_SYS_SDRAM_SIZE);
 
202
        return 0;
 
203
}