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Viewing changes to roms/u-boot/board/sandburst/karef/hal_ka_of_auto.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/sandburst/karef/hal_ka_of_auto.h
 
1
/* ****************************************************************
 
2
 * Common defs for reg spec for chip ka_of
 
3
 * Auto-generated by trex2: DO NOT HAND-EDIT!!
 
4
 * ****************************************************************
 
5
 */
 
6
 
 
7
#ifndef HAL_KA_OF_AUTO_H
 
8
#define HAL_KA_OF_AUTO_H
 
9
 
 
10
 
 
11
/* ----------------------------------------------------------------
 
12
 * For block: 'ofem'
 
13
 */
 
14
 
 
15
/* ---- Block instance addressing (for block-select) */
 
16
#define OFEM_BLOCK_ADDR_BIT_L 6
 
17
#define OFEM_BLOCK_ADDR_BIT_H 9
 
18
#define OFEM_BLOCK_ADDR_WIDTH 4
 
19
 
 
20
#define  OFEM_ADDR  0x0
 
21
 
 
22
/* ---- Reg addressing (within block) */
 
23
#define OFEM_REG_ADDR_BIT_L 2
 
24
#define OFEM_REG_ADDR_BIT_H 5
 
25
#define OFEM_REG_ADDR_WIDTH 4
 
26
 
 
27
 
 
28
/* ================================================================
 
29
 * ---- Register KA_OF_OFEM_REVISION */
 
30
#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET    0x000
 
31
#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
 
32
#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK    0x000
 
33
#endif
 
34
#define SAND_HAL_KA_OF_OFEM_REVISION_MASK    0xffffffff
 
35
#define SAND_HAL_KA_OF_OFEM_REVISION_MSB     31
 
36
#define SAND_HAL_KA_OF_OFEM_REVISION_LSB      0
 
37
 
 
38
/* ================================================================
 
39
 * ---- Register KA_OF_OFEM_RESET */
 
40
#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET    0x004
 
41
#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
 
42
#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK    0x000
 
43
#endif
 
44
#define SAND_HAL_KA_OF_OFEM_RESET_MASK    0xffffffff
 
45
#define SAND_HAL_KA_OF_OFEM_RESET_MSB     31
 
46
#define SAND_HAL_KA_OF_OFEM_RESET_LSB      0
 
47
 
 
48
/* ================================================================
 
49
 * ---- Register KA_OF_OFEM_CNTL */
 
50
#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET    0x018
 
51
#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
 
52
#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK    0x000
 
53
#endif
 
54
#define SAND_HAL_KA_OF_OFEM_CNTL_MASK    0xffffffff
 
55
#define SAND_HAL_KA_OF_OFEM_CNTL_MSB     31
 
56
#define SAND_HAL_KA_OF_OFEM_CNTL_LSB      0
 
57
 
 
58
/* ================================================================
 
59
 * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
 
60
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET    0x01c
 
61
#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
 
62
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK    0x000
 
63
#endif
 
64
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK    0xffffffff
 
65
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB     31
 
66
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB      0
 
67
 
 
68
/* ================================================================
 
69
 * ---- Register KA_OF_OFEM_INTERRUPT */
 
70
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET    0x008
 
71
#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
 
72
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK    0x000
 
73
#endif
 
74
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK    0xffffffff
 
75
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB     31
 
76
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB      0
 
77
 
 
78
/* ================================================================
 
79
 * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
 
80
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET    0x00c
 
81
#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
 
82
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK    0x000
 
83
#endif
 
84
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK    0xffffffff
 
85
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB     31
 
86
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB      0
 
87
 
 
88
/* ================================================================
 
89
 * ---- Register KA_OF_OFEM_SCRATCH */
 
90
#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET    0x010
 
91
#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
 
92
#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK    0x000
 
93
#endif
 
94
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK    0xffffffff
 
95
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB     31
 
96
#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB      0
 
97
 
 
98
/* ================================================================
 
99
 * ---- Register KA_OF_OFEM_SCRATCH_MASK */
 
100
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET    0x014
 
101
#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
 
102
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK    0x000
 
103
#endif
 
104
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK    0xffffffff
 
105
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB     31
 
106
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB      0
 
107
 
 
108
/* ================================================================
 
109
 * Field info for register KA_OF_OFEM_REVISION */
 
110
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK    0x0000ff00
 
111
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT    8
 
112
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB    15
 
113
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB    8
 
114
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
 
115
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT    0x00000024
 
116
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK    0x000000ff
 
117
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT    0
 
118
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB    7
 
119
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB    0
 
120
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
 
121
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT    0x00000000
 
122
 
 
123
/* ================================================================
 
124
 * Field info for register KA_OF_OFEM_RESET */
 
125
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
 
126
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT    2
 
127
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB    2
 
128
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB    2
 
129
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
 
130
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
 
131
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK    0x00000002
 
132
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT    1
 
133
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB    1
 
134
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB    1
 
135
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
 
136
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT    0x00000000
 
137
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK    0x00000001
 
138
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT    0
 
139
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB    0
 
140
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB    0
 
141
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
 
142
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT    0x00000000
 
143
 
 
144
/* ================================================================
 
145
 * Field info for register KA_OF_OFEM_CNTL */
 
146
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK    0x000000c0
 
147
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT    6
 
148
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB    7
 
149
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB    6
 
150
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
 
151
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT    0x00000000
 
152
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK    0x00000030
 
153
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT    4
 
154
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB    5
 
155
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB    4
 
156
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
 
157
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT    0x00000000
 
158
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK    0x0000000c
 
159
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT    2
 
160
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB    3
 
161
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB    2
 
162
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
 
163
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT    0x00000000
 
164
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK    0x00000003
 
165
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT    0
 
166
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB    1
 
167
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB    0
 
168
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
 
169
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT    0x00000000
 
170
 
 
171
/* ================================================================
 
172
 * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
 
173
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK    0x00000100
 
174
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT    8
 
175
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB    8
 
176
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB    8
 
177
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
 
178
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT    0x00000000
 
179
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
 
180
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
 
181
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
 
182
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
 
183
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
 
184
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
 
185
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
 
186
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
 
187
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
 
188
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
 
189
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
 
190
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
 
191
 
 
192
/* ================================================================
 
193
 * Field info for register KA_OF_OFEM_INTERRUPT */
 
194
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK    0x00000100
 
195
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT    8
 
196
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB    8
 
197
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB    8
 
198
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
 
199
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
 
200
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000080
 
201
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT    7
 
202
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB    7
 
203
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB    7
 
204
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
 
205
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
 
206
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000040
 
207
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT    6
 
208
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB    6
 
209
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB    6
 
210
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
 
211
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
 
212
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK    0x00000020
 
213
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT    5
 
214
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB    5
 
215
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB    5
 
216
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
 
217
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
 
218
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK    0x00000010
 
219
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT    4
 
220
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB    4
 
221
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB    4
 
222
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
 
223
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
 
224
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK    0x00000008
 
225
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT    3
 
226
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB    3
 
227
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB    3
 
228
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
 
229
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
 
230
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK    0x00000004
 
231
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT    2
 
232
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB    2
 
233
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB    2
 
234
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
 
235
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
 
236
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK    0x00000002
 
237
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT    1
 
238
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB    1
 
239
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB    1
 
240
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
 
241
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
 
242
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK    0x00000001
 
243
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT    0
 
244
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB    0
 
245
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB    0
 
246
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
 
247
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
 
248
 
 
249
/* ================================================================
 
250
 * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
 
251
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00000100
 
252
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    8
 
253
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    8
 
254
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    8
 
255
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
256
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
 
257
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000080
 
258
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    7
 
259
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    7
 
260
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    7
 
261
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
262
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
 
263
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000040
 
264
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    6
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    6
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    6
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000020
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    5
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    5
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    5
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000010
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    4
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    4
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    4
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000008
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    3
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    3
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    3
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000004
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    2
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    2
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    2
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
292
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
 
295
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
 
296
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
 
297
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
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#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
 
299
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
 
300
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
 
301
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
 
302
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
 
303
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
304
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
 
305
 
 
306
/* ================================================================
 
307
 * Field info for register KA_OF_OFEM_SCRATCH */
 
308
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK    0xffffffff
 
309
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT    0
 
310
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB    31
 
311
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB    0
 
312
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
 
313
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT    0x00000000
 
314
 
 
315
/* ================================================================
 
316
 * Field info for register KA_OF_OFEM_SCRATCH_MASK */
 
317
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
 
318
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
 
319
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
 
320
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
 
321
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
 
322
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
 
323
 
 
324
#endif /* matches #ifndef HAL_KA_OF_AUTO_H */