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Viewing changes to roms/u-boot/arch/arm/cpu/armv7/omap5/hwinit.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/arm/cpu/armv7/omap5/hwinit.c
 
1
/*
 
2
 *
 
3
 * Functions for omap5 based boards.
 
4
 *
 
5
 * (C) Copyright 2011
 
6
 * Texas Instruments, <www.ti.com>
 
7
 *
 
8
 * Author :
 
9
 *      Aneesh V        <aneesh@ti.com>
 
10
 *      Steve Sakoman   <steve@sakoman.com>
 
11
 *      Sricharan       <r.sricharan@ti.com>
 
12
 *
 
13
 * SPDX-License-Identifier:     GPL-2.0+
 
14
 */
 
15
#include <common.h>
 
16
#include <asm/armv7.h>
 
17
#include <asm/arch/cpu.h>
 
18
#include <asm/arch/sys_proto.h>
 
19
#include <asm/arch/clock.h>
 
20
#include <linux/sizes.h>
 
21
#include <asm/utils.h>
 
22
#include <asm/arch/gpio.h>
 
23
#include <asm/emif.h>
 
24
#include <asm/omap_common.h>
 
25
 
 
26
DECLARE_GLOBAL_DATA_PTR;
 
27
 
 
28
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
 
29
 
 
30
static struct gpio_bank gpio_bank_54xx[8] = {
 
31
        { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
 
32
        { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
 
33
        { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
 
34
        { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
 
35
        { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
 
36
        { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
 
37
        { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
 
38
        { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
 
39
};
 
40
 
 
41
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
42
 
 
43
#ifdef CONFIG_SPL_BUILD
 
44
/* LPDDR2 specific IO settings */
 
45
static void io_settings_lpddr2(void)
 
46
{
 
47
        const struct ctrl_ioregs *ioregs;
 
48
 
 
49
        get_ioregs(&ioregs);
 
50
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
 
51
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
 
52
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
 
53
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
 
54
        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
 
55
        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
 
56
        writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
 
57
        writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
 
58
        writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
 
59
}
 
60
 
 
61
/* DDR3 specific IO settings */
 
62
static void io_settings_ddr3(void)
 
63
{
 
64
        u32 io_settings = 0;
 
65
        const struct ctrl_ioregs *ioregs;
 
66
 
 
67
        get_ioregs(&ioregs);
 
68
        writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
 
69
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
 
70
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
 
71
 
 
72
        writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
 
73
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
 
74
        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
 
75
 
 
76
        writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
 
77
        writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
 
78
        writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
 
79
 
 
80
        /* omap5432 does not use lpddr2 */
 
81
        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
 
82
        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
 
83
 
 
84
        writel(ioregs->ctrl_emif_sdram_config_ext,
 
85
               (*ctrl)->control_emif1_sdram_config_ext);
 
86
        writel(ioregs->ctrl_emif_sdram_config_ext,
 
87
               (*ctrl)->control_emif2_sdram_config_ext);
 
88
 
 
89
        if (is_omap54xx()) {
 
90
                /* Disable DLL select */
 
91
                io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
 
92
                                                        & 0xFFEFFFFF);
 
93
                writel(io_settings,
 
94
                        (*ctrl)->control_port_emif1_sdram_config);
 
95
 
 
96
                io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 
97
                                                        & 0xFFEFFFFF);
 
98
                writel(io_settings,
 
99
                        (*ctrl)->control_port_emif2_sdram_config);
 
100
        } else {
 
101
                writel(ioregs->ctrl_ddr_ctrl_ext_0,
 
102
                                (*ctrl)->control_ddr_control_ext_0);
 
103
        }
 
104
}
 
105
 
 
106
/*
 
107
 * Some tuning of IOs for optimal power and performance
 
108
 */
 
109
void do_io_settings(void)
 
110
{
 
111
        u32 io_settings = 0, mask = 0;
 
112
 
 
113
        /* Impedance settings EMMC, C2C 1,2, hsi2 */
 
114
        mask = (ds_mask << 2) | (ds_mask << 8) |
 
115
                (ds_mask << 16) | (ds_mask << 18);
 
116
        io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 
117
                                (~mask);
 
118
        io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 
119
                        (ds_45_ohm << 18) | (ds_60_ohm << 2);
 
120
        writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 
121
 
 
122
        /* Impedance settings Mcspi2 */
 
123
        mask = (ds_mask << 30);
 
124
        io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 
125
                        (~mask);
 
126
        io_settings |= (ds_60_ohm << 30);
 
127
        writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 
128
 
 
129
        /* Impedance settings C2C 3,4 */
 
130
        mask = (ds_mask << 14) | (ds_mask << 16);
 
131
        io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 
132
                        (~mask);
 
133
        io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 
134
        writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 
135
 
 
136
        /* Slew rate settings EMMC, C2C 1,2 */
 
137
        mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 
138
        io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 
139
                        (~mask);
 
140
        io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 
141
        writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 
142
 
 
143
        /* Slew rate settings hsi2, Mcspi2 */
 
144
        mask = (sc_mask << 24) | (sc_mask << 28);
 
145
        io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 
146
                        (~mask);
 
147
        io_settings |= (sc_fast << 28) | (sc_fast << 24);
 
148
        writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 
149
 
 
150
        /* Slew rate settings C2C 3,4 */
 
151
        mask = (sc_mask << 16) | (sc_mask << 18);
 
152
        io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 
153
                        (~mask);
 
154
        io_settings |= (sc_na << 16) | (sc_na << 18);
 
155
        writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 
156
 
 
157
        /* impedance and slew rate settings for usb */
 
158
        mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 
159
                (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 
160
        io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 
161
                        (~mask);
 
162
        io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 
163
                       (ds_60_ohm << 23) | (sc_fast << 20) |
 
164
                       (sc_fast << 17) | (sc_fast << 14);
 
165
        writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 
166
 
 
167
        if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 
168
                io_settings_lpddr2();
 
169
        else
 
170
                io_settings_ddr3();
 
171
}
 
172
 
 
173
static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 
174
        {0x45, 0x1},    /* 12 MHz   */
 
175
        {-1, -1},       /* 13 MHz   */
 
176
        {0x63, 0x2},    /* 16.8 MHz */
 
177
        {0x57, 0x2},    /* 19.2 MHz */
 
178
        {0x20, 0x1},    /* 26 MHz   */
 
179
        {-1, -1},       /* 27 MHz   */
 
180
        {0x41, 0x3}     /* 38.4 MHz */
 
181
};
 
182
 
 
183
void srcomp_enable(void)
 
184
{
 
185
        u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 
186
        u32 sysclk_ind  = get_sys_clk_index();
 
187
        u32 omap_rev    = omap_revision();
 
188
 
 
189
        if (!is_omap54xx())
 
190
                return;
 
191
 
 
192
        mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 
193
        div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 
194
 
 
195
        for (i = 0; i < 4; i++) {
 
196
                srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 
197
                srcomp_value &=
 
198
                        ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 
199
                srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 
200
                        (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 
201
                writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 
202
        }
 
203
 
 
204
        if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 
205
                clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 
206
                clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 
207
                writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 
208
 
 
209
                for (i = 0; i < 4; i++) {
 
210
                        srcomp_value =
 
211
                                readl((*ctrl)->control_srcomp_north_side + i*4);
 
212
                        srcomp_value &= ~PWRDWN_XS_MASK;
 
213
                        writel(srcomp_value,
 
214
                               (*ctrl)->control_srcomp_north_side + i*4);
 
215
 
 
216
                        while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 
217
                                & SRCODE_READ_XS_MASK) >>
 
218
                                SRCODE_READ_XS_SHIFT) == 0)
 
219
                                ;
 
220
 
 
221
                        srcomp_value =
 
222
                                readl((*ctrl)->control_srcomp_north_side + i*4);
 
223
                        srcomp_value &= ~OVERRIDE_XS_MASK;
 
224
                        writel(srcomp_value,
 
225
                               (*ctrl)->control_srcomp_north_side + i*4);
 
226
                }
 
227
        } else {
 
228
                srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 
229
                srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 
230
                                  DIVIDE_FACTOR_XS_MASK);
 
231
                srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 
232
                                (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 
233
                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 
234
 
 
235
                for (i = 0; i < 4; i++) {
 
236
                        srcomp_value =
 
237
                                readl((*ctrl)->control_srcomp_north_side + i*4);
 
238
                        srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 
239
                        writel(srcomp_value,
 
240
                               (*ctrl)->control_srcomp_north_side + i*4);
 
241
 
 
242
                        srcomp_value =
 
243
                                readl((*ctrl)->control_srcomp_north_side + i*4);
 
244
                        srcomp_value &= ~OVERRIDE_XS_MASK;
 
245
                        writel(srcomp_value,
 
246
                               (*ctrl)->control_srcomp_north_side + i*4);
 
247
                }
 
248
 
 
249
                srcomp_value =
 
250
                        readl((*ctrl)->control_srcomp_east_side_wkup);
 
251
                srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 
252
                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 
253
 
 
254
                srcomp_value =
 
255
                        readl((*ctrl)->control_srcomp_east_side_wkup);
 
256
                srcomp_value &= ~OVERRIDE_XS_MASK;
 
257
                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 
258
 
 
259
                clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 
260
                clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 
261
                writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 
262
 
 
263
                clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 
264
                clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 
265
                writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 
266
 
 
267
                for (i = 0; i < 4; i++) {
 
268
                        while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 
269
                                & SRCODE_READ_XS_MASK) >>
 
270
                                SRCODE_READ_XS_SHIFT) == 0)
 
271
                                ;
 
272
 
 
273
                        srcomp_value =
 
274
                                readl((*ctrl)->control_srcomp_north_side + i*4);
 
275
                        srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 
276
                        writel(srcomp_value,
 
277
                               (*ctrl)->control_srcomp_north_side + i*4);
 
278
                }
 
279
 
 
280
                while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 
281
                        SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 
282
                        ;
 
283
 
 
284
                srcomp_value =
 
285
                        readl((*ctrl)->control_srcomp_east_side_wkup);
 
286
                srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 
287
                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 
288
        }
 
289
}
 
290
#endif
 
291
 
 
292
void config_data_eye_leveling_samples(u32 emif_base)
 
293
{
 
294
        const struct ctrl_ioregs *ioregs;
 
295
 
 
296
        get_ioregs(&ioregs);
 
297
 
 
298
        /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 
299
        if (emif_base == EMIF1_BASE)
 
300
                writel(ioregs->ctrl_emif_sdram_config_ext_final,
 
301
                       (*ctrl)->control_emif1_sdram_config_ext);
 
302
        else if (emif_base == EMIF2_BASE)
 
303
                writel(ioregs->ctrl_emif_sdram_config_ext_final,
 
304
                       (*ctrl)->control_emif2_sdram_config_ext);
 
305
}
 
306
 
 
307
void init_omap_revision(void)
 
308
{
 
309
        /*
 
310
         * For some of the ES2/ES1 boards ID_CODE is not reliable:
 
311
         * Also, ES1 and ES2 have different ARM revisions
 
312
         * So use ARM revision for identification
 
313
         */
 
314
        unsigned int rev = cortex_rev();
 
315
 
 
316
        switch (readl(CONTROL_ID_CODE)) {
 
317
        case OMAP5430_CONTROL_ID_CODE_ES1_0:
 
318
                *omap_si_rev = OMAP5430_ES1_0;
 
319
                if (rev == MIDR_CORTEX_A15_R2P2)
 
320
                        *omap_si_rev = OMAP5430_ES2_0;
 
321
                break;
 
322
        case OMAP5432_CONTROL_ID_CODE_ES1_0:
 
323
                *omap_si_rev = OMAP5432_ES1_0;
 
324
                if (rev == MIDR_CORTEX_A15_R2P2)
 
325
                        *omap_si_rev = OMAP5432_ES2_0;
 
326
                break;
 
327
        case OMAP5430_CONTROL_ID_CODE_ES2_0:
 
328
                *omap_si_rev = OMAP5430_ES2_0;
 
329
                break;
 
330
        case OMAP5432_CONTROL_ID_CODE_ES2_0:
 
331
                *omap_si_rev = OMAP5432_ES2_0;
 
332
                break;
 
333
        case DRA752_CONTROL_ID_CODE_ES1_0:
 
334
                *omap_si_rev = DRA752_ES1_0;
 
335
                break;
 
336
        case DRA752_CONTROL_ID_CODE_ES1_1:
 
337
                *omap_si_rev = DRA752_ES1_1;
 
338
                break;
 
339
        default:
 
340
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 
341
        }
 
342
}
 
343
 
 
344
void reset_cpu(ulong ignored)
 
345
{
 
346
        u32 omap_rev = omap_revision();
 
347
 
 
348
        /*
 
349
         * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 
350
         * So use cold reset in case instead.
 
351
         */
 
352
        if (omap_rev == OMAP5430_ES1_0)
 
353
                writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 
354
        else
 
355
                writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 
356
}
 
357
 
 
358
u32 warm_reset(void)
 
359
{
 
360
        return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 
361
}
 
362
 
 
363
void setup_warmreset_time(void)
 
364
{
 
365
        u32 rst_time, rst_val;
 
366
 
 
367
#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 
368
        rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
 
369
#else
 
370
        rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
 
371
#endif
 
372
        rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
 
373
 
 
374
        if (rst_time > RSTTIME1_MASK)
 
375
                rst_time = RSTTIME1_MASK;
 
376
 
 
377
        rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 
378
        rst_val |= rst_time;
 
379
        writel(rst_val, (*prcm)->prm_rsttime);
 
380
}