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Viewing changes to roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
 
1
/*
 
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 * Memory setup for board based on EXYNOS4210
 
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 *
 
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 * Copyright (C) 2013 Samsung Electronics
 
5
 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
 
6
 *
 
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 * See file CREDITS for list of people who contributed to this
 
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 * project.
 
9
 *
 
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 * This program is free software; you can redistribute it and/or
 
11
 * modify it under the terms of the GNU General Public License as
 
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 * published by the Free Software Foundation; either version 2 of
 
13
 * the License, or (at your option) any later version.
 
14
 *
 
15
 * This program is distributed in the hope that it will be useful,
 
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
18
 * GNU General Public License for more details.
 
19
 *
 
20
 * You should have received a copy of the GNU General Public License
 
21
 * along with this program; if not, write to the Free Software
 
22
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 
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 * MA 02111-1307 USA
 
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 */
 
25
 
 
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#include <config.h>
 
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#include <asm/arch/dmc.h>
 
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#include "common_setup.h"
 
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#include "exynos4_setup.h"
 
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struct mem_timings mem = {
 
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        .direct_cmd_msr = {
 
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                DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
 
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        },
 
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        .timingref = TIMINGREF_VAL,
 
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        .timingrow = TIMINGROW_VAL,
 
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        .timingdata = TIMINGDATA_VAL,
 
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        .timingpower = TIMINGPOWER_VAL,
 
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        .zqcontrol = ZQ_CONTROL_VAL,
 
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        .control0 = CONTROL0_VAL,
 
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        .control1 = CONTROL1_VAL,
 
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        .control2 = CONTROL2_VAL,
 
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        .concontrol = CONCONTROL_VAL,
 
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        .prechconfig = PRECHCONFIG,
 
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        .memcontrol = MEMCONTROL_VAL,
 
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        .memconfig0 = MEMCONFIG0_VAL,
 
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        .memconfig1 = MEMCONFIG1_VAL,
 
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        .dll_resync = FORCE_DLL_RESYNC,
 
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        .dll_on = DLL_CONTROL_ON,
 
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};
 
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static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
 
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{
 
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        if (ctrl_no) {
 
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                writel((mem.control1 | (1 << mem.dll_resync)),
 
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                       &dmc->phycontrol1);
 
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                writel((mem.control1 | (0 << mem.dll_resync)),
 
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                       &dmc->phycontrol1);
 
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        } else {
 
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                writel((mem.control0 | (0 << mem.dll_on)),
 
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                       &dmc->phycontrol0);
 
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                writel((mem.control0 | (1 << mem.dll_on)),
 
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                       &dmc->phycontrol0);
 
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        }
 
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}
 
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static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
 
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{
 
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        int i;
 
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        unsigned long mask = 0;
 
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        if (chip)
 
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                mask = DIRECT_CMD_CHIP1_SHIFT;
 
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        for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
 
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                writel(mem.direct_cmd_msr[i] | mask,
 
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                       &dmc->directcmd);
 
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        }
 
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}
 
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static void dmc_init(struct exynos4_dmc *dmc)
 
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{
 
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        /*
 
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         * DLL Parameter Setting:
 
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         * Termination: Enable R/W
 
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         * Phase Delay for DQS Cleaning: 180' Shift
 
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         */
 
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        writel(mem.control1, &dmc->phycontrol1);
 
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        /*
 
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         * ZQ Calibration
 
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         * Termination: Disable
 
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         * Auto Calibration Start: Enable
 
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         */
 
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        writel(mem.zqcontrol, &dmc->phyzqcontrol);
 
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        sdelay(0x100000);
 
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        /*
 
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         * Update DLL Information:
 
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         * Force DLL Resyncronization
 
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         */
 
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        phy_control_reset(1, dmc);
 
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        phy_control_reset(0, dmc);
 
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        /* Set DLL Parameters */
 
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        writel(mem.control1, &dmc->phycontrol1);
 
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        /* DLL Start */
 
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        writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
 
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        writel(mem.control2, &dmc->phycontrol2);
 
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        /* Set Clock Ratio of Bus clock to Memory Clock */
 
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        writel(mem.concontrol, &dmc->concontrol);
 
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        /*
 
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         * Memor Burst length: 8
 
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         * Number of chips: 2
 
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         * Memory Bus width: 32 bit
 
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         * Memory Type: DDR3
 
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         * Additional Latancy for PLL: 1 Cycle
 
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         */
 
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        writel(mem.memcontrol, &dmc->memcontrol);
 
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        writel(mem.memconfig0, &dmc->memconfig0);
 
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        writel(mem.memconfig1, &dmc->memconfig1);
 
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        /* Config Precharge Policy */
 
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        writel(mem.prechconfig, &dmc->prechconfig);
 
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        /*
 
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         * TimingAref, TimingRow, TimingData, TimingPower Setting:
 
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         * Values as per Memory AC Parameters
 
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         */
 
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        writel(mem.timingref, &dmc->timingref);
 
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        writel(mem.timingrow, &dmc->timingrow);
 
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        writel(mem.timingdata, &dmc->timingdata);
 
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        writel(mem.timingpower, &dmc->timingpower);
 
137
 
 
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        /* Chip0: NOP Command: Assert and Hold CKE to high level */
 
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        writel(DIRECT_CMD_NOP, &dmc->directcmd);
 
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        sdelay(0x100000);
 
141
 
 
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        /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
 
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        dmc_config_mrs(dmc, 0);
 
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        sdelay(0x100000);
 
145
 
 
146
        /* Chip0: ZQINIT */
 
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        writel(DIRECT_CMD_ZQ, &dmc->directcmd);
 
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        sdelay(0x100000);
 
149
 
 
150
        writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
 
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        sdelay(0x100000);
 
152
 
 
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        /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
 
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        dmc_config_mrs(dmc, 1);
 
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        sdelay(0x100000);
 
156
 
 
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        /* Chip1: ZQINIT */
 
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        writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
 
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        sdelay(0x100000);
 
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        phy_control_reset(1, dmc);
 
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        sdelay(0x100000);
 
163
 
 
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        /* turn on DREX0, DREX1 */
 
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        writel((mem.concontrol | AREF_EN), &dmc->concontrol);
 
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}
 
167
 
 
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void mem_ctrl_init(int reset)
 
169
{
 
170
        struct exynos4_dmc *dmc;
 
171
 
 
172
        /*
 
173
         * Async bridge configuration at CPU_core:
 
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         * 1: half_sync
 
175
         * 0: full_sync
 
176
         */
 
177
        writel(1, ASYNC_CONFIG);
 
178
#ifdef CONFIG_ORIGEN
 
179
        /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 
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        writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
 
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                APB_SFR_INTERLEAVE_CONF_OFFSET);
 
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        /* Update MIU Configuration */
 
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        writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
 
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                APB_SFR_ARBRITATION_CONF_OFFSET);
 
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#else
 
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        writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
 
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                APB_SFR_INTERLEAVE_CONF_OFFSET);
 
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        writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
 
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        writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
 
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        writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
 
194
#ifdef CONFIG_MIU_LINEAR
 
195
        writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
 
197
        writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
 
199
        writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);
 
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        writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
 
203
        writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
 
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                ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
 
205
#endif
 
206
#endif
 
207
        /* DREX0 */
 
208
        dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
 
209
        dmc_init(dmc);
 
210
        dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
 
211
                                        + DMC_OFFSET);
 
212
        dmc_init(dmc);
 
213
}