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  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/ti/ti816x/evm.c
 
1
/*
 
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 * evm.c
 
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 *
 
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 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
 
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 * Antoine Tenart, <atenart@adeneo-embedded.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
9
 
 
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#include <common.h>
 
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#include <spl.h>
 
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#include <asm/cache.h>
 
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#include <asm/io.h>
 
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#include <asm/arch/clock.h>
 
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#include <asm/arch/cpu.h>
 
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#include <asm/arch/ddr_defs.h>
 
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#include <asm/arch/hardware.h>
 
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#include <asm/arch/sys_proto.h>
 
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#include <asm/arch/mmc_host_def.h>
 
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#include <asm/arch/mem.h>
 
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#include <asm/arch/mux.h>
 
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DECLARE_GLOBAL_DATA_PTR;
 
24
 
 
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int board_init(void)
 
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{
 
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        gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 
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        return 0;
 
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}
 
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#ifdef CONFIG_SPL_BUILD
 
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static struct module_pin_mux mmc_pin_mux[] = {
 
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        { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
 
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        { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
 
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        { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
 
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        { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
 
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        { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
 
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        { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
 
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        { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
 
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        { -1 },
 
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};
 
43
 
 
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const struct dmm_lisa_map_regs evm_lisa_map_regs = {
 
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        .dmm_lisa_map_0 = 0x00000000,
 
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        .dmm_lisa_map_1 = 0x00000000,
 
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        .dmm_lisa_map_2 = 0x80640300,
 
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        .dmm_lisa_map_3 = 0xC0640320,
 
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};
 
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/*
 
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 * DDR2 related definitions
 
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 */
 
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#ifdef CONFIG_TI816X_EVM_DDR2
 
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static struct ddr_data ddr2_data = {
 
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        .datardsratio0          = ((0x40<<10) | (0x40<<0)),
 
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        .datawdsratio0          = ((0x4A<<10) | (0x4A<<0)),
 
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        .datawiratio0           = ((0x0<<10) | (0x0<<0)),
 
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        .datagiratio0           = ((0x0<<10) | (0x0<<0)),
 
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        .datafwsratio0          = ((0x13A<<10) | (0x13A<<0)),
 
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        .datawrsratio0          = ((0x8A<<10) | (0x8A<<0)),
 
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};
 
63
 
 
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static struct cmd_control ddr2_ctrl = {
 
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        .cmd0csratio    = 0x80,
 
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        .cmd0iclkout    = 0x00,
 
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        .cmd1csratio    = 0x80,
 
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        .cmd1iclkout    = 0x00,
 
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        .cmd2csratio    = 0x80,
 
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        .cmd2iclkout    = 0x00,
 
73
 
 
74
};
 
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static struct emif_regs ddr2_emif0_regs = {
 
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        .sdram_config           = 0x43801A3A,
 
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        .ref_ctrl               = 0x10000C30,
 
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        .sdram_tim1             = 0x0AAB15E2,
 
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        .sdram_tim2             = 0x423631D2,
 
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        .sdram_tim3             = 0x0080032F,
 
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        .emif_ddr_phy_ctlr_1    = 0x0, /* depend on cpu rev, set later */
 
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};
 
84
 
 
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static struct emif_regs ddr2_emif1_regs = {
 
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        .sdram_config           = 0x43801A3A,
 
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        .ref_ctrl               = 0x10000C30,
 
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        .sdram_tim1             = 0x0AAB15E2,
 
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        .sdram_tim2             = 0x423631D2,
 
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        .sdram_tim3             = 0x0080032F,
 
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        .emif_ddr_phy_ctlr_1    = 0x0, /* depend on cpu rev, set later */
 
92
};
 
93
#endif
 
94
 
 
95
/*
 
96
 * DDR3 related definitions
 
97
 */
 
98
 
 
99
#if defined(CONFIG_TI816X_DDR_PLL_400)
 
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#define RD_DQS          0x03B
 
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#define WR_DQS          0x0A6
 
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#define RD_DQS_GATE     0x12A
 
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#define EMIF_SDCFG      0x62A41032
 
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#define EMIF_SDREF      0x10000C30
 
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#define EMIF_TIM1       0x0CCCE524
 
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#define EMIF_TIM2       0x30308023
 
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#define EMIF_TIM3       0x009F82CF
 
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#define EMIF_PHYCFG     0x0000010B
 
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#elif defined(CONFIG_TI816X_DDR_PLL_531)
 
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#define RD_DQS          0x039
 
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#define WR_DQS          0x0B4
 
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#define RD_DQS_GATE     0x13D
 
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#define EMIF_SDCFG      0x62A51832
 
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#define EMIF_SDREF      0x1000102E
 
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#define EMIF_TIM1       0x0EF136AC
 
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#define EMIF_TIM2       0x30408063
 
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#define EMIF_TIM3       0x009F83AF
 
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#define EMIF_PHYCFG     0x0000010C
 
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#elif defined(CONFIG_TI816X_DDR_PLL_675)
 
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#define RD_DQS          0x039
 
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#define WR_DQS          0x091
 
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#define RD_DQS_GATE     0x196
 
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#define EMIF_SDCFG      0x62A63032
 
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#define EMIF_SDREF      0x10001491
 
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#define EMIF_TIM1       0x13358875
 
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#define EMIF_TIM2       0x5051806C
 
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#define EMIF_TIM3       0x009F84AF
 
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#define EMIF_PHYCFG     0x0000010F
 
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#elif defined(CONFIG_TI816X_DDR_PLL_796)
 
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#define RD_DQS          0x035
 
131
#define WR_DQS          0x093
 
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#define RD_DQS_GATE     0x1B3
 
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#define EMIF_SDCFG      0x62A73832
 
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#define EMIF_SDREF      0x10001841
 
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#define EMIF_TIM1       0x1779C9FE
 
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#define EMIF_TIM2       0x50608074
 
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#define EMIF_TIM3       0x009F857F
 
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#define EMIF_PHYCFG     0x00000110
 
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#endif
 
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141
static struct ddr_data ddr3_data = {
 
142
        .datardsratio0          = ((RD_DQS<<10) | (RD_DQS<<0)),
 
143
        .datawdsratio0          = ((WR_DQS<<10) | (WR_DQS<<0)),
 
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        .datawiratio0           = ((0x20<<10) | 0x20<<0),
 
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        .datagiratio0           = ((0x20<<10) | 0x20<<0),
 
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        .datafwsratio0          = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 
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        .datawrsratio0          = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 
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};
 
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static const struct cmd_control ddr3_ctrl = {
 
151
        .cmd0csratio    = 0x100,
 
152
        .cmd0iclkout    = 0x001,
 
153
 
 
154
        .cmd1csratio    = 0x100,
 
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        .cmd1iclkout    = 0x001,
 
156
 
 
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        .cmd2csratio    = 0x100,
 
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        .cmd2iclkout    = 0x001,
 
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};
 
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static const struct emif_regs ddr3_emif0_regs = {
 
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        .sdram_config           = EMIF_SDCFG,
 
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        .ref_ctrl               = EMIF_SDREF,
 
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        .sdram_tim1             = EMIF_TIM1,
 
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        .sdram_tim2             = EMIF_TIM2,
 
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        .sdram_tim3             = EMIF_TIM3,
 
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        .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 
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};
 
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static const struct emif_regs ddr3_emif1_regs = {
 
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        .sdram_config           = EMIF_SDCFG,
 
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        .ref_ctrl               = EMIF_SDREF,
 
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        .sdram_tim1             = EMIF_TIM1,
 
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        .sdram_tim2             = EMIF_TIM2,
 
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        .sdram_tim3             = EMIF_TIM3,
 
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        .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 
177
};
 
178
 
 
179
void set_uart_mux_conf(void) {}
 
180
 
 
181
void set_mux_conf_regs(void)
 
182
{
 
183
        configure_module_pin_mux(mmc_pin_mux);
 
184
}
 
185
 
 
186
void sdram_init(void)
 
187
{
 
188
        config_dmm(&evm_lisa_map_regs);
 
189
 
 
190
#ifdef CONFIG_TI816X_EVM_DDR2
 
191
        if (CONFIG_TI816X_USE_EMIF0) {
 
192
                ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 
193
                        (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
 
194
                config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
 
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                           0);
 
196
        }
 
197
 
 
198
        if (CONFIG_TI816X_USE_EMIF1) {
 
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                ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
 
200
                        (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
 
201
                config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
 
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                           1);
 
203
        }
 
204
#endif
 
205
 
 
206
#ifdef CONFIG_TI816X_EVM_DDR3
 
207
        if (CONFIG_TI816X_USE_EMIF0)
 
208
                config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
 
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                           0);
 
210
 
 
211
        if (CONFIG_TI816X_USE_EMIF1)
 
212
                config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
 
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                           1);
 
214
#endif
 
215
}
 
216
#endif /* CONFIG_SPL_BUILD */