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Viewing changes to roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c
 
1
/*
 
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 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/io.h>
 
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#include <asm/arch/freeze_controller.h>
 
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#include <asm/arch/timer.h>
 
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#include <asm/errno.h>
 
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DECLARE_GLOBAL_DATA_PTR;
 
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static const struct socfpga_freeze_controller *freeze_controller_base =
 
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                (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
 
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19
/*
 
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 * Default state from cold reset is FREEZE_ALL; the global
 
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 * flag is set to TRUE to indicate the IO banks are frozen
 
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 */
 
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static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
 
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        = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
 
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        FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
 
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/* Freeze HPS IOs */
 
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void sys_mgr_frzctrl_freeze_req(void)
 
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{
 
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        u32 ioctrl_reg_offset;
 
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        u32 reg_value;
 
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        u32 reg_cfg_mask;
 
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        u32 channel_id;
 
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        /* select software FSM */
 
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        writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
 
37
 
 
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        /* Freeze channel 0 to 2 */
 
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        for (channel_id = 0; channel_id <= 2; channel_id++) {
 
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                ioctrl_reg_offset = (u32)(
 
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                        &freeze_controller_base->vioctrl +
 
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                        (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
 
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44
                /*
 
45
                 * Assert active low enrnsl, plniotri
 
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                 * and niotri signals
 
47
                 */
 
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                reg_cfg_mask =
 
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                        SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
 
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                        | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
 
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                        | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
 
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                clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
 
53
 
 
54
                /*
 
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                 * Note: Delay for 20ns at min
 
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                 * Assert active low bhniotri signal and de-assert
 
57
                 * active high csrdone
 
58
                 */
 
59
                reg_cfg_mask
 
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                        = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
 
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                        | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
 
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                clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
 
63
 
 
64
                /* Set global flag to indicate channel is frozen */
 
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                frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
 
66
        }
 
67
 
 
68
        /* Freeze channel 3 */
 
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        /*
 
70
         * Assert active low enrnsl, plniotri and
 
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         * niotri signals
 
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         */
 
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        reg_cfg_mask
 
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                = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
 
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                | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
 
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                | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
 
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        clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
 
78
 
 
79
        /*
 
80
         * assert active low bhniotri & nfrzdrv signals,
 
81
         * de-assert active high csrdone and assert
 
82
         * active high frzreg and nfrzdrv signals
 
83
         */
 
84
        reg_value = readl(&freeze_controller_base->hioctrl);
 
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        reg_cfg_mask
 
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                = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
 
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                | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
 
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        reg_value
 
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                = (reg_value & ~reg_cfg_mask)
 
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                | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
 
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                | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
 
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        writel(reg_value, &freeze_controller_base->hioctrl);
 
93
 
 
94
        /*
 
95
         * assert active high reinit signal and de-assert
 
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         * active high pllbiasen signals
 
97
         */
 
98
        reg_value = readl(&freeze_controller_base->hioctrl);
 
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        reg_value
 
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                = (reg_value &
 
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                ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
 
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                | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
 
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        writel(reg_value, &freeze_controller_base->hioctrl);
 
104
 
 
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        /* Set global flag to indicate channel is frozen */
 
106
        frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
 
107
}
 
108
 
 
109
/* Unfreeze/Thaw HPS IOs */
 
110
void sys_mgr_frzctrl_thaw_req(void)
 
111
{
 
112
        u32 ioctrl_reg_offset;
 
113
        u32 reg_cfg_mask;
 
114
        u32 reg_value;
 
115
        u32 channel_id;
 
116
 
 
117
        /* select software FSM */
 
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        writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
 
119
 
 
120
        /* Thaw channel 0 to 2 */
 
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        for (channel_id = 0; channel_id <= 2; channel_id++) {
 
122
                ioctrl_reg_offset
 
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                        = (u32)(&freeze_controller_base->vioctrl
 
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                                + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
 
125
 
 
126
                /*
 
127
                 * Assert active low bhniotri signal and
 
128
                 * de-assert active high csrdone
 
129
                 */
 
130
                reg_cfg_mask
 
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                        = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
 
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                        | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
 
133
                setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
 
134
 
 
135
                /*
 
136
                 * Note: Delay for 20ns at min
 
137
                 * de-assert active low plniotri and niotri signals
 
138
                 */
 
139
                reg_cfg_mask
 
140
                        = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
 
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                        | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
 
142
                setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
 
143
 
 
144
                /*
 
145
                 * Note: Delay for 20ns at min
 
146
                 * de-assert active low enrnsl signal
 
147
                 */
 
148
                setbits_le32(ioctrl_reg_offset,
 
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                        SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
 
150
 
 
151
                /* Set global flag to indicate channel is thawed */
 
152
                frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
 
153
        }
 
154
 
 
155
        /* Thaw channel 3 */
 
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        /* de-assert active high reinit signal */
 
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        clrbits_le32(&freeze_controller_base->hioctrl,
 
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                SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
 
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160
        /*
 
161
         * Note: Delay for 40ns at min
 
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         * assert active high pllbiasen signals
 
163
         */
 
164
        setbits_le32(&freeze_controller_base->hioctrl,
 
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                SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
 
166
 
 
167
        /*
 
168
         * Delay 1000 intosc. intosc is based on eosc1
 
169
         * Use worst case which is fatest eosc1=50MHz, delay required
 
170
         * is 1/50MHz * 1000 = 20us
 
171
         */
 
172
        udelay(20);
 
173
 
 
174
        /*
 
175
         * de-assert active low bhniotri signals,
 
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         * assert active high csrdone and nfrzdrv signal
 
177
         */
 
178
        reg_value = readl(&freeze_controller_base->hioctrl);
 
179
        reg_value = (reg_value
 
180
                | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
 
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                | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
 
182
                & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
 
183
        writel(reg_value, &freeze_controller_base->hioctrl);
 
184
 
 
185
        /*
 
186
         * Delay 33 intosc
 
187
         * Use worst case which is fatest eosc1=50MHz, delay required
 
188
         * is 1/50MHz * 33 = 660ns ~= 1us
 
189
         */
 
190
        udelay(1);
 
191
 
 
192
        /* de-assert active low plniotri and niotri signals */
 
193
        reg_cfg_mask
 
194
                = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
 
195
                | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
 
196
 
 
197
        setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
 
198
 
 
199
        /*
 
200
         * Note: Delay for 40ns at min
 
201
         * de-assert active high frzreg signal
 
202
         */
 
203
        clrbits_le32(&freeze_controller_base->hioctrl,
 
204
                SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
 
205
 
 
206
        /*
 
207
         * Note: Delay for 40ns at min
 
208
         * de-assert active low enrnsl signal
 
209
         */
 
210
        setbits_le32(&freeze_controller_base->hioctrl,
 
211
                SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
 
212
 
 
213
        /* Set global flag to indicate channel is thawed */
 
214
        frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
 
215
}