115
115
#define TCG_CT_CONST_MONE 0x800
117
117
/* parse target specific constraints */
118
static int target_parse_constraint(TCGArgConstraint *ct,
119
const char **pct_str)
118
static const char *target_parse_constraint(TCGArgConstraint *ct,
119
const char *ct_str, TCGType type)
121
const char *ct_str = *pct_str;
125
123
ct->ct |= TCG_CT_REG;
126
124
tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1);
344
339
/* Conditional select instructions. */
345
340
I3506_CSEL = 0x1a800000,
346
341
I3506_CSINC = 0x1a800400,
342
I3506_CSINV = 0x5a800000,
343
I3506_CSNEG = 0x5a800400,
348
345
/* Data-processing (1 source) instructions. */
346
I3507_CLZ = 0x5ac01000,
347
I3507_RBIT = 0x5ac00000,
349
348
I3507_REV16 = 0x5ac00400,
350
349
I3507_REV32 = 0x5ac00800,
351
350
I3507_REV64 = 0x5ac00c00,
870
static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a,
869
static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
871
870
TCGArg b, bool b_const, TCGLabel *l)
941
static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
940
static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
942
941
TCGReg rh, TCGReg al, TCGReg ah,
943
942
tcg_target_long bl, tcg_target_long bh,
944
943
bool const_bl, bool const_bh, bool sub)
998
997
tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1000
static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
1001
TCGReg a0, TCGArg b, bool const_b, bool is_ctz)
1006
tcg_out_insn(s, 3507, RBIT, ext, a1, a0);
1008
if (const_b && b == (ext ? 64 : 32)) {
1009
tcg_out_insn(s, 3507, CLZ, ext, d, a1);
1011
AArch64Insn sel = I3506_CSEL;
1013
tcg_out_cmp(s, ext, a0, 0, 1);
1014
tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1);
1020
} else if (b == 0) {
1023
tcg_out_movi(s, ext, d, b);
1027
tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE);
1001
1031
#ifdef CONFIG_SOFTMMU
1002
1032
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
1003
1033
* TCGMemOpIdx oi, uintptr_t ra)
1597
case INDEX_op_clz_i64:
1598
case INDEX_op_clz_i32:
1599
tcg_out_cltz(s, ext, a0, a1, a2, c2, false);
1601
case INDEX_op_ctz_i64:
1602
case INDEX_op_ctz_i32:
1603
tcg_out_cltz(s, ext, a0, a1, a2, c2, true);
1567
1606
case INDEX_op_brcond_i32:
1568
1607
a1 = (int32_t)a1;
1640
1679
tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
1682
case INDEX_op_extract_i64:
1683
case INDEX_op_extract_i32:
1684
tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
1687
case INDEX_op_sextract_i64:
1688
case INDEX_op_sextract_i32:
1689
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
1643
1692
case INDEX_op_add2_i32:
1644
1693
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
1645
1694
(int32_t)args[4], args[5], const_args[4],
1745
1794
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
1746
1795
{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
1747
1796
{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
1797
{ INDEX_op_clz_i32, { "r", "r", "rAL" } },
1798
{ INDEX_op_ctz_i32, { "r", "r", "rAL" } },
1748
1799
{ INDEX_op_shl_i64, { "r", "r", "ri" } },
1749
1800
{ INDEX_op_shr_i64, { "r", "r", "ri" } },
1750
1801
{ INDEX_op_sar_i64, { "r", "r", "ri" } },
1751
1802
{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
1752
1803
{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
1804
{ INDEX_op_clz_i64, { "r", "r", "rAL" } },
1805
{ INDEX_op_ctz_i64, { "r", "r", "rAL" } },
1754
1807
{ INDEX_op_brcond_i32, { "r", "rA" } },
1755
1808
{ INDEX_op_brcond_i64, { "r", "rA" } },
1786
1839
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
1787
1840
{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
1841
{ INDEX_op_extract_i32, { "r", "r" } },
1842
{ INDEX_op_extract_i64, { "r", "r" } },
1843
{ INDEX_op_sextract_i32, { "r", "r" } },
1844
{ INDEX_op_sextract_i64, { "r", "r" } },
1789
1846
{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
1790
1847
{ INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
1858
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
1860
int i, n = ARRAY_SIZE(aarch64_op_defs);
1862
for (i = 0; i < n; ++i) {
1863
if (aarch64_op_defs[i].op == op) {
1864
return &aarch64_op_defs[i];
1801
1870
static void tcg_target_init(TCGContext *s)
1803
1872
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1820
1889
tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
1821
1890
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
1822
1891
tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
1824
tcg_add_target_add_op_defs(aarch64_op_defs);
1827
1894
/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */