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Viewing changes to roms/u-boot/arch/m68k/include/asm/immap_5301x.h

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/m68k/include/asm/immap_5301x.h
 
1
/*
 
2
 * MCF5301x Internal Memory Map
 
3
 *
 
4
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 
5
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 
6
 *
 
7
 * SPDX-License-Identifier:     GPL-2.0+
 
8
 */
 
9
 
 
10
#ifndef __IMMAP_5301X__
 
11
#define __IMMAP_5301X__
 
12
 
 
13
#define MMAP_SCM1       (CONFIG_SYS_MBAR + 0x00000000)
 
14
#define MMAP_XBS        (CONFIG_SYS_MBAR + 0x00004000)
 
15
#define MMAP_FBCS       (CONFIG_SYS_MBAR + 0x00008000)
 
16
#define MMAP_MPU        (CONFIG_SYS_MBAR + 0x00014000)
 
17
#define MMAP_FEC0       (CONFIG_SYS_MBAR + 0x00030000)
 
18
#define MMAP_FEC1       (CONFIG_SYS_MBAR + 0x00034000)
 
19
#define MMAP_SCM2       (CONFIG_SYS_MBAR + 0x00040000)
 
20
#define MMAP_EDMA       (CONFIG_SYS_MBAR + 0x00044000)
 
21
#define MMAP_INTC0      (CONFIG_SYS_MBAR + 0x00048000)
 
22
#define MMAP_INTC1      (CONFIG_SYS_MBAR + 0x0004C000)
 
23
#define MMAP_INTCACK    (CONFIG_SYS_MBAR + 0x00054000)
 
24
#define MMAP_I2C        (CONFIG_SYS_MBAR + 0x00058000)
 
25
#define MMAP_DSPI       (CONFIG_SYS_MBAR + 0x0005C000)
 
26
#define MMAP_UART0      (CONFIG_SYS_MBAR + 0x00060000)
 
27
#define MMAP_UART1      (CONFIG_SYS_MBAR + 0x00064000)
 
28
#define MMAP_UART2      (CONFIG_SYS_MBAR + 0x00068000)
 
29
#define MMAP_DTMR0      (CONFIG_SYS_MBAR + 0x00070000)
 
30
#define MMAP_DTMR1      (CONFIG_SYS_MBAR + 0x00074000)
 
31
#define MMAP_DTMR2      (CONFIG_SYS_MBAR + 0x00078000)
 
32
#define MMAP_DTMR3      (CONFIG_SYS_MBAR + 0x0007C000)
 
33
#define MMAP_PIT0       (CONFIG_SYS_MBAR + 0x00080000)
 
34
#define MMAP_PIT1       (CONFIG_SYS_MBAR + 0x00084000)
 
35
#define MMAP_PIT2       (CONFIG_SYS_MBAR + 0x00088000)
 
36
#define MMAP_PIT3       (CONFIG_SYS_MBAR + 0x0008C000)
 
37
#define MMAP_EPORT0     (CONFIG_SYS_MBAR + 0x00090000)
 
38
#define MMAP_EPORT1     (CONFIG_SYS_MBAR + 0x00094000)
 
39
#define MMAP_VOICOD     (CONFIG_SYS_MBAR + 0x0009C000)
 
40
#define MMAP_RCM        (CONFIG_SYS_MBAR + 0x000A0000)
 
41
#define MMAP_CCM        (CONFIG_SYS_MBAR + 0x000A0004)
 
42
#define MMAP_GPIO       (CONFIG_SYS_MBAR + 0x000A4000)
 
43
#define MMAP_RTC        (CONFIG_SYS_MBAR + 0x000A8000)
 
44
#define MMAP_SIM        (CONFIG_SYS_MBAR + 0x000AC000)
 
45
#define MMAP_USBOTG     (CONFIG_SYS_MBAR + 0x000B0000)
 
46
#define MMAP_USBH       (CONFIG_SYS_MBAR + 0x000B4000)
 
47
#define MMAP_SDRAM      (CONFIG_SYS_MBAR + 0x000B8000)
 
48
#define MMAP_SSI        (CONFIG_SYS_MBAR + 0x000BC000)
 
49
#define MMAP_PLL        (CONFIG_SYS_MBAR + 0x000C0000)
 
50
#define MMAP_RNG        (CONFIG_SYS_MBAR + 0x000C4000)
 
51
#define MMAP_IIM        (CONFIG_SYS_MBAR + 0x000C8000)
 
52
#define MMAP_ESDHC      (CONFIG_SYS_MBAR + 0x000CC000)
 
53
 
 
54
#include <asm/coldfire/crossbar.h>
 
55
#include <asm/coldfire/dspi.h>
 
56
#include <asm/coldfire/edma.h>
 
57
#include <asm/coldfire/eport.h>
 
58
#include <asm/coldfire/flexbus.h>
 
59
#include <asm/coldfire/intctrl.h>
 
60
#include <asm/coldfire/ssi.h>
 
61
#include <asm/coldfire/rng.h>
 
62
#include <asm/rtc.h>
 
63
 
 
64
/* System Controller Module */
 
65
typedef struct scm1 {
 
66
        u32 mpr;                /* 0x00 Master Privilege */
 
67
        u32 rsvd1[7];
 
68
        u32 pacra;              /* 0x20 Peripheral Access Ctrl A */
 
69
        u32 pacrb;              /* 0x24 Peripheral Access Ctrl B */
 
70
        u32 pacrc;              /* 0x28 Peripheral Access Ctrl C */
 
71
        u32 pacrd;              /* 0x2C Peripheral Access Ctrl D */
 
72
        u32 rsvd2[4];
 
73
        u32 pacre;              /* 0x40 Peripheral Access Ctrl E */
 
74
        u32 pacrf;              /* 0x44 Peripheral Access Ctrl F */
 
75
        u32 pacrg;              /* 0x48 Peripheral Access Ctrl G */
 
76
} scm1_t;
 
77
 
 
78
typedef struct scm2 {
 
79
        u8 rsvd1[19];           /* 0x00 - 0x12 */
 
80
        u8 wcr;                 /* 0x13 */
 
81
        u16 rsvd2;              /* 0x14 - 0x15 */
 
82
        u16 cwcr;               /* 0x16 */
 
83
        u8 rsvd3[3];            /* 0x18 - 0x1A */
 
84
        u8 cwsr;                /* 0x1B */
 
85
        u8 rsvd4[3];            /* 0x1C - 0x1E */
 
86
        u8 scmisr;              /* 0x1F */
 
87
        u32 rsvd5;              /* 0x20 - 0x23 */
 
88
        u8 bcr;                 /* 0x24 */
 
89
        u8 rsvd6[74];           /* 0x25 - 0x6F */
 
90
        u32 cfadr;              /* 0x70 */
 
91
        u8 rsvd7;               /* 0x74 */
 
92
        u8 cfier;               /* 0x75 */
 
93
        u8 cfloc;               /* 0x76 */
 
94
        u8 cfatr;               /* 0x77 */
 
95
        u32 rsvd8;              /* 0x78 - 0x7B */
 
96
        u32 cfdtr;              /* 0x7C */
 
97
} scm2_t;
 
98
 
 
99
/* PWM module */
 
100
typedef struct pwm_ctrl {
 
101
        u8 en;                  /* 0x00 PWM Enable */
 
102
        u8 pol;                 /* 0x01 Polarity */
 
103
        u8 clk;                 /* 0x02 Clock Select */
 
104
        u8 prclk;               /* 0x03 Prescale Clock Select */
 
105
        u8 cae;                 /* 0x04 Center Align Enable */
 
106
        u8 ctl;                 /* 0x05 Ctrl */
 
107
        u8 res1[2];             /* 0x06 - 0x07 */
 
108
        u8 scla;                /* 0x08 Scale A */
 
109
        u8 sclb;                /* 0x09 Scale B */
 
110
        u8 res2[2];             /* 0x0A - 0x0B */
 
111
        u8 cnt0;                /* 0x0C Channel 0 Counter */
 
112
        u8 cnt1;                /* 0x0D Channel 1 Counter */
 
113
        u8 cnt2;                /* 0x0E Channel 2 Counter */
 
114
        u8 cnt3;                /* 0x0F Channel 3 Counter */
 
115
        u8 cnt4;                /* 0x10 Channel 4 Counter */
 
116
        u8 cnt5;                /* 0x11 Channel 5 Counter */
 
117
        u8 cnt6;                /* 0x12 Channel 6 Counter */
 
118
        u8 cnt7;                /* 0x13 Channel 7 Counter */
 
119
        u8 per0;                /* 0x14 Channel 0 Period */
 
120
        u8 per1;                /* 0x15 Channel 1 Period */
 
121
        u8 per2;                /* 0x16 Channel 2 Period */
 
122
        u8 per3;                /* 0x17 Channel 3 Period */
 
123
        u8 per4;                /* 0x18 Channel 4 Period */
 
124
        u8 per5;                /* 0x19 Channel 5 Period */
 
125
        u8 per6;                /* 0x1A Channel 6 Period */
 
126
        u8 per7;                /* 0x1B Channel 7 Period */
 
127
        u8 dty0;                /* 0x1C Channel 0 Duty */
 
128
        u8 dty1;                /* 0x1D Channel 1 Duty */
 
129
        u8 dty2;                /* 0x1E Channel 2 Duty */
 
130
        u8 dty3;                /* 0x1F Channel 3 Duty */
 
131
        u8 dty4;                /* 0x20 Channel 4 Duty */
 
132
        u8 dty5;                /* 0x21 Channel 5 Duty */
 
133
        u8 dty6;                /* 0x22 Channel 6 Duty */
 
134
        u8 dty7;                /* 0x23 Channel 7 Duty */
 
135
        u8 sdn;                 /* 0x24 Shutdown */
 
136
        u8 res3[3];             /* 0x25 - 0x27 */
 
137
} pwm_t;
 
138
 
 
139
/* Chip configuration module */
 
140
typedef struct rcm {
 
141
        u8 rcr;
 
142
        u8 rsr;
 
143
} rcm_t;
 
144
 
 
145
typedef struct ccm_ctrl {
 
146
        u16 ccr;                /* 0x00 Chip Cfg */
 
147
        u16 res1;               /* 0x02 */
 
148
        u16 rcon;               /* 0x04 Reset Cfg */
 
149
        u16 cir;                /* 0x06 Chip ID */
 
150
        u32 res2;               /* 0x08 */
 
151
        u16 misccr;             /* 0x0A Misc Ctrl */
 
152
        u16 cdr;                /* 0x0C Clock divider */
 
153
        u16 uhcsr;              /* 0x10 USB Host status */
 
154
        u16 uocsr;              /* 0x12 USB On-the-Go Status */
 
155
        u16 res3;               /* 0x14 */
 
156
        u16 codeccr;            /* 0x16 Codec Control */
 
157
        u16 misccr2;            /* 0x18 Misc2 Ctrl */
 
158
} ccm_t;
 
159
 
 
160
/* GPIO port */
 
161
typedef struct gpio_ctrl {
 
162
        /* Port Output Data */
 
163
        u8 podr_fbctl;          /* 0x00 */
 
164
        u8 podr_be;             /* 0x01 */
 
165
        u8 podr_cs;             /* 0x02 */
 
166
        u8 podr_dspi;           /* 0x03 */
 
167
        u8 res01;               /* 0x04 */
 
168
        u8 podr_fec0;           /* 0x05 */
 
169
        u8 podr_feci2c;         /* 0x06 */
 
170
        u8 res02[2];            /* 0x07 - 0x08 */
 
171
        u8 podr_simp1;          /* 0x09 */
 
172
        u8 podr_simp0;          /* 0x0A */
 
173
        u8 podr_timer;          /* 0x0B */
 
174
        u8 podr_uart;           /* 0x0C */
 
175
        u8 podr_debug;          /* 0x0D */
 
176
        u8 res03;               /* 0x0E */
 
177
        u8 podr_sdhc;           /* 0x0F */
 
178
        u8 podr_ssi;            /* 0x10 */
 
179
        u8 res04[3];            /* 0x11 - 0x13 */
 
180
 
 
181
        /* Port Data Direction */
 
182
        u8 pddr_fbctl;          /* 0x14 */
 
183
        u8 pddr_be;             /* 0x15 */
 
184
        u8 pddr_cs;             /* 0x16 */
 
185
        u8 pddr_dspi;           /* 0x17 */
 
186
        u8 res05;               /* 0x18 */
 
187
        u8 pddr_fec0;           /* 0x19 */
 
188
        u8 pddr_feci2c;         /* 0x1A */
 
189
        u8 res06[2];            /* 0x1B - 0x1C */
 
190
        u8 pddr_simp1;          /* 0x1D */
 
191
        u8 pddr_simp0;          /* 0x1E */
 
192
        u8 pddr_timer;          /* 0x1F */
 
193
        u8 pddr_uart;           /* 0x20 */
 
194
        u8 pddr_debug;          /* 0x21 */
 
195
        u8 res07;               /* 0x22 */
 
196
        u8 pddr_sdhc;           /* 0x23 */
 
197
        u8 pddr_ssi;            /* 0x24 */
 
198
        u8 res08[3];            /* 0x25 - 0x27 */
 
199
 
 
200
        /* Port Data Direction */
 
201
        u8 ppdr_fbctl;          /* 0x28 */
 
202
        u8 ppdr_be;             /* 0x29 */
 
203
        u8 ppdr_cs;             /* 0x2A */
 
204
        u8 ppdr_dspi;           /* 0x2B */
 
205
        u8 res09;               /* 0x2C */
 
206
        u8 ppdr_fec0;           /* 0x2D */
 
207
        u8 ppdr_feci2c;         /* 0x2E */
 
208
        u8 res10[2];            /* 0x2F - 0x30 */
 
209
        u8 ppdr_simp1;          /* 0x31 */
 
210
        u8 ppdr_simp0;          /* 0x32 */
 
211
        u8 ppdr_timer;          /* 0x33 */
 
212
        u8 ppdr_uart;           /* 0x34 */
 
213
        u8 ppdr_debug;          /* 0x35 */
 
214
        u8 res11;               /* 0x36 */
 
215
        u8 ppdr_sdhc;           /* 0x37 */
 
216
        u8 ppdr_ssi;            /* 0x38 */
 
217
        u8 res12[3];            /* 0x39 - 0x3B */
 
218
 
 
219
        /* Port Clear Output Data */
 
220
        u8 pclrr_fbctl;         /* 0x3C */
 
221
        u8 pclrr_be;            /* 0x3D */
 
222
        u8 pclrr_cs;            /* 0x3E */
 
223
        u8 pclrr_dspi;          /* 0x3F */
 
224
        u8 res13;               /* 0x40 */
 
225
        u8 pclrr_fec0;          /* 0x41 */
 
226
        u8 pclrr_feci2c;        /* 0x42 */
 
227
        u8 res14[2];            /* 0x43 - 0x44 */
 
228
        u8 pclrr_simp1;         /* 0x45 */
 
229
        u8 pclrr_simp0;         /* 0x46 */
 
230
        u8 pclrr_timer;         /* 0x47 */
 
231
        u8 pclrr_uart;          /* 0x48 */
 
232
        u8 pclrr_debug;         /* 0x49 */
 
233
        u8 res15;               /* 0x4A */
 
234
        u8 pclrr_sdhc;          /* 0x4B */
 
235
        u8 pclrr_ssi;           /* 0x4C */
 
236
        u8 res16[3];            /* 0x4D - 0x4F */
 
237
 
 
238
        /* Pin Assignment */
 
239
        u8 par_fbctl;           /* 0x50 */
 
240
        u8 par_be;              /* 0x51 */
 
241
        u8 par_cs;              /* 0x52 */
 
242
        u8 res17;               /* 0x53 */
 
243
        u8 par_dspih;           /* 0x54 */
 
244
        u8 par_dspil;           /* 0x55 */
 
245
        u8 par_fec;             /* 0x56 */
 
246
        u8 par_feci2c;          /* 0x57 */
 
247
        u8 par_irq0h;           /* 0x58 */
 
248
        u8 par_irq0l;           /* 0x59 */
 
249
        u8 par_irq1h;           /* 0x5A */
 
250
        u8 par_irq1l;           /* 0x5B */
 
251
        u8 par_simp1h;          /* 0x5C */
 
252
        u8 par_simp1l;          /* 0x5D */
 
253
        u8 par_simp0;           /* 0x5E */
 
254
        u8 par_timer;           /* 0x5F */
 
255
        u8 par_uart;            /* 0x60 */
 
256
        u8 res18;               /* 0x61 */
 
257
        u8 par_debug;           /* 0x62 */
 
258
        u8 par_sdhc;            /* 0x63 */
 
259
        u8 par_ssih;            /* 0x64 */
 
260
        u8 par_ssil;            /* 0x65 */
 
261
        u8 res19[2];            /* 0x66 - 0x67 */
 
262
 
 
263
        /* Mode Select Control */
 
264
        /* Drive Strength Control */
 
265
        u8 mscr_mscr1;          /* 0x68 */
 
266
        u8 mscr_mscr2;          /* 0x69 */
 
267
        u8 mscr_mscr3;          /* 0x6A */
 
268
        u8 mscr_mscr45;         /* 0x6B */
 
269
        u8 srcr_dspi;           /* 0x6C */
 
270
        u8 dscr_fec;            /* 0x6D */
 
271
        u8 srcr_i2c;            /* 0x6E */
 
272
        u8 srcr_irq;            /* 0x6F */
 
273
 
 
274
        u8 srcr_sim;            /* 0x70 */
 
275
        u8 srcr_timer;          /* 0x71 */
 
276
        u8 srcr_uart;           /* 0x72 */
 
277
        u8 res20;               /* 0x73 */
 
278
        u8 srcr_sdhc;           /* 0x74 */
 
279
        u8 srcr_ssi;            /* 0x75 */
 
280
        u8 res21[2];            /* 0x76 - 0x77 */
 
281
        u8 pcr_pcrh;            /* 0x78 */
 
282
        u8 pcr_pcrl;            /* 0x79 */
 
283
} gpio_t;
 
284
 
 
285
/* SDRAM controller */
 
286
typedef struct sdram_ctrl {
 
287
        u32 mode;               /* 0x00 Mode/Extended Mode */
 
288
        u32 ctrl;               /* 0x04 Ctrl */
 
289
        u32 cfg1;               /* 0x08 Cfg 1 */
 
290
        u32 cfg2;               /* 0x0C Cfg 2 */
 
291
        u32 res1[64];           /* 0x10 - 0x10F */
 
292
        u32 cs0;                /* 0x110 Chip Select 0 Cfg */
 
293
        u32 cs1;                /* 0x114 Chip Select 1 Cfg */
 
294
} sdram_t;
 
295
 
 
296
/* Clock Module */
 
297
typedef struct pll_ctrl {
 
298
        u32 pcr;                /* 0x00 Ctrl */
 
299
        u32 pdr;                /* 0x04 Divider */
 
300
        u32 psr;                /* 0x08 Status */
 
301
} pll_t;
 
302
 
 
303
typedef struct rtcex {
 
304
        u32 rsvd1[3];
 
305
        u32 gocu;
 
306
        u32 gocl;
 
307
} rtcex_t;
 
308
#endif                          /* __IMMAP_5301X__ */