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Viewing changes to roms/u-boot/board/exmeritus/hww1u1a/tlb.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/board/exmeritus/hww1u1a/tlb.c
 
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/*
 
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 * Copyright 2009-2010 eXMeritus, A Boeing Company
 
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 * Copyright 2008-2009 Freescale Semiconductor, Inc.
 
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 *
 
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 * (C) Copyright 2000
 
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 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/mmu.h>
 
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struct fsl_e_tlb_entry tlb_table[] = {
 
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        /* TLB 0 - for temp stack in cache */
 
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        SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      +  0 * 1024,
 
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                                CONFIG_SYS_INIT_RAM_ADDR_PHYS +  0 * 1024,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                                0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      +  4 * 1024,
 
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                                CONFIG_SYS_INIT_RAM_ADDR_PHYS +  4 * 1024,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                                0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      +  8 * 1024,
 
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                                CONFIG_SYS_INIT_RAM_ADDR_PHYS +  8 * 1024,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                                0, 0, BOOKE_PAGESZ_4K, 0),
 
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        SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      + 12 * 1024,
 
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                                CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, 0,
 
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                                0, 0, BOOKE_PAGESZ_4K, 0),
 
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        /* TLB 1 */
 
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        /* *I*** - Boot page */
 
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        SET_TLB_ENTRY(1,        CONFIG_BPTR_VIRT_ADDR,
 
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                                CONFIG_BPTR_VIRT_ADDR,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                                0, 0, BOOKE_PAGESZ_4K, 1),
 
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        /* *I*G* - CCSRBAR */
 
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        SET_TLB_ENTRY(1,        CONFIG_SYS_CCSRBAR,
 
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                                CONFIG_SYS_CCSRBAR_PHYS,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                                0, 1, BOOKE_PAGESZ_1M, 1),
 
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        /*
 
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         * W**G* - FLASH (Will be *I*G* after relocation to RAM)
 
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         *
 
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         * This maps both SPI FLASH chips (128MByte per chip)
 
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         */
 
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        SET_TLB_ENTRY(1,        CONFIG_SYS_FLASH_BASE,
 
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                                CONFIG_SYS_FLASH_BASE_PHYS,
 
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                                MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 
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                                0, 2, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * *I*G* - PCI memory
 
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         *
 
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         * We have 1.5GB total PCI-E memory space to map and we want to use
 
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         * the minimum possible number of TLB entries.  Since Book-E TLB
 
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         * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
 
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         */
 
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        SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_MEM_VIRT,
 
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                                CONFIG_SYS_PCIE3_MEM_PHYS,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                                0, 3, BOOKE_PAGESZ_1G, 1),
 
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        SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
 
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                                CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                                0, 4, BOOKE_PAGESZ_256M, 1),
 
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        SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
 
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                                CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                                0, 5, BOOKE_PAGESZ_256M, 1),
 
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        /*
 
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         * *I*G* - PCI I/O
 
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         *
 
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         * This one entry covers all 3 64k PCI-E I/O windows
 
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         */
 
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        SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_IO_VIRT,
 
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                                CONFIG_SYS_PCIE3_IO_PHYS,
 
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                                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
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                                0, 6, BOOKE_PAGESZ_256K, 1),
 
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};
 
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int num_tlb_entries = ARRAY_SIZE(tlb_table);