2
* Voipac PXA270 configuration file
4
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6
* SPDX-License-Identifier: GPL-2.0+
13
* High Level Board Configuration Options
15
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
17
#define CONFIG_SYS_TEXT_BASE 0xa0000000
21
#define CONFIG_SPL_ONENAND_SUPPORT
22
#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000
23
#define CONFIG_SPL_ONENAND_LOAD_SIZE \
24
(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
25
#define CONFIG_SPL_TEXT_BASE 0x5c000000
26
#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds"
30
* Environment settings
32
#define CONFIG_ENV_OVERWRITE
33
#define CONFIG_SYS_MALLOC_LEN (128*1024)
34
#define CONFIG_ARCH_CPU_INIT
35
#define CONFIG_BOOTCOMMAND \
36
"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
37
"bootm 0xa4000000; " \
39
"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
40
"bootm 0xa4000000; " \
42
"if ide reset && fatload ide 0 0xa4000000 uImage; then " \
43
"bootm 0xa4000000; " \
47
#define CONFIG_EXTRA_ENV_SETTINGS \
49
"onenand erase 0x0 0x80000 ; " \
50
"onenand write 0xa0000000 0x0 0x80000"
52
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
53
#define CONFIG_TIMESTAMP
54
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
55
#define CONFIG_CMDLINE_TAG
56
#define CONFIG_SETUP_MEMORY_TAGS
57
#define CONFIG_LZMA /* LZMA compression support */
58
#define CONFIG_OF_LIBFDT
61
* Serial Console Configuration
63
#define CONFIG_PXA_SERIAL
64
#define CONFIG_FFUART 1
65
#define CONFIG_CONS_INDEX 3
66
#define CONFIG_BAUDRATE 115200
69
* Bootloader Components Configuration
71
#include <config_cmd_default.h>
73
#define CONFIG_CMD_NET
74
#define CONFIG_CMD_ENV
75
#undef CONFIG_CMD_IMLS
76
#define CONFIG_CMD_MMC
77
#define CONFIG_CMD_USB
79
#define CONFIG_CMD_IDE
82
#undef CONFIG_CMD_FLASH
83
#define CONFIG_CMD_ONENAND
85
#define CONFIG_CMD_FLASH
86
#undef CONFIG_CMD_ONENAND
90
* Networking Configuration
91
* chip on the Voipac PXA270 board
94
#define CONFIG_CMD_PING
95
#define CONFIG_CMD_DHCP
97
#define CONFIG_DRIVER_DM9000 1
98
#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
99
#define DM9000_IO (CONFIG_DM9000_BASE)
100
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
101
#define CONFIG_NET_RETRY_COUNT 10
103
#define CONFIG_BOOTP_BOOTFILESIZE
104
#define CONFIG_BOOTP_BOOTPATH
105
#define CONFIG_BOOTP_GATEWAY
106
#define CONFIG_BOOTP_HOSTNAME
110
* MMC Card Configuration
112
#ifdef CONFIG_CMD_MMC
114
#define CONFIG_GENERIC_MMC
115
#define CONFIG_PXA_MMC_GENERIC
116
#define CONFIG_SYS_MMC_BASE 0xF0000000
117
#define CONFIG_CMD_FAT
118
#define CONFIG_CMD_EXT2
119
#define CONFIG_DOS_PARTITION
125
#ifdef CONFIG_CMD_KGDB
126
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
130
* HUSH Shell Configuration
132
#define CONFIG_SYS_HUSH_PARSER 1
134
#define CONFIG_SYS_LONGHELP
135
#ifdef CONFIG_SYS_HUSH_PARSER
136
#define CONFIG_SYS_PROMPT "$ "
139
#define CONFIG_SYS_CBSIZE 256
140
#define CONFIG_SYS_PBSIZE \
141
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
142
#define CONFIG_SYS_MAXARGS 16
143
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
144
#define CONFIG_SYS_DEVICE_NULLDEV 1
145
#define CONFIG_CMDLINE_EDITING 1
146
#define CONFIG_AUTO_COMPLETE 1
149
* Clock Configuration
151
#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
157
#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
158
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
159
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
161
#ifdef CONFIG_RAM_256M
162
#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
163
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
166
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
167
#ifdef CONFIG_RAM_256M
168
#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
170
#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
173
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
174
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
176
#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
177
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
178
#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
183
#define CONFIG_SYS_MONITOR_BASE 0x0
184
#define CONFIG_SYS_MONITOR_LEN 0x80000
185
#define CONFIG_ENV_ADDR \
186
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
187
#define CONFIG_ENV_SIZE 0x20000
188
#define CONFIG_ENV_SECT_SIZE 0x20000
190
#if defined(CONFIG_CMD_FLASH) /* NOR */
191
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
193
#ifdef CONFIG_RAM_256M
194
#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
197
#define CONFIG_SYS_FLASH_CFI
198
#define CONFIG_FLASH_CFI_DRIVER 1
200
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
201
#ifdef CONFIG_RAM_256M
202
#define CONFIG_SYS_MAX_FLASH_BANKS 2
203
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
205
#define CONFIG_SYS_MAX_FLASH_BANKS 1
206
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
209
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
210
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
212
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
213
#define CONFIG_SYS_FLASH_PROTECTION 1
215
#define CONFIG_ENV_IS_IN_FLASH 1
217
#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
218
#define CONFIG_SYS_NO_FLASH
219
#define CONFIG_SYS_ONENAND_BASE 0x00000000
221
#define CONFIG_ENV_IS_IN_ONENAND 1
224
#define CONFIG_SYS_NO_FLASH
225
#define CONFIG_SYS_ENV_IS_NOWHERE
231
#ifdef CONFIG_CMD_IDE
233
#undef CONFIG_IDE_LED
234
#undef CONFIG_IDE_RESET
238
#define CONFIG_SYS_IDE_MAXBUS 1
239
#define CONFIG_SYS_IDE_MAXDEVICE 1
241
#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
242
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
244
#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
245
#define CONFIG_SYS_ATA_REG_OFFSET 0x120
246
#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
248
#define CONFIG_SYS_ATA_STRIDE 2
254
#define CONFIG_SYS_GPSR0_VAL 0x01308800
255
#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
256
#define CONFIG_SYS_GPSR2_VAL 0x922ac000
257
#define CONFIG_SYS_GPSR3_VAL 0x0161e800
259
#define CONFIG_SYS_GPCR0_VAL 0x00010000
260
#define CONFIG_SYS_GPCR1_VAL 0x0
261
#define CONFIG_SYS_GPCR2_VAL 0x0
262
#define CONFIG_SYS_GPCR3_VAL 0x0
264
#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
265
#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
266
#define CONFIG_SYS_GPDR2_VAL 0x922affff
267
#define CONFIG_SYS_GPDR3_VAL 0x0161e904
269
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
270
#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
271
#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
272
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
273
#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
274
#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
275
#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
276
#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
278
#define CONFIG_SYS_PSSR_VAL 0x30
283
#define CONFIG_SYS_CKEN 0x00500240
284
#define CONFIG_SYS_CCCR 0x02000290
289
#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9
290
#define CONFIG_SYS_MSC1_VAL 0x02ccf974
291
#define CONFIG_SYS_MSC2_VAL 0x00000000
292
#ifdef CONFIG_RAM_256M
293
#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
295
#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
297
#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
298
#define CONFIG_SYS_MDMRS_VAL 0x00000000
299
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
300
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
301
#define CONFIG_SYS_MEM_BUF_IMP 0x0f
304
* PCMCIA and CF Interfaces
306
#define CONFIG_SYS_MECR_VAL 0x00000001
307
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
308
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
309
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
310
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
311
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
312
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
318
#define CONFIG_VOIPAC_LCD
324
#ifdef CONFIG_CMD_USB
325
#define CONFIG_USB_OHCI_NEW
326
#define CONFIG_SYS_USB_OHCI_CPU_INIT
327
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
328
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
329
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
330
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
331
#define CONFIG_USB_STORAGE
334
#endif /* __CONFIG_H */