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* PCI Enhanced Allocation
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/** Number of entries */
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#define PCIEA_ENTRIES 2
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#define PCIEA_ENTRIES_MASK 0x3f
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/** Entry descriptor */
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#define PCIEA_DESC_SIZE(desc) ( ( (desc) >> 0 ) & 0x7 )
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/** BAR equivalent indicator */
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#define PCIEA_DESC_BEI(desc) ( ( (desc) >> 4 ) & 0xf )
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/** BAR equivalent indicators */
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PCIEA_BEI_BAR_0 = 0, /**< Standard BAR 0 */
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PCIEA_BEI_BAR_1 = 1, /**< Standard BAR 1 */
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PCIEA_BEI_BAR_2 = 2, /**< Standard BAR 2 */
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PCIEA_BEI_BAR_3 = 3, /**< Standard BAR 3 */
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PCIEA_BEI_BAR_4 = 4, /**< Standard BAR 4 */
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PCIEA_BEI_BAR_5 = 5, /**< Standard BAR 5 */
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PCIEA_BEI_ROM = 8, /**< Expansion ROM BAR */
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PCIEA_BEI_VF_BAR_0 = 9, /**< Virtual function BAR 0 */
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PCIEA_BEI_VF_BAR_1 = 10, /**< Virtual function BAR 1 */
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PCIEA_BEI_VF_BAR_2 = 11, /**< Virtual function BAR 2 */
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PCIEA_BEI_VF_BAR_3 = 12, /**< Virtual function BAR 3 */
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PCIEA_BEI_VF_BAR_4 = 13, /**< Virtual function BAR 4 */
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PCIEA_BEI_VF_BAR_5 = 14, /**< Virtual function BAR 5 */
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/** Entry is enabled */
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#define PCIEA_DESC_ENABLED 0x80000000UL
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/** Base address low dword */
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#define PCIEA_LOW_BASE 4
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/** Limit low dword */
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#define PCIEA_LOW_LIMIT 8
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#define PCIEA_LOW_ATTR_64BIT 0x00000002UL
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/** Low dword attribute bit mask */
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#define PCIEA_LOW_ATTR_MASK 0x00000003UL
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/** Offset to high dwords */
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#define PCIEA_LOW_HIGH 8
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extern unsigned long pciea_bar_start ( struct pci_device *pci,
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extern unsigned long pciea_bar_size ( struct pci_device *pci,
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#endif /* _IPXE_PCIEA_H */