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Viewing changes to hw/arm/exynos4210.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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hw/arm/exynos4210.c
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
 
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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/* PMU SFR base address */
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#define EXYNOS4210_PMU_BASE_ADDR            0x10020000
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/* Clock controller SFR base address */
 
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#define EXYNOS4210_CLK_BASE_ADDR            0x10030000
 
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/* Display controllers (FIMD) */
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#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
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                       info->smp_loader_start);
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}
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static uint64_t exynos4210_calc_affinity(int cpu)
 
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{
 
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    uint64_t mp_affinity;
 
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    /* Exynos4210 has 0x9 as cluster ID */
 
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    mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu;
 
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    return mp_affinity;
 
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}
 
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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        unsigned long ram_size)
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{
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        }
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        s->cpu[n] = ARM_CPU(cpuobj);
 
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        object_property_set_int(cpuobj, exynos4210_calc_affinity(n),
 
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                                "mp-affinity", &error_abort);
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        object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
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                                "reset-cbar", &error_abort);
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        object_property_set_bool(cpuobj, true, "realized", &error_fatal);
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    */
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    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
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    sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
 
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    /* PWM */
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    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
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                          s->irq_table[exynos4210_get_irq(22, 0)],