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Viewing changes to roms/u-boot/drivers/ddr/fsl/arm_ddr_gen3.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/drivers/ddr/fsl/arm_ddr_gen3.c
 
1
/*
 
2
 * Copyright 2013 Freescale Semiconductor, Inc.
 
3
 *
 
4
 * SPDX-License-Identifier:     GPL-2.0+
 
5
 *
 
6
 * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
 
7
 */
 
8
 
 
9
#include <common.h>
 
10
#include <asm/io.h>
 
11
#include <fsl_ddr_sdram.h>
 
12
#include <asm/processor.h>
 
13
#include <fsl_immap.h>
 
14
#include <fsl_ddr.h>
 
15
 
 
16
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 
17
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 
18
#endif
 
19
 
 
20
 
 
21
/*
 
22
 * regs has the to-be-set values for DDR controller registers
 
23
 * ctrl_num is the DDR controller number
 
24
 * step: 0 goes through the initialization in one pass
 
25
 *       1 sets registers and returns before enabling controller
 
26
 *       2 resumes from step 1 and continues to initialize
 
27
 * Dividing the initialization to two steps to deassert DDR reset signal
 
28
 * to comply with JEDEC specs for RDIMMs.
 
29
 */
 
30
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
31
                             unsigned int ctrl_num, int step)
 
32
{
 
33
        unsigned int i, bus_width;
 
34
        struct ccsr_ddr __iomem *ddr;
 
35
        u32 temp_sdram_cfg;
 
36
        u32 total_gb_size_per_controller;
 
37
        int timeout;
 
38
 
 
39
        switch (ctrl_num) {
 
40
        case 0:
 
41
                ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
42
                break;
 
43
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 
44
        case 1:
 
45
                ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 
46
                break;
 
47
#endif
 
48
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 
49
        case 2:
 
50
                ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 
51
                break;
 
52
#endif
 
53
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 
54
        case 3:
 
55
                ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 
56
                break;
 
57
#endif
 
58
        default:
 
59
                printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
 
60
                return;
 
61
        }
 
62
 
 
63
        if (step == 2)
 
64
                goto step2;
 
65
 
 
66
        if (regs->ddr_eor)
 
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                ddr_out32(&ddr->eor, regs->ddr_eor);
 
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        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 
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                if (i == 0) {
 
70
                        ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 
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                        ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 
72
                        ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 
73
 
 
74
                } else if (i == 1) {
 
75
                        ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 
76
                        ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 
77
                        ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 
78
 
 
79
                } else if (i == 2) {
 
80
                        ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 
81
                        ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 
82
                        ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 
83
 
 
84
                } else if (i == 3) {
 
85
                        ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 
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                        ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 
87
                        ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 
88
                }
 
89
        }
 
90
 
 
91
        ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 
92
        ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 
93
        ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 
94
        ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 
95
        ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 
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        ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 
97
        ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 
98
        ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 
99
        ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 
100
        ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 
101
        ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 
102
        ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 
103
        ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 
104
        ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 
105
        ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 
106
        ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 
107
        ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 
108
        ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 
109
        ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 
110
 
 
111
        ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 
112
        ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 
113
        ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 
114
        ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 
115
#ifndef CONFIG_SYS_FSL_DDR_EMU
 
116
        /*
 
117
         * Skip these two registers if running on emulator
 
118
         * because emulator doesn't have skew between bytes.
 
119
         */
 
120
 
 
121
        if (regs->ddr_wrlvl_cntl_2)
 
122
                ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 
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        if (regs->ddr_wrlvl_cntl_3)
 
124
                ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 
125
#endif
 
126
 
 
127
        ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 
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        ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 
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        ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
130
        ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 
131
        ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 
132
        ddr_out32(&ddr->err_disable, regs->err_disable);
 
133
        ddr_out32(&ddr->err_int_en, regs->err_int_en);
 
134
        for (i = 0; i < 32; i++) {
 
135
                if (regs->debug[i]) {
 
136
                        debug("Write to debug_%d as %08x\n", i + 1,
 
137
                              regs->debug[i]);
 
138
                        ddr_out32(&ddr->debug[i], regs->debug[i]);
 
139
                }
 
140
        }
 
141
 
 
142
        /*
 
143
         * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 
144
         * deasserted. Clocks start when any chip select is enabled and clock
 
145
         * control register is set. Because all DDR components are connected to
 
146
         * one reset signal, this needs to be done in two steps. Step 1 is to
 
147
         * get the clocks started. Step 2 resumes after reset signal is
 
148
         * deasserted.
 
149
         */
 
150
        if (step == 1) {
 
151
                udelay(200);
 
152
                return;
 
153
        }
 
154
 
 
155
step2:
 
156
        /* Set, but do not enable the memory */
 
157
        temp_sdram_cfg = regs->ddr_sdram_cfg;
 
158
        temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 
159
        ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 
160
 
 
161
        /*
 
162
         * 500 painful micro-seconds must elapse between
 
163
         * the DDR clock setup and the DDR config enable.
 
164
         * DDR2 need 200 us, and DDR3 need 500 us from spec,
 
165
         * we choose the max, that is 500 us for all of case.
 
166
         */
 
167
        udelay(500);
 
168
        asm volatile("dsb sy;isb");
 
169
 
 
170
        /* Let the controller go */
 
171
        temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 
172
        ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 
173
        asm volatile("dsb sy;isb");
 
174
 
 
175
        total_gb_size_per_controller = 0;
 
176
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 
177
                if (!(regs->cs[i].config & 0x80000000))
 
178
                        continue;
 
179
                total_gb_size_per_controller += 1 << (
 
180
                        ((regs->cs[i].config >> 14) & 0x3) + 2 +
 
181
                        ((regs->cs[i].config >> 8) & 0x7) + 12 +
 
182
                        ((regs->cs[i].config >> 0) & 0x7) + 8 +
 
183
                        3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 
184
                        26);                    /* minus 26 (count of 64M) */
 
185
        }
 
186
        if (regs->cs[0].config & 0x20000000) {
 
187
                /* 2-way interleaving */
 
188
                total_gb_size_per_controller <<= 1;
 
189
        }
 
190
        /*
 
191
         * total memory / bus width = transactions needed
 
192
         * transactions needed / data rate = seconds
 
193
         * to add plenty of buffer, double the time
 
194
         * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 
195
         * Let's wait for 800ms
 
196
         */
 
197
        bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 
198
                        >> SDRAM_CFG_DBW_SHIFT);
 
199
        timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 
200
                (get_ddr_freq(0) >> 20)) << 1;
 
201
        total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 
202
        debug("total %d GB\n", total_gb_size_per_controller);
 
203
        debug("Need to wait up to %d * 10ms\n", timeout);
 
204
 
 
205
        /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 
206
        while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 
207
                (timeout >= 0)) {
 
208
                udelay(10000);          /* throttle polling rate */
 
209
                timeout--;
 
210
        }
 
211
 
 
212
        if (timeout <= 0)
 
213
                printf("Waiting for D_INIT timeout. Memory may not work.\n");
 
214
}