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Viewing changes to roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am33xx.c

  • Committer: Phil Dennis-Jordan
  • Date: 2017-07-21 08:03:43 UTC
  • mfrom: (1.1.1)
  • Revision ID: phil@philjordan.eu-20170721080343-2yr2vdj7713czahv
New upstream release 2.9.0.

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roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
 
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/*
 
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 * clock_am33xx.c
 
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 *
 
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 * clocks for AM33XX based boards
 
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 *
 
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 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
 
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 *
 
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 * SPDX-License-Identifier:     GPL-2.0+
 
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 */
 
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#include <common.h>
 
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#include <asm/arch/cpu.h>
 
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#include <asm/arch/clock.h>
 
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#include <asm/arch/hardware.h>
 
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#include <asm/io.h>
 
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#define OSC     (V_OSCK/1000000)
 
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
 
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 
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struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
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const struct dpll_regs dpll_mpu_regs = {
 
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        .cm_clkmode_dpll        = CM_WKUP + 0x88,
 
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        .cm_idlest_dpll         = CM_WKUP + 0x20,
 
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        .cm_clksel_dpll         = CM_WKUP + 0x2C,
 
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        .cm_div_m2_dpll         = CM_WKUP + 0xA8,
 
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};
 
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const struct dpll_regs dpll_core_regs = {
 
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        .cm_clkmode_dpll        = CM_WKUP + 0x90,
 
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        .cm_idlest_dpll         = CM_WKUP + 0x5C,
 
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        .cm_clksel_dpll         = CM_WKUP + 0x68,
 
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        .cm_div_m4_dpll         = CM_WKUP + 0x80,
 
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        .cm_div_m5_dpll         = CM_WKUP + 0x84,
 
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        .cm_div_m6_dpll         = CM_WKUP + 0xD8,
 
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};
 
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const struct dpll_regs dpll_per_regs = {
 
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        .cm_clkmode_dpll        = CM_WKUP + 0x8C,
 
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        .cm_idlest_dpll         = CM_WKUP + 0x70,
 
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        .cm_clksel_dpll         = CM_WKUP + 0x9C,
 
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        .cm_div_m2_dpll         = CM_WKUP + 0xAC,
 
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};
 
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const struct dpll_regs dpll_ddr_regs = {
 
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        .cm_clkmode_dpll        = CM_WKUP + 0x94,
 
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        .cm_idlest_dpll         = CM_WKUP + 0x34,
 
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        .cm_clksel_dpll         = CM_WKUP + 0x40,
 
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        .cm_div_m2_dpll         = CM_WKUP + 0xA0,
 
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};
 
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struct dpll_params dpll_mpu_opp100 = {
 
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                CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 
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const struct dpll_params dpll_core_opp100 = {
 
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                1000, OSC-1, -1, -1, 10, 8, 4};
 
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const struct dpll_params dpll_mpu = {
 
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                MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
 
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const struct dpll_params dpll_core = {
 
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                50, OSC-1, -1, -1, 1, 1, 1};
 
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const struct dpll_params dpll_per = {
 
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                960, OSC-1, 5, -1, -1, -1, -1};
 
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const struct dpll_params *get_dpll_mpu_params(void)
 
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{
 
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        return &dpll_mpu;
 
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}
 
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const struct dpll_params *get_dpll_core_params(void)
 
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{
 
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        return &dpll_core;
 
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}
 
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const struct dpll_params *get_dpll_per_params(void)
 
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{
 
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        return &dpll_per;
 
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}
 
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void setup_clocks_for_console(void)
 
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{
 
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        clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 
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                        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 
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                        CD_CLKCTRL_CLKTRCTRL_SHIFT);
 
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        clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 
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                        CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 
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                        CD_CLKCTRL_CLKTRCTRL_SHIFT);
 
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        clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
 
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                        MODULE_CLKCTRL_MODULEMODE_MASK,
 
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                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 
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                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
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        clrsetbits_le32(&cmper->uart1clkctrl,
 
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                        MODULE_CLKCTRL_MODULEMODE_MASK,
 
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                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 
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                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
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        clrsetbits_le32(&cmper->uart2clkctrl,
 
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                        MODULE_CLKCTRL_MODULEMODE_MASK,
 
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                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 
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                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
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        clrsetbits_le32(&cmper->uart3clkctrl,
 
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                        MODULE_CLKCTRL_MODULEMODE_MASK,
 
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                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 
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                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
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        clrsetbits_le32(&cmper->uart4clkctrl,
 
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                        MODULE_CLKCTRL_MODULEMODE_MASK,
 
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                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 
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                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
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        clrsetbits_le32(&cmper->uart5clkctrl,
 
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                        MODULE_CLKCTRL_MODULEMODE_MASK,
 
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                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 
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                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
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}
 
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void enable_basic_clocks(void)
 
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{
 
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        u32 *const clk_domains[] = {
 
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                &cmper->l3clkstctrl,
 
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                &cmper->l4fwclkstctrl,
 
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                &cmper->l3sclkstctrl,
 
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                &cmper->l4lsclkstctrl,
 
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                &cmwkup->wkclkstctrl,
 
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                &cmper->emiffwclkctrl,
 
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                &cmrtc->clkstctrl,
 
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                0
 
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        };
 
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        u32 *const clk_modules_explicit_en[] = {
 
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                &cmper->l3clkctrl,
 
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                &cmper->l4lsclkctrl,
 
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                &cmper->l4fwclkctrl,
 
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                &cmwkup->wkl4wkclkctrl,
 
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                &cmper->l3instrclkctrl,
 
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                &cmper->l4hsclkctrl,
 
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                &cmwkup->wkgpio0clkctrl,
 
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                &cmwkup->wkctrlclkctrl,
 
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                &cmper->timer2clkctrl,
 
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                &cmper->gpmcclkctrl,
 
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                &cmper->elmclkctrl,
 
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                &cmper->mmc0clkctrl,
 
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                &cmper->mmc1clkctrl,
 
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                &cmwkup->wkup_i2c0ctrl,
 
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                &cmper->gpio1clkctrl,
 
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                &cmper->gpio2clkctrl,
 
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                &cmper->gpio3clkctrl,
 
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                &cmper->i2c1clkctrl,
 
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                &cmper->cpgmac0clkctrl,
 
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                &cmper->spi0clkctrl,
 
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                &cmrtc->rtcclkctrl,
 
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                &cmper->usb0clkctrl,
 
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                &cmper->emiffwclkctrl,
 
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                &cmper->emifclkctrl,
 
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                0
 
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        };
 
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        do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
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        /* Select the Master osc 24 MHZ as Timer2 clock source */
 
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        writel(0x1, &cmdpll->clktimer2clk);
 
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}