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#include <linux/spinlock.h>
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#include <linux/dma-mapping.h>
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#include <asm/scatterlist.h>
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#include <asm/machvec.h>
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* The following structure is used to manage multiple PCI busses.
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struct pci_iommu_arena;
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/* A controller. Used to manage multiple PCI busses. */
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struct pci_controller {
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struct pci_controller *next;
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struct resource *io_space;
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struct resource *mem_space;
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/* The following are for reporting to userland. The invariant is
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that if we report a BWX-capable dense memory, we do not report
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a sparse memory at all, even if it exists. */
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unsigned long sparse_mem_base;
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unsigned long dense_mem_base;
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unsigned long sparse_io_base;
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unsigned long dense_io_base;
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/* This one's for the kernel only. It's in KSEG somewhere. */
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unsigned long config_space_base;
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/* For compatibility with current (as of July 2003) pciutils
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and XFree86. Eventually will be removed. */
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unsigned int need_domain_info;
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struct pci_iommu_arena *sg_pci;
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struct pci_iommu_arena *sg_isa;
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/* Override the logic in pci_scan_bus for skipping already-configured
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO alpha_mv.min_io_address
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#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address
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extern void pcibios_set_master(struct pci_dev *dev);
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extern inline void pcibios_penalize_isa_irq(int irq, int active)
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/* We don't do dynamic PCI IRQ allocation */
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/* The PCI address space does not equal the physical memory address space.
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The networking and block device layers use this boolean for bounce buffer
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#define PCI_DMA_BUS_IS_PHYS 0
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/* implement the pci_ DMA API in terms of the generic device dma_ one */
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#include <asm-generic/pci-dma-compat.h>
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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unsigned long cacheline_size;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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cacheline_size = 1024;
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_BOUNDARY;
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*strategy_parameter = cacheline_size;
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/* TODO: integrate with include/asm-generic/pci.h ? */
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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return channel ? 15 : 14;
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extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
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extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
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static inline int pci_proc_domain(struct pci_bus *bus)
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struct pci_controller *hose = bus->sysdata;
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return hose->need_domain_info;
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#endif /* __KERNEL__ */
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/* Values for the `which' argument to sys_pciconfig_iobase. */
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#define IOBASE_HOSE 0
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#define IOBASE_SPARSE_MEM 1
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#define IOBASE_DENSE_MEM 2
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#define IOBASE_SPARSE_IO 3
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#define IOBASE_DENSE_IO 4
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#define IOBASE_ROOT_BUS 5
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#define IOBASE_FROM_HOSE 0x10000
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extern struct pci_dev *isa_bridge;
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extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
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extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state);
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extern void pci_adjust_legacy_attr(struct pci_bus *bus,
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enum pci_mmap_state mmap_type);
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#define HAVE_PCI_LEGACY 1
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extern int pci_create_resource_files(struct pci_dev *dev);
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extern void pci_remove_resource_files(struct pci_dev *dev);
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#endif /* __ALPHA_PCI_H */