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* Freescale SPI controller driver.
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* Maintainer: Kumar Gala
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* Copyright (C) 2006 Polycom, Inc.
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* Copyright 2010 Freescale Semiconductor, Inc.
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_devices.h>
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#include <linux/dma-mapping.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <sysdev/fsl_soc.h>
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#include "spi-fsl-lib.h"
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/* CPM1 and CPM2 are mutually exclusive. */
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#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
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#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
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/* SPI Controller registers */
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/* SPI Controller mode register definitions */
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_CI_INACTIVEHIGH (1 << 29)
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#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
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#define SPMODE_DIV16 (1 << 27)
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#define SPMODE_REV (1 << 26)
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#define SPMODE_MS (1 << 25)
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#define SPMODE_ENABLE (1 << 24)
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#define SPMODE_LEN(x) ((x) << 20)
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#define SPMODE_PM(x) ((x) << 16)
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#define SPMODE_OP (1 << 14)
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#define SPMODE_CG(x) ((x) << 7)
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* Default for SPI Mode:
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* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
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#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
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SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
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/* SPIE register values */
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#define SPIE_NE 0x00000200 /* Not empty */
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#define SPIE_NF 0x00000100 /* Not full */
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/* SPIM register values */
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
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#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
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/* SPCOM register values */
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#define SPCOM_STR (1 << 23) /* Start transmit */
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#define SPI_PRAM_SIZE 0x100
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#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
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static void *fsl_dummy_rx;
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static DEFINE_MUTEX(fsl_dummy_rx_lock);
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static int fsl_dummy_rx_refcnt;
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static void fsl_spi_change_mode(struct spi_device *spi)
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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__be32 __iomem *mode = ®_base->mode;
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if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
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/* Turn off IRQs locally to minimize time that SPI is disabled. */
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
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/* When in CPM mode, we need to reinit tx and rx. */
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if (mspi->flags & SPI_CPM_MODE) {
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if (mspi->flags & SPI_QE) {
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qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
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QE_CR_PROTOCOL_UNSPECIFIED, 0);
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cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
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if (mspi->flags & SPI_CPM1) {
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out_be16(&mspi->pram->rbptr,
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in_be16(&mspi->pram->rbase));
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out_be16(&mspi->pram->tbptr,
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in_be16(&mspi->pram->tbase));
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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local_irq_restore(flags);
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static void fsl_spi_chipselect(struct spi_device *spi, int value)
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
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bool pol = spi->mode & SPI_CS_HIGH;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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if (value == BITBANG_CS_INACTIVE) {
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if (pdata->cs_control)
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pdata->cs_control(spi, !pol);
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if (value == BITBANG_CS_ACTIVE) {
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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fsl_spi_change_mode(spi);
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if (pdata->cs_control)
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pdata->cs_control(spi, pol);
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static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
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struct spi_device *spi,
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struct mpc8xxx_spi *mpc8xxx_spi,
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if (bits_per_word <= 8) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u8;
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cs->get_tx = mpc8xxx_spi_tx_buf_u8;
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if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
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} else if (bits_per_word <= 16) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u16;
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cs->get_tx = mpc8xxx_spi_tx_buf_u16;
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if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
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} else if (bits_per_word <= 32) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u32;
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cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
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spi->mode & SPI_LSB_FIRST) {
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if (bits_per_word <= 8)
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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return bits_per_word;
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static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
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struct spi_device *spi,
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/* QE uses Little Endian for words > 8
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* so transform all words > 8 into 8 bits
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* Unfortnatly that doesn't work for LSB so
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* reject these for now */
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/* Note: 32 bits word, LSB works iff
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* tfcr/rfcr is set to CPMFCR_GBL */
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if (spi->mode & SPI_LSB_FIRST &&
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if (bits_per_word > 8)
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return 8; /* pretend its 8 bits */
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return bits_per_word;
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static int fsl_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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struct mpc8xxx_spi *mpc8xxx_spi;
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int bits_per_word = 0;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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bits_per_word = t->bits_per_word;
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/* spi_transfer level calls that work per-word */
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bits_per_word = spi->bits_per_word;
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/* Make sure its a bit width we support [4..16, 32] */
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if ((bits_per_word < 4)
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|| ((bits_per_word > 16) && (bits_per_word != 32)))
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hz = spi->max_speed_hz;
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if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
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bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
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else if (mpc8xxx_spi->flags & SPI_QE)
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bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
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if (bits_per_word < 0)
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return bits_per_word;
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if (bits_per_word == 32)
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
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cs->hw_mode |= SPMODE_LEN(bits_per_word);
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= SPMODE_DIV16;
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
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WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
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"Will use %d Hz instead.\n", dev_name(&spi->dev),
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hz, mpc8xxx_spi->spibrg / 1024);
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
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cs->hw_mode |= SPMODE_PM(pm);
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fsl_spi_change_mode(spi);
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static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
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struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
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struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
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unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
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unsigned int xfer_ofs;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
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if (mspi->rx_dma == mspi->dma_dummy_rx)
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out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma);
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out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
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out_be16(&rx_bd->cbd_datlen, 0);
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out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
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if (mspi->tx_dma == mspi->dma_dummy_tx)
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out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma);
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out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
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out_be16(&tx_bd->cbd_datlen, xfer_len);
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out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
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mpc8xxx_spi_write_reg(®_base->command, SPCOM_STR);
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static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, bool is_dma_mapped)
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struct device *dev = mspi->dev;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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mspi->map_tx_dma = 0;
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mspi->map_rx_dma = 0;
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mspi->map_tx_dma = 1;
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mspi->map_rx_dma = 1;
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mspi->tx_dma = mspi->dma_dummy_tx;
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mspi->map_tx_dma = 0;
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mspi->rx_dma = mspi->dma_dummy_rx;
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mspi->map_rx_dma = 0;
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if (mspi->map_tx_dma) {
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void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
352
mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
354
if (dma_mapping_error(dev, mspi->tx_dma)) {
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dev_err(dev, "unable to map tx dma\n");
358
} else if (t->tx_buf) {
359
mspi->tx_dma = t->tx_dma;
362
if (mspi->map_rx_dma) {
363
mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
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if (dma_mapping_error(dev, mspi->rx_dma)) {
366
dev_err(dev, "unable to map rx dma\n");
369
} else if (t->rx_buf) {
370
mspi->rx_dma = t->rx_dma;
374
mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB);
376
mspi->xfer_in_progress = t;
377
mspi->count = t->len;
379
/* start CPM transfers */
380
fsl_spi_cpm_bufs_start(mspi);
385
if (mspi->map_tx_dma)
386
dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
390
static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
392
struct device *dev = mspi->dev;
393
struct spi_transfer *t = mspi->xfer_in_progress;
395
if (mspi->map_tx_dma)
396
dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
397
if (mspi->map_rx_dma)
398
dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
399
mspi->xfer_in_progress = NULL;
402
static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
403
struct spi_transfer *t, unsigned int len)
406
struct fsl_spi_reg *reg_base = mspi->reg_base;
411
mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
414
word = mspi->get_tx(mspi);
415
mpc8xxx_spi_write_reg(®_base->transmit, word);
420
static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
423
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
424
struct fsl_spi_reg *reg_base;
425
unsigned int len = t->len;
429
reg_base = mpc8xxx_spi->reg_base;
430
bits_per_word = spi->bits_per_word;
431
if (t->bits_per_word)
432
bits_per_word = t->bits_per_word;
434
if (bits_per_word > 8) {
435
/* invalid length? */
440
if (bits_per_word > 16) {
441
/* invalid length? */
447
mpc8xxx_spi->tx = t->tx_buf;
448
mpc8xxx_spi->rx = t->rx_buf;
450
INIT_COMPLETION(mpc8xxx_spi->done);
452
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
453
ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
455
ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
459
wait_for_completion(&mpc8xxx_spi->done);
461
/* disable rx ints */
462
mpc8xxx_spi_write_reg(®_base->mask, 0);
464
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
465
fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
467
return mpc8xxx_spi->count;
470
static void fsl_spi_do_one_msg(struct spi_message *m)
472
struct spi_device *spi = m->spi;
473
struct spi_transfer *t;
474
unsigned int cs_change;
475
const int nsecs = 50;
480
list_for_each_entry(t, &m->transfers, transfer_list) {
481
if (t->bits_per_word || t->speed_hz) {
482
/* Don't allow changes if CS is active */
486
status = fsl_spi_setup_transfer(spi, t);
492
fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
495
cs_change = t->cs_change;
497
status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
502
m->actual_length += t->len;
505
udelay(t->delay_usecs);
509
fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
515
m->complete(m->context);
517
if (status || !cs_change) {
519
fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
522
fsl_spi_setup_transfer(spi, NULL);
525
static int fsl_spi_setup(struct spi_device *spi)
527
struct mpc8xxx_spi *mpc8xxx_spi;
528
struct fsl_spi_reg *reg_base;
531
struct spi_mpc8xxx_cs *cs = spi->controller_state;
533
if (!spi->max_speed_hz)
537
cs = kzalloc(sizeof *cs, GFP_KERNEL);
540
spi->controller_state = cs;
542
mpc8xxx_spi = spi_master_get_devdata(spi->master);
544
reg_base = mpc8xxx_spi->reg_base;
546
hw_mode = cs->hw_mode; /* Save original settings */
547
cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
548
/* mask out bits we are going to set */
549
cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
550
| SPMODE_REV | SPMODE_LOOP);
552
if (spi->mode & SPI_CPHA)
553
cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
554
if (spi->mode & SPI_CPOL)
555
cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
556
if (!(spi->mode & SPI_LSB_FIRST))
557
cs->hw_mode |= SPMODE_REV;
558
if (spi->mode & SPI_LOOP)
559
cs->hw_mode |= SPMODE_LOOP;
561
retval = fsl_spi_setup_transfer(spi, NULL);
563
cs->hw_mode = hw_mode; /* Restore settings */
569
static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
572
struct fsl_spi_reg *reg_base = mspi->reg_base;
574
dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
575
in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
577
len = in_be16(&mspi->rx_bd->cbd_datlen);
578
if (len > mspi->count) {
583
/* Clear the events */
584
mpc8xxx_spi_write_reg(®_base->event, events);
588
fsl_spi_cpm_bufs_start(mspi);
590
complete(&mspi->done);
593
static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
595
struct fsl_spi_reg *reg_base = mspi->reg_base;
597
/* We need handle RX first */
598
if (events & SPIE_NE) {
599
u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
602
mspi->get_rx(rx_data, mspi);
605
if ((events & SPIE_NF) == 0)
606
/* spin until TX is done */
608
mpc8xxx_spi_read_reg(®_base->event)) &
612
/* Clear the events */
613
mpc8xxx_spi_write_reg(®_base->event, events);
617
u32 word = mspi->get_tx(mspi);
619
mpc8xxx_spi_write_reg(®_base->transmit, word);
621
complete(&mspi->done);
625
static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
627
struct mpc8xxx_spi *mspi = context_data;
628
irqreturn_t ret = IRQ_NONE;
630
struct fsl_spi_reg *reg_base = mspi->reg_base;
632
/* Get interrupt events(tx/rx) */
633
events = mpc8xxx_spi_read_reg(®_base->event);
637
dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
639
if (mspi->flags & SPI_CPM_MODE)
640
fsl_spi_cpm_irq(mspi, events);
642
fsl_spi_cpu_irq(mspi, events);
647
static void *fsl_spi_alloc_dummy_rx(void)
649
mutex_lock(&fsl_dummy_rx_lock);
652
fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
654
fsl_dummy_rx_refcnt++;
656
mutex_unlock(&fsl_dummy_rx_lock);
661
static void fsl_spi_free_dummy_rx(void)
663
mutex_lock(&fsl_dummy_rx_lock);
665
switch (fsl_dummy_rx_refcnt) {
674
fsl_dummy_rx_refcnt--;
678
mutex_unlock(&fsl_dummy_rx_lock);
681
static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
683
struct device *dev = mspi->dev;
684
struct device_node *np = dev->of_node;
687
void __iomem *spi_base;
688
unsigned long pram_ofs = -ENOMEM;
690
/* Can't use of_address_to_resource(), QE muram isn't at 0. */
691
iprop = of_get_property(np, "reg", &size);
693
/* QE with a fixed pram location? */
694
if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
695
return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
697
/* QE but with a dynamic pram location? */
698
if (mspi->flags & SPI_QE) {
699
pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
700
qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
701
QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
705
spi_base = of_iomap(np, 1);
706
if (spi_base == NULL)
709
if (mspi->flags & SPI_CPM2) {
710
pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
711
out_be16(spi_base, pram_ofs);
713
struct spi_pram __iomem *pram = spi_base;
714
u16 rpbase = in_be16(&pram->rpbase);
716
/* Microcode relocation patch applied? */
720
pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
721
out_be16(spi_base, pram_ofs);
729
static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
731
struct device *dev = mspi->dev;
732
struct device_node *np = dev->of_node;
735
unsigned long pram_ofs;
736
unsigned long bds_ofs;
738
if (!(mspi->flags & SPI_CPM_MODE))
741
if (!fsl_spi_alloc_dummy_rx())
744
if (mspi->flags & SPI_QE) {
745
iprop = of_get_property(np, "cell-index", &size);
746
if (iprop && size == sizeof(*iprop))
747
mspi->subblock = *iprop;
749
switch (mspi->subblock) {
751
dev_warn(dev, "cell-index unspecified, assuming SPI1");
754
mspi->subblock = QE_CR_SUBBLOCK_SPI1;
757
mspi->subblock = QE_CR_SUBBLOCK_SPI2;
762
pram_ofs = fsl_spi_cpm_get_pram(mspi);
763
if (IS_ERR_VALUE(pram_ofs)) {
764
dev_err(dev, "can't allocate spi parameter ram\n");
768
bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
769
sizeof(*mspi->rx_bd), 8);
770
if (IS_ERR_VALUE(bds_ofs)) {
771
dev_err(dev, "can't allocate bds\n");
775
mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
777
if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
778
dev_err(dev, "unable to map dummy tx buffer\n");
782
mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
784
if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
785
dev_err(dev, "unable to map dummy rx buffer\n");
789
mspi->pram = cpm_muram_addr(pram_ofs);
791
mspi->tx_bd = cpm_muram_addr(bds_ofs);
792
mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
794
/* Initialize parameter ram. */
795
out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
796
out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
797
out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
798
out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
799
out_be16(&mspi->pram->mrblr, SPI_MRBLR);
800
out_be32(&mspi->pram->rstate, 0);
801
out_be32(&mspi->pram->rdp, 0);
802
out_be16(&mspi->pram->rbptr, 0);
803
out_be16(&mspi->pram->rbc, 0);
804
out_be32(&mspi->pram->rxtmp, 0);
805
out_be32(&mspi->pram->tstate, 0);
806
out_be32(&mspi->pram->tdp, 0);
807
out_be16(&mspi->pram->tbptr, 0);
808
out_be16(&mspi->pram->tbc, 0);
809
out_be32(&mspi->pram->txtmp, 0);
814
dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
816
cpm_muram_free(bds_ofs);
818
cpm_muram_free(pram_ofs);
820
fsl_spi_free_dummy_rx();
824
static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
826
struct device *dev = mspi->dev;
828
if (!(mspi->flags & SPI_CPM_MODE))
831
dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
832
dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
833
cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
834
cpm_muram_free(cpm_muram_offset(mspi->pram));
835
fsl_spi_free_dummy_rx();
838
static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
840
iounmap(mspi->reg_base);
841
fsl_spi_cpm_free(mspi);
844
static struct spi_master * __devinit fsl_spi_probe(struct device *dev,
845
struct resource *mem, unsigned int irq)
847
struct fsl_spi_platform_data *pdata = dev->platform_data;
848
struct spi_master *master;
849
struct mpc8xxx_spi *mpc8xxx_spi;
850
struct fsl_spi_reg *reg_base;
854
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
855
if (master == NULL) {
860
dev_set_drvdata(dev, master);
862
ret = mpc8xxx_spi_probe(dev, mem, irq);
866
master->setup = fsl_spi_setup;
868
mpc8xxx_spi = spi_master_get_devdata(master);
869
mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
870
mpc8xxx_spi->spi_remove = fsl_spi_remove;
873
ret = fsl_spi_cpm_init(mpc8xxx_spi);
877
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
878
mpc8xxx_spi->rx_shift = 16;
879
mpc8xxx_spi->tx_shift = 24;
882
mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
883
if (mpc8xxx_spi->reg_base == NULL) {
888
/* Register for SPI Interrupt */
889
ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
890
0, "fsl_spi", mpc8xxx_spi);
895
reg_base = mpc8xxx_spi->reg_base;
897
/* SPI controller initializations */
898
mpc8xxx_spi_write_reg(®_base->mode, 0);
899
mpc8xxx_spi_write_reg(®_base->mask, 0);
900
mpc8xxx_spi_write_reg(®_base->command, 0);
901
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
903
/* Enable SPI interface */
904
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
905
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
908
mpc8xxx_spi_write_reg(®_base->mode, regval);
910
ret = spi_register_master(master);
914
dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
915
mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
920
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
922
iounmap(mpc8xxx_spi->reg_base);
924
fsl_spi_cpm_free(mpc8xxx_spi);
927
spi_master_put(master);
932
static void fsl_spi_cs_control(struct spi_device *spi, bool on)
934
struct device *dev = spi->dev.parent;
935
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
936
u16 cs = spi->chip_select;
937
int gpio = pinfo->gpios[cs];
938
bool alow = pinfo->alow_flags[cs];
940
gpio_set_value(gpio, on ^ alow);
943
static int of_fsl_spi_get_chipselects(struct device *dev)
945
struct device_node *np = dev->of_node;
946
struct fsl_spi_platform_data *pdata = dev->platform_data;
947
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
952
ngpios = of_gpio_count(np);
955
* SPI w/o chip-select line. One SPI device is still permitted
958
pdata->max_chipselect = 1;
962
pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
965
memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
967
pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
969
if (!pinfo->alow_flags) {
971
goto err_alloc_flags;
974
for (; i < ngpios; i++) {
976
enum of_gpio_flags flags;
978
gpio = of_get_gpio_flags(np, i, &flags);
979
if (!gpio_is_valid(gpio)) {
980
dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
985
ret = gpio_request(gpio, dev_name(dev));
987
dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
991
pinfo->gpios[i] = gpio;
992
pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
994
ret = gpio_direction_output(pinfo->gpios[i],
995
pinfo->alow_flags[i]);
997
dev_err(dev, "can't set output direction for gpio "
998
"#%d: %d\n", i, ret);
1003
pdata->max_chipselect = ngpios;
1004
pdata->cs_control = fsl_spi_cs_control;
1010
if (gpio_is_valid(pinfo->gpios[i]))
1011
gpio_free(pinfo->gpios[i]);
1015
kfree(pinfo->alow_flags);
1016
pinfo->alow_flags = NULL;
1018
kfree(pinfo->gpios);
1019
pinfo->gpios = NULL;
1023
static int of_fsl_spi_free_chipselects(struct device *dev)
1025
struct fsl_spi_platform_data *pdata = dev->platform_data;
1026
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1032
for (i = 0; i < pdata->max_chipselect; i++) {
1033
if (gpio_is_valid(pinfo->gpios[i]))
1034
gpio_free(pinfo->gpios[i]);
1037
kfree(pinfo->gpios);
1038
kfree(pinfo->alow_flags);
1042
static int __devinit of_fsl_spi_probe(struct platform_device *ofdev)
1044
struct device *dev = &ofdev->dev;
1045
struct device_node *np = ofdev->dev.of_node;
1046
struct spi_master *master;
1047
struct resource mem;
1048
struct resource irq;
1051
ret = of_mpc8xxx_spi_probe(ofdev);
1055
ret = of_fsl_spi_get_chipselects(dev);
1059
ret = of_address_to_resource(np, 0, &mem);
1063
ret = of_irq_to_resource(np, 0, &irq);
1069
master = fsl_spi_probe(dev, &mem, irq.start);
1070
if (IS_ERR(master)) {
1071
ret = PTR_ERR(master);
1078
of_fsl_spi_free_chipselects(dev);
1082
static int __devexit of_fsl_spi_remove(struct platform_device *ofdev)
1086
ret = mpc8xxx_spi_remove(&ofdev->dev);
1089
of_fsl_spi_free_chipselects(&ofdev->dev);
1093
static const struct of_device_id of_fsl_spi_match[] = {
1094
{ .compatible = "fsl,spi" },
1097
MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
1099
static struct platform_driver of_fsl_spi_driver = {
1102
.owner = THIS_MODULE,
1103
.of_match_table = of_fsl_spi_match,
1105
.probe = of_fsl_spi_probe,
1106
.remove = __devexit_p(of_fsl_spi_remove),
1109
#ifdef CONFIG_MPC832x_RDB
1112
* This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1113
* only. The driver should go away soon, since newer MPC8323E-RDB's device
1114
* tree can work with OpenFirmware driver. But for now we support old trees
1117
static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1119
struct resource *mem;
1121
struct spi_master *master;
1123
if (!pdev->dev.platform_data)
1126
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130
irq = platform_get_irq(pdev, 0);
1134
master = fsl_spi_probe(&pdev->dev, mem, irq);
1136
return PTR_ERR(master);
1140
static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1142
return mpc8xxx_spi_remove(&pdev->dev);
1145
MODULE_ALIAS("platform:mpc8xxx_spi");
1146
static struct platform_driver mpc8xxx_spi_driver = {
1147
.probe = plat_mpc8xxx_spi_probe,
1148
.remove = __devexit_p(plat_mpc8xxx_spi_remove),
1150
.name = "mpc8xxx_spi",
1151
.owner = THIS_MODULE,
1155
static bool legacy_driver_failed;
1157
static void __init legacy_driver_register(void)
1159
legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1162
static void __exit legacy_driver_unregister(void)
1164
if (legacy_driver_failed)
1166
platform_driver_unregister(&mpc8xxx_spi_driver);
1169
static void __init legacy_driver_register(void) {}
1170
static void __exit legacy_driver_unregister(void) {}
1171
#endif /* CONFIG_MPC832x_RDB */
1173
static int __init fsl_spi_init(void)
1175
legacy_driver_register();
1176
return platform_driver_register(&of_fsl_spi_driver);
1178
module_init(fsl_spi_init);
1180
static void __exit fsl_spi_exit(void)
1182
platform_driver_unregister(&of_fsl_spi_driver);
1183
legacy_driver_unregister();
1185
module_exit(fsl_spi_exit);
1187
MODULE_AUTHOR("Kumar Gala");
1188
MODULE_DESCRIPTION("Simple Freescale SPI Driver");
1189
MODULE_LICENSE("GPL");