2
* Copyright (C) 2007 Ben Skeggs.
5
* Permission is hereby granted, free of charge, to any person obtaining
6
* a copy of this software and associated documentation files (the
7
* "Software"), to deal in the Software without restriction, including
8
* without limitation the rights to use, copy, modify, merge, publish,
9
* distribute, sublicense, and/or sell copies of the Software, and to
10
* permit persons to whom the Software is furnished to do so, subject to
11
* the following conditions:
13
* The above copyright notice and this permission notice (including the
14
* next paragraph) shall be included in all copies or substantial
15
* portions of the Software.
17
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
#include "nouveau_drv.h"
30
#include "nouveau_ramht.h"
31
#include "nouveau_grctx.h"
32
#include "nouveau_dma.h"
33
#include "nouveau_vm.h"
36
struct nv50_graph_engine {
37
struct nouveau_exec_engine base;
44
nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
46
const uint32_t mask = 0x00010001;
49
nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
51
nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
54
static struct nouveau_channel *
55
nv50_graph_channel(struct drm_device *dev)
57
struct drm_nouveau_private *dev_priv = dev->dev_private;
61
/* Be sure we're not in the middle of a context switch or bad things
62
* will happen, such as unloading the wrong pgraph context.
64
if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
65
NV_ERROR(dev, "Ctxprog is still running\n");
67
inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
68
if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
70
inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
72
for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
73
struct nouveau_channel *chan = dev_priv->channels.ptr[i];
75
if (chan && chan->ramin && chan->ramin->vinst == inst)
83
nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
85
uint32_t fifo = nv_rd32(dev, 0x400500);
87
nv_wr32(dev, 0x400500, fifo & ~1);
88
nv_wr32(dev, 0x400784, inst);
89
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
90
nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
91
nv_wr32(dev, 0x400040, 0xffffffff);
92
(void)nv_rd32(dev, 0x400040);
93
nv_wr32(dev, 0x400040, 0x00000000);
94
nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
96
if (nouveau_wait_for_idle(dev))
97
nv_wr32(dev, 0x40032c, inst | (1<<31));
98
nv_wr32(dev, 0x400500, fifo);
104
nv50_graph_unload_context(struct drm_device *dev)
108
inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
109
if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
111
inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
113
nouveau_wait_for_idle(dev);
114
nv_wr32(dev, 0x400784, inst);
115
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
116
nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
117
nouveau_wait_for_idle(dev);
119
nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
124
nv50_graph_init(struct drm_device *dev, int engine)
126
struct drm_nouveau_private *dev_priv = dev->dev_private;
127
struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
128
u32 units = nv_rd32(dev, 0x001540);
134
nv_mask(dev, 0x000200, 0x00201000, 0x00000000);
135
nv_mask(dev, 0x000200, 0x00201000, 0x00201000);
136
nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
138
/* reset/enable traps and interrupts */
139
nv_wr32(dev, 0x400804, 0xc0000000);
140
nv_wr32(dev, 0x406800, 0xc0000000);
141
nv_wr32(dev, 0x400c04, 0xc0000000);
142
nv_wr32(dev, 0x401800, 0xc0000000);
143
nv_wr32(dev, 0x405018, 0xc0000000);
144
nv_wr32(dev, 0x402000, 0xc0000000);
145
for (i = 0; i < 16; i++) {
146
if (!(units & (1 << i)))
149
if (dev_priv->chipset < 0xa0) {
150
nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
151
nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
152
nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
154
nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
155
nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
156
nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
160
nv_wr32(dev, 0x400108, 0xffffffff);
161
nv_wr32(dev, 0x400138, 0xffffffff);
162
nv_wr32(dev, 0x400100, 0xffffffff);
163
nv_wr32(dev, 0x40013c, 0xffffffff);
164
nv_wr32(dev, 0x400500, 0x00010001);
166
/* upload context program, initialise ctxctl defaults */
167
nv_wr32(dev, 0x400324, 0x00000000);
168
for (i = 0; i < pgraph->ctxprog_size; i++)
169
nv_wr32(dev, 0x400328, pgraph->ctxprog[i]);
170
nv_wr32(dev, 0x400824, 0x00000000);
171
nv_wr32(dev, 0x400828, 0x00000000);
172
nv_wr32(dev, 0x40082c, 0x00000000);
173
nv_wr32(dev, 0x400830, 0x00000000);
174
nv_wr32(dev, 0x400724, 0x00000000);
175
nv_wr32(dev, 0x40032c, 0x00000000);
176
nv_wr32(dev, 0x400320, 4); /* CTXCTL_CMD = NEWCTXDMA */
178
/* some unknown zcull magic */
179
switch (dev_priv->chipset & 0xf0) {
183
nv_wr32(dev, 0x402ca8, 0x00000800);
187
nv_wr32(dev, 0x402cc0, 0x00000000);
188
if (dev_priv->chipset == 0xa0 ||
189
dev_priv->chipset == 0xaa ||
190
dev_priv->chipset == 0xac) {
191
nv_wr32(dev, 0x402ca8, 0x00000802);
193
nv_wr32(dev, 0x402cc0, 0x00000000);
194
nv_wr32(dev, 0x402ca8, 0x00000002);
200
/* zero out zcull regions */
201
for (i = 0; i < 8; i++) {
202
nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
203
nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
204
nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
205
nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
212
nv50_graph_fini(struct drm_device *dev, int engine, bool suspend)
214
nv_mask(dev, 0x400500, 0x00010001, 0x00000000);
215
if (!nv_wait(dev, 0x400700, ~0, 0) && suspend) {
216
nv_mask(dev, 0x400500, 0x00010001, 0x00010001);
219
nv50_graph_unload_context(dev);
220
nv_wr32(dev, 0x40013c, 0x00000000);
225
nv50_graph_context_new(struct nouveau_channel *chan, int engine)
227
struct drm_device *dev = chan->dev;
228
struct drm_nouveau_private *dev_priv = dev->dev_private;
229
struct nouveau_gpuobj *ramin = chan->ramin;
230
struct nouveau_gpuobj *grctx = NULL;
231
struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
232
struct nouveau_grctx ctx = {};
235
NV_DEBUG(dev, "ch%d\n", chan->id);
237
ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
238
NVOBJ_FLAG_ZERO_ALLOC |
239
NVOBJ_FLAG_ZERO_FREE, &grctx);
243
hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
244
nv_wo32(ramin, hdr + 0x00, 0x00190002);
245
nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
246
nv_wo32(ramin, hdr + 0x08, grctx->vinst);
247
nv_wo32(ramin, hdr + 0x0c, 0);
248
nv_wo32(ramin, hdr + 0x10, 0);
249
nv_wo32(ramin, hdr + 0x14, 0x00010000);
252
ctx.mode = NOUVEAU_GRCTX_VALS;
254
nv50_grctx_init(&ctx);
256
nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
258
dev_priv->engine.instmem.flush(dev);
260
atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
261
chan->engctx[NVOBJ_ENGINE_GR] = grctx;
266
nv50_graph_context_del(struct nouveau_channel *chan, int engine)
268
struct nouveau_gpuobj *grctx = chan->engctx[engine];
269
struct drm_device *dev = chan->dev;
270
struct drm_nouveau_private *dev_priv = dev->dev_private;
271
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
272
int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
275
NV_DEBUG(dev, "ch%d\n", chan->id);
280
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
281
pfifo->reassign(dev, false);
282
nv50_graph_fifo_access(dev, false);
284
if (nv50_graph_channel(dev) == chan)
285
nv50_graph_unload_context(dev);
287
for (i = hdr; i < hdr + 24; i += 4)
288
nv_wo32(chan->ramin, i, 0);
289
dev_priv->engine.instmem.flush(dev);
291
nv50_graph_fifo_access(dev, true);
292
pfifo->reassign(dev, true);
293
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
295
nouveau_gpuobj_ref(NULL, &grctx);
297
atomic_dec(&chan->vm->engref[engine]);
298
chan->engctx[engine] = NULL;
302
nv50_graph_object_new(struct nouveau_channel *chan, int engine,
303
u32 handle, u16 class)
305
struct drm_device *dev = chan->dev;
306
struct drm_nouveau_private *dev_priv = dev->dev_private;
307
struct nouveau_gpuobj *obj = NULL;
310
ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
316
nv_wo32(obj, 0x00, class);
317
nv_wo32(obj, 0x04, 0x00000000);
318
nv_wo32(obj, 0x08, 0x00000000);
319
nv_wo32(obj, 0x0c, 0x00000000);
320
dev_priv->engine.instmem.flush(dev);
322
ret = nouveau_ramht_insert(chan, handle, obj);
323
nouveau_gpuobj_ref(NULL, &obj);
328
nv50_graph_context_switch(struct drm_device *dev)
332
nv50_graph_unload_context(dev);
334
inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
335
inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
336
nv50_graph_do_load_context(dev, inst);
338
nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
339
NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
343
nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
344
u32 class, u32 mthd, u32 data)
346
struct nouveau_gpuobj *gpuobj;
348
gpuobj = nouveau_ramht_find(chan, data);
352
if (nouveau_notifier_offset(gpuobj, NULL))
355
chan->nvsw.vblsem = gpuobj;
356
chan->nvsw.vblsem_offset = ~0;
361
nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
362
u32 class, u32 mthd, u32 data)
364
if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
367
chan->nvsw.vblsem_offset = data >> 2;
372
nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
373
u32 class, u32 mthd, u32 data)
375
chan->nvsw.vblsem_rval = data;
380
nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
381
u32 class, u32 mthd, u32 data)
383
struct drm_device *dev = chan->dev;
384
struct drm_nouveau_private *dev_priv = dev->dev_private;
386
if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
389
drm_vblank_get(dev, data);
391
chan->nvsw.vblsem_head = data;
392
list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
398
nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
399
u32 class, u32 mthd, u32 data)
401
nouveau_finish_page_flip(chan, NULL);
407
nv50_graph_tlb_flush(struct drm_device *dev, int engine)
409
nv50_vm_flush_engine(dev, 0);
413
nv84_graph_tlb_flush(struct drm_device *dev, int engine)
415
struct drm_nouveau_private *dev_priv = dev->dev_private;
416
struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
417
bool idle, timeout = false;
422
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
423
nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
425
start = ptimer->read(dev);
429
for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
434
for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
439
for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
443
} while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
446
NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
447
"0x%08x 0x%08x 0x%08x 0x%08x\n",
448
nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
449
nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
452
nv50_vm_flush_engine(dev, 0);
454
nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
455
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
458
static struct nouveau_enum nv50_mp_exec_error_names[] = {
459
{ 3, "STACK_UNDERFLOW", NULL },
460
{ 4, "QUADON_ACTIVE", NULL },
461
{ 8, "TIMEOUT", NULL },
462
{ 0x10, "INVALID_OPCODE", NULL },
463
{ 0x40, "BREAKPOINT", NULL },
467
static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
468
{ 0x00000001, "NOTIFY" },
469
{ 0x00000002, "IN" },
470
{ 0x00000004, "OUT" },
474
static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
475
{ 0x00000001, "FAULT" },
479
static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
480
{ 0x00000001, "FAULT" },
484
static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
485
{ 0x00000001, "FAULT" },
489
/* There must be a *lot* of these. Will take some time to gather them up. */
490
struct nouveau_enum nv50_data_error_names[] = {
491
{ 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
492
{ 0x00000004, "INVALID_VALUE", NULL },
493
{ 0x00000005, "INVALID_ENUM", NULL },
494
{ 0x00000008, "INVALID_OBJECT", NULL },
495
{ 0x00000009, "READ_ONLY_OBJECT", NULL },
496
{ 0x0000000a, "SUPERVISOR_OBJECT", NULL },
497
{ 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
498
{ 0x0000000c, "INVALID_BITFIELD", NULL },
499
{ 0x0000000d, "BEGIN_END_ACTIVE", NULL },
500
{ 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
501
{ 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
502
{ 0x00000010, "RT_DOUBLE_BIND", NULL },
503
{ 0x00000011, "RT_TYPES_MISMATCH", NULL },
504
{ 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
505
{ 0x00000015, "FP_TOO_FEW_REGS", NULL },
506
{ 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
507
{ 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
508
{ 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
509
{ 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
510
{ 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
511
{ 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
512
{ 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
513
{ 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
514
{ 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
515
{ 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
516
{ 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
517
{ 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
518
{ 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
519
{ 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
520
{ 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
521
{ 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
522
{ 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
523
{ 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
524
{ 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
525
{ 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
526
{ 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
527
{ 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
528
{ 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
529
{ 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
530
{ 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
531
{ 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
535
static struct nouveau_bitfield nv50_graph_intr[] = {
536
{ 0x00000001, "NOTIFY" },
537
{ 0x00000002, "COMPUTE_QUERY" },
538
{ 0x00000010, "ILLEGAL_MTHD" },
539
{ 0x00000020, "ILLEGAL_CLASS" },
540
{ 0x00000040, "DOUBLE_NOTIFY" },
541
{ 0x00001000, "CONTEXT_SWITCH" },
542
{ 0x00010000, "BUFFER_NOTIFY" },
543
{ 0x00100000, "DATA_ERROR" },
544
{ 0x00200000, "TRAP" },
545
{ 0x01000000, "SINGLE_STEP" },
550
nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
552
struct drm_nouveau_private *dev_priv = dev->dev_private;
553
uint32_t units = nv_rd32(dev, 0x1540);
554
uint32_t addr, mp10, status, pc, oplow, ophigh;
557
for (i = 0; i < 4; i++) {
558
if (!(units & 1 << (i+24)))
560
if (dev_priv->chipset < 0xa0)
561
addr = 0x408200 + (tpid << 12) + (i << 7);
563
addr = 0x408100 + (tpid << 11) + (i << 7);
564
mp10 = nv_rd32(dev, addr + 0x10);
565
status = nv_rd32(dev, addr + 0x14);
569
nv_rd32(dev, addr + 0x20);
570
pc = nv_rd32(dev, addr + 0x24);
571
oplow = nv_rd32(dev, addr + 0x70);
572
ophigh = nv_rd32(dev, addr + 0x74);
573
NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
574
"TP %d MP %d: ", tpid, i);
575
nouveau_enum_print(nv50_mp_exec_error_names, status);
576
printk(" at %06x warp %d, opcode %08x %08x\n",
577
pc&0xffffff, pc >> 24,
580
nv_wr32(dev, addr + 0x10, mp10);
581
nv_wr32(dev, addr + 0x14, 0);
585
NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
586
"No MPs claiming errors?\n", tpid);
590
nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
591
uint32_t ustatus_new, int display, const char *name)
593
struct drm_nouveau_private *dev_priv = dev->dev_private;
595
uint32_t units = nv_rd32(dev, 0x1540);
597
uint32_t ustatus_addr, ustatus;
598
for (i = 0; i < 16; i++) {
599
if (!(units & (1 << i)))
601
if (dev_priv->chipset < 0xa0)
602
ustatus_addr = ustatus_old + (i << 12);
604
ustatus_addr = ustatus_new + (i << 11);
605
ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
610
case 6: /* texture error... unknown for now */
612
NV_ERROR(dev, "magic set %d:\n", i);
613
for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
614
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
618
case 7: /* MP error */
619
if (ustatus & 0x00010000) {
620
nv50_pgraph_mp_trap(dev, i, display);
621
ustatus &= ~0x00010000;
624
case 8: /* TPDMA error */
626
uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
627
uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
628
uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
629
uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
630
uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
631
uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
632
uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
633
/* 2d engine destination */
634
if (ustatus & 0x00000010) {
636
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
638
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
639
i, e0c, e18, e1c, e20, e24);
641
ustatus &= ~0x00000010;
644
if (ustatus & 0x00000040) {
646
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
648
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
649
i, e0c, e18, e1c, e20, e24);
651
ustatus &= ~0x00000040;
653
/* CUDA memory: l[], g[] or stack. */
654
if (ustatus & 0x00000080) {
656
if (e18 & 0x80000000) {
657
/* g[] read fault? */
658
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
659
i, e14, e10 | ((e18 >> 24) & 0x1f));
661
} else if (e18 & 0xc) {
662
/* g[] write fault? */
663
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
664
i, e14, e10 | ((e18 >> 7) & 0x1f));
667
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
670
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
671
i, e0c, e18, e1c, e20, e24);
673
ustatus &= ~0x00000080;
680
NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
682
nv_wr32(dev, ustatus_addr, 0xc0000000);
686
NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
690
nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
692
u32 status = nv_rd32(dev, 0x400108);
695
if (!status && display) {
696
NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
700
/* DISPATCH: Relays commands to other units and handles NOTIFY,
701
* COND, QUERY. If you get a trap from it, the command is still stuck
702
* in DISPATCH and you need to do something about it. */
703
if (status & 0x001) {
704
ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
705
if (!ustatus && display) {
706
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
709
nv_wr32(dev, 0x400500, 0x00000000);
711
/* Known to be triggered by screwed up NOTIFY and COND... */
712
if (ustatus & 0x00000001) {
713
u32 addr = nv_rd32(dev, 0x400808);
714
u32 subc = (addr & 0x00070000) >> 16;
715
u32 mthd = (addr & 0x00001ffc);
716
u32 datal = nv_rd32(dev, 0x40080c);
717
u32 datah = nv_rd32(dev, 0x400810);
718
u32 class = nv_rd32(dev, 0x400814);
719
u32 r848 = nv_rd32(dev, 0x400848);
721
NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
722
if (display && (addr & 0x80000000)) {
723
NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
724
"subc %d class 0x%04x mthd 0x%04x "
726
"400808 0x%08x 400848 0x%08x\n",
727
chid, inst, subc, class, mthd, datah,
731
NV_INFO(dev, "PGRAPH - no stuck command?\n");
734
nv_wr32(dev, 0x400808, 0);
735
nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
736
nv_wr32(dev, 0x400848, 0);
737
ustatus &= ~0x00000001;
740
if (ustatus & 0x00000002) {
741
u32 addr = nv_rd32(dev, 0x40084c);
742
u32 subc = (addr & 0x00070000) >> 16;
743
u32 mthd = (addr & 0x00001ffc);
744
u32 data = nv_rd32(dev, 0x40085c);
745
u32 class = nv_rd32(dev, 0x400814);
747
NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
748
if (display && (addr & 0x80000000)) {
749
NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
750
"subc %d class 0x%04x mthd 0x%04x "
751
"data 0x%08x 40084c 0x%08x\n",
752
chid, inst, subc, class, mthd,
756
NV_INFO(dev, "PGRAPH - no stuck command?\n");
759
nv_wr32(dev, 0x40084c, 0);
760
ustatus &= ~0x00000002;
763
if (ustatus && display) {
764
NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
765
"0x%08x)\n", ustatus);
768
nv_wr32(dev, 0x400804, 0xc0000000);
769
nv_wr32(dev, 0x400108, 0x001);
775
/* M2MF: Memory to memory copy engine. */
776
if (status & 0x002) {
777
u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
779
NV_INFO(dev, "PGRAPH - TRAP_M2MF");
780
nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
782
NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
783
nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
784
nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
788
/* No sane way found yet -- just reset the bugger. */
789
nv_wr32(dev, 0x400040, 2);
790
nv_wr32(dev, 0x400040, 0);
791
nv_wr32(dev, 0x406800, 0xc0000000);
792
nv_wr32(dev, 0x400108, 0x002);
796
/* VFETCH: Fetches data from vertex buffers. */
797
if (status & 0x004) {
798
u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
800
NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
801
nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
803
NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
804
nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
805
nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
808
nv_wr32(dev, 0x400c04, 0xc0000000);
809
nv_wr32(dev, 0x400108, 0x004);
813
/* STRMOUT: DirectX streamout / OpenGL transform feedback. */
814
if (status & 0x008) {
815
ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
817
NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
818
nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
820
NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
821
nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
822
nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
826
/* No sane way found yet -- just reset the bugger. */
827
nv_wr32(dev, 0x400040, 0x80);
828
nv_wr32(dev, 0x400040, 0);
829
nv_wr32(dev, 0x401800, 0xc0000000);
830
nv_wr32(dev, 0x400108, 0x008);
834
/* CCACHE: Handles code and c[] caches and fills them. */
835
if (status & 0x010) {
836
ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
838
NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
839
nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
841
NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
843
nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
844
nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
845
nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
846
nv_rd32(dev, 0x40501c));
850
nv_wr32(dev, 0x405018, 0xc0000000);
851
nv_wr32(dev, 0x400108, 0x010);
855
/* Unknown, not seen yet... 0x402000 is the only trap status reg
856
* remaining, so try to handle it anyway. Perhaps related to that
857
* unknown DMA slot on tesla? */
859
ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
861
NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
862
nv_wr32(dev, 0x402000, 0xc0000000);
863
/* no status modifiction on purpose */
866
/* TEXTURE: CUDA texturing units */
867
if (status & 0x040) {
868
nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
869
"PGRAPH - TRAP_TEXTURE");
870
nv_wr32(dev, 0x400108, 0x040);
874
/* MP: CUDA execution engines. */
875
if (status & 0x080) {
876
nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
878
nv_wr32(dev, 0x400108, 0x080);
882
/* TPDMA: Handles TP-initiated uncached memory accesses:
883
* l[], g[], stack, 2d surfaces, render targets. */
884
if (status & 0x100) {
885
nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
886
"PGRAPH - TRAP_TPDMA");
887
nv_wr32(dev, 0x400108, 0x100);
893
NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
894
nv_wr32(dev, 0x400108, status);
901
nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
903
struct drm_nouveau_private *dev_priv = dev->dev_private;
904
struct nouveau_channel *chan;
908
spin_lock_irqsave(&dev_priv->channels.lock, flags);
909
for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
910
chan = dev_priv->channels.ptr[i];
911
if (!chan || !chan->ramin)
914
if (inst == chan->ramin->vinst)
917
spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
922
nv50_graph_isr(struct drm_device *dev)
926
while ((stat = nv_rd32(dev, 0x400100))) {
927
u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
928
u32 chid = nv50_graph_isr_chid(dev, inst);
929
u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
930
u32 subc = (addr & 0x00070000) >> 16;
931
u32 mthd = (addr & 0x00001ffc);
932
u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
933
u32 class = nv_rd32(dev, 0x400814);
936
if (stat & 0x00000010) {
937
if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
942
if (stat & 0x00001000) {
943
nv_wr32(dev, 0x400500, 0x00000000);
944
nv_wr32(dev, 0x400100, 0x00001000);
945
nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
946
nv50_graph_context_switch(dev);
951
show = (show && nouveau_ratelimit()) ? show : 0;
953
if (show & 0x00100000) {
954
u32 ecode = nv_rd32(dev, 0x400110);
955
NV_INFO(dev, "PGRAPH - DATA_ERROR ");
956
nouveau_enum_print(nv50_data_error_names, ecode);
960
if (stat & 0x00200000) {
961
if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
965
nv_wr32(dev, 0x400100, stat);
966
nv_wr32(dev, 0x400500, 0x00010001);
969
NV_INFO(dev, "PGRAPH -");
970
nouveau_bitfield_print(nv50_graph_intr, show);
972
NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
973
"class 0x%04x mthd 0x%04x data 0x%08x\n",
974
chid, inst, subc, class, mthd, data);
975
nv50_fb_vm_trap(dev, 1);
979
if (nv_rd32(dev, 0x400824) & (1 << 31))
980
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
984
nv50_graph_destroy(struct drm_device *dev, int engine)
986
struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
988
NVOBJ_ENGINE_DEL(dev, GR);
990
nouveau_irq_unregister(dev, 12);
995
nv50_graph_create(struct drm_device *dev)
997
struct drm_nouveau_private *dev_priv = dev->dev_private;
998
struct nv50_graph_engine *pgraph;
999
struct nouveau_grctx ctx = {};
1002
pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
1007
ctx.mode = NOUVEAU_GRCTX_PROG;
1008
ctx.data = pgraph->ctxprog;
1009
ctx.ctxprog_max = ARRAY_SIZE(pgraph->ctxprog);
1011
ret = nv50_grctx_init(&ctx);
1013
NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
1018
pgraph->grctx_size = ctx.ctxvals_pos * 4;
1019
pgraph->ctxprog_size = ctx.ctxprog_len;
1021
pgraph->base.destroy = nv50_graph_destroy;
1022
pgraph->base.init = nv50_graph_init;
1023
pgraph->base.fini = nv50_graph_fini;
1024
pgraph->base.context_new = nv50_graph_context_new;
1025
pgraph->base.context_del = nv50_graph_context_del;
1026
pgraph->base.object_new = nv50_graph_object_new;
1027
if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
1028
pgraph->base.tlb_flush = nv50_graph_tlb_flush;
1030
pgraph->base.tlb_flush = nv84_graph_tlb_flush;
1032
nouveau_irq_register(dev, 12, nv50_graph_isr);
1034
/* NVSW really doesn't live here... */
1035
NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
1036
NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
1037
NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
1038
NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
1039
NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
1040
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
1042
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
1043
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
1044
NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
1045
NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
1048
if (dev_priv->chipset == 0x50)
1049
NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
1051
if (dev_priv->chipset < 0xa0)
1052
NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
1054
switch (dev_priv->chipset) {
1058
NVOBJ_CLASS(dev, 0x8397, GR);
1063
NVOBJ_CLASS(dev, 0x8597, GR);
1066
NVOBJ_CLASS(dev, 0x8697, GR);
1072
NVOBJ_CLASS(dev, 0x50c0, GR);
1073
if (dev_priv->chipset > 0xa0 &&
1074
dev_priv->chipset != 0xaa &&
1075
dev_priv->chipset != 0xac)
1076
NVOBJ_CLASS(dev, 0x85c0, GR);