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* Driver for Samsung S5K6AAFX SXGA 1/6" 1.3M CMOS Image Sensor
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* with embedded SoC ISP.
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* Copyright (C) 2011, Samsung Electronics Co., Ltd.
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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* Based on a driver authored by Dongsoo Nathaniel Kim.
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* Copyright (C) 2009, Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/media.h>
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#include <linux/module.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <media/media-entity.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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#include <media/v4l2-mediabus.h>
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#include <media/s5k6aa.h>
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module_param(debug, int, 0644);
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#define DRIVER_NAME "S5K6AA"
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/* The token to indicate array termination */
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#define S5K6AA_TERM 0xffff
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#define S5K6AA_OUT_WIDTH_DEF 640
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#define S5K6AA_OUT_HEIGHT_DEF 480
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#define S5K6AA_WIN_WIDTH_MAX 1280
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#define S5K6AA_WIN_HEIGHT_MAX 1024
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#define S5K6AA_WIN_WIDTH_MIN 8
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#define S5K6AA_WIN_HEIGHT_MIN 8
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* H/W register Interface (0xD0000000 - 0xD0000FFF)
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#define AHB_MSB_ADDR_PTR 0xfcfc
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#define GEN_REG_OFFSH 0xd000
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#define REG_CMDWR_ADDRH 0x0028
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#define REG_CMDWR_ADDRL 0x002a
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#define REG_CMDRD_ADDRH 0x002c
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#define REG_CMDRD_ADDRL 0x002e
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#define REG_CMDBUF0_ADDR 0x0f12
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#define REG_CMDBUF1_ADDR 0x0f10
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* Host S/W Register interface (0x70000000 - 0x70002000)
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* The value of the two most significant address bytes is 0x7000,
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* (HOST_SWIF_OFFS_H). The register addresses below specify 2 LSBs.
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#define HOST_SWIF_OFFSH 0x7000
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/* Initialization parameters */
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/* Master clock frequency in KHz */
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#define REG_I_INCLK_FREQ_L 0x01b8
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#define REG_I_INCLK_FREQ_H 0x01ba
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#define MIN_MCLK_FREQ_KHZ 6000U
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#define MAX_MCLK_FREQ_KHZ 27000U
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#define REG_I_USE_NPVI_CLOCKS 0x01c6
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#define REG_I_USE_NMIPI_CLOCKS 0x01c8
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/* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
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#define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc)
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#define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce)
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#define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0)
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#define SYS_PLL_OUT_FREQ (48000000 / 4000)
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#define PCLK_FREQ_MIN (24000000 / 4000)
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#define PCLK_FREQ_MAX (48000000 / 4000)
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#define REG_I_INIT_PARAMS_UPDATED 0x01e0
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#define REG_I_ERROR_INFO 0x01e2
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/* General purpose parameters */
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#define REG_USER_BRIGHTNESS 0x01e4
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#define REG_USER_CONTRAST 0x01e6
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#define REG_USER_SATURATION 0x01e8
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#define REG_USER_SHARPBLUR 0x01ea
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#define REG_G_SPEC_EFFECTS 0x01ee
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#define REG_G_ENABLE_PREV 0x01f0
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#define REG_G_ENABLE_PREV_CHG 0x01f2
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#define REG_G_NEW_CFG_SYNC 0x01f8
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#define REG_G_PREVZOOM_IN_WIDTH 0x020a
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#define REG_G_PREVZOOM_IN_HEIGHT 0x020c
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#define REG_G_PREVZOOM_IN_XOFFS 0x020e
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#define REG_G_PREVZOOM_IN_YOFFS 0x0210
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#define REG_G_INPUTS_CHANGE_REQ 0x021a
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#define REG_G_ACTIVE_PREV_CFG 0x021c
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#define REG_G_PREV_CFG_CHG 0x021e
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#define REG_G_PREV_OPEN_AFTER_CH 0x0220
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#define REG_G_PREV_CFG_ERROR 0x0222
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/* Preview control section. n = 0...4. */
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#define PREG(n, x) ((n) * 0x26 + x)
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#define REG_P_OUT_WIDTH(n) PREG(n, 0x0242)
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#define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244)
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#define REG_P_FMT(n) PREG(n, 0x0246)
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#define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248)
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#define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a)
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#define REG_P_PVI_MASK(n) PREG(n, 0x024c)
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#define REG_P_CLK_INDEX(n) PREG(n, 0x024e)
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#define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250)
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#define FR_RATE_DYNAMIC 0
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#define FR_RATE_FIXED 1
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#define FR_RATE_FIXED_ACCURATE 2
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#define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252)
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#define FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */
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#define FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */
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/* Frame period in 0.1 ms units */
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#define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254)
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#define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256)
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/* Conversion to REG_P_[MAX/MIN]_FR_TIME value; __t: time in us */
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#define US_TO_FR_TIME(__t) ((__t) / 100)
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#define S5K6AA_MIN_FR_TIME 33300 /* us */
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#define S5K6AA_MAX_FR_TIME 650000 /* us */
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#define S5K6AA_MAX_HIGHRES_FR_TIME 666 /* x100 us */
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/* The below 5 registers are for "device correction" values */
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#define REG_P_COLORTEMP(n) PREG(n, 0x025e)
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#define REG_P_PREV_MIRROR(n) PREG(n, 0x0262)
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/* Extended image property controls */
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/* Exposure time in 10 us units */
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#define REG_SF_USR_EXPOSURE_L 0x03c6
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#define REG_SF_USR_EXPOSURE_H 0x03c8
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#define REG_SF_USR_EXPOSURE_CHG 0x03ca
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#define REG_SF_USR_TOT_GAIN 0x03cc
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#define REG_SF_USR_TOT_GAIN_CHG 0x03ce
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#define REG_SF_RGAIN 0x03d0
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#define REG_SF_RGAIN_CHG 0x03d2
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#define REG_SF_GGAIN 0x03d4
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#define REG_SF_GGAIN_CHG 0x03d6
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#define REG_SF_BGAIN 0x03d8
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#define REG_SF_BGAIN_CHG 0x03da
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#define REG_SF_FLICKER_QUANT 0x03dc
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#define REG_SF_FLICKER_QUANT_CHG 0x03de
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/* Output interface (parallel/MIPI) setup */
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#define REG_OIF_EN_MIPI_LANES 0x03fa
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#define REG_OIF_EN_PACKETS 0x03fc
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#define REG_OIF_CFG_CHG 0x03fe
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/* Auto-algorithms enable mask */
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#define REG_DBG_AUTOALG_EN 0x0400
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#define AALG_ALL_EN_MASK (1 << 0)
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#define AALG_AE_EN_MASK (1 << 1)
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#define AALG_DIVLEI_EN_MASK (1 << 2)
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#define AALG_WB_EN_MASK (1 << 3)
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#define AALG_FLICKER_EN_MASK (1 << 5)
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#define AALG_FIT_EN_MASK (1 << 6)
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#define AALG_WRHW_EN_MASK (1 << 7)
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/* Firmware revision information */
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#define REG_FW_APIVER 0x012e
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#define S5K6AAFX_FW_APIVER 0x0001
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#define REG_FW_REVISION 0x0130
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/* For now we use only one user configuration register set */
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#define S5K6AA_MAX_PRESETS 1
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static const char * const s5k6aa_supply_names[] = {
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"vdd_core", /* Digital core supply 1.5V (1.4V to 1.6V) */
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"vdda", /* Analog power supply 2.8V (2.6V to 3.0V) */
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"vdd_reg", /* Regulator input power 1.8V (1.7V to 1.9V)
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or 2.8V (2.6V to 3.0) */
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"vddio", /* I/O supply 1.8V (1.65V to 1.95V)
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or 2.8V (2.5V to 3.1V) */
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#define S5K6AA_NUM_SUPPLIES ARRAY_SIZE(s5k6aa_supply_names)
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enum s5k6aa_gpio_id {
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struct s5k6aa_regval {
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struct s5k6aa_pixfmt {
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enum v4l2_mbus_pixelcode code;
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/* REG_P_FMT(x) register value */
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struct s5k6aa_preset {
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/* output pixel format and resolution */
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struct v4l2_mbus_framefmt mbus_fmt;
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struct s5k6aa_ctrls {
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struct v4l2_ctrl_handler handler;
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/* Auto / manual white balance cluster */
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struct v4l2_ctrl *awb;
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struct v4l2_ctrl *gain_red;
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struct v4l2_ctrl *gain_blue;
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struct v4l2_ctrl *gain_green;
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struct v4l2_ctrl *hflip;
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struct v4l2_ctrl *vflip;
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/* Auto exposure / manual exposure and gain cluster */
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struct v4l2_ctrl *auto_exp;
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struct v4l2_ctrl *exposure;
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struct v4l2_ctrl *gain;
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struct s5k6aa_interval {
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struct v4l2_fract interval;
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/* Maximum rectangle for the interval */
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struct v4l2_frmsize_discrete size;
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struct v4l2_subdev sd;
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struct media_pad pad;
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enum v4l2_mbus_type bus_type;
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int (*s_power)(int enable);
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struct regulator_bulk_data supplies[S5K6AA_NUM_SUPPLIES];
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struct s5k6aa_gpio gpio[GPIO_NUM];
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/* external master clock frequency */
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unsigned long mclk_frequency;
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/* ISP internal master clock frequency */
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/* output pixel clock frequency range */
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unsigned int inv_hflip:1;
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unsigned int inv_vflip:1;
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/* protects the struct members below */
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/* sensor matrix scan window */
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struct v4l2_rect ccd_rect;
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struct s5k6aa_ctrls ctrls;
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struct s5k6aa_preset presets[S5K6AA_MAX_PRESETS];
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struct s5k6aa_preset *preset;
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const struct s5k6aa_interval *fiv;
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unsigned int streaming:1;
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unsigned int apply_cfg:1;
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unsigned int apply_crop:1;
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static struct s5k6aa_regval s5k6aa_analog_config[] = {
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/* Analog settings */
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{ 0x112a, 0x0000 }, { 0x1132, 0x0000 },
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{ 0x113e, 0x0000 }, { 0x115c, 0x0000 },
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{ 0x1164, 0x0000 }, { 0x1174, 0x0000 },
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{ 0x1178, 0x0000 }, { 0x077a, 0x0000 },
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{ 0x077c, 0x0000 }, { 0x077e, 0x0000 },
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{ 0x0780, 0x0000 }, { 0x0782, 0x0000 },
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{ 0x0784, 0x0000 }, { 0x0786, 0x0000 },
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{ 0x0788, 0x0000 }, { 0x07a2, 0x0000 },
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{ 0x07a4, 0x0000 }, { 0x07a6, 0x0000 },
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{ 0x07a8, 0x0000 }, { 0x07b6, 0x0000 },
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{ 0x07b8, 0x0002 }, { 0x07ba, 0x0004 },
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{ 0x07bc, 0x0004 }, { 0x07be, 0x0005 },
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{ 0x07c0, 0x0005 }, { S5K6AA_TERM, 0 },
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/* TODO: Add RGB888 and Bayer format */
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static const struct s5k6aa_pixfmt s5k6aa_formats[] = {
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{ V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 5 },
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{ V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_REC709, 6 },
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{ V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_JPEG, 0 },
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static const struct s5k6aa_interval s5k6aa_intervals[] = {
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{ 1000, {10000, 1000000}, {1280, 1024} }, /* 10 fps */
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{ 666, {15000, 1000000}, {1280, 1024} }, /* 15 fps */
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{ 500, {20000, 1000000}, {1280, 720} }, /* 20 fps */
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{ 400, {25000, 1000000}, {640, 480} }, /* 25 fps */
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{ 333, {33300, 1000000}, {640, 480} }, /* 30 fps */
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#define S5K6AA_INTERVAL_DEF_INDEX 1 /* 15 fps */
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static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
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return &container_of(ctrl->handler, struct s5k6aa, ctrls.handler)->sd;
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static inline struct s5k6aa *to_s5k6aa(struct v4l2_subdev *sd)
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return container_of(sd, struct s5k6aa, sd);
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/* Set initial values for all preview presets */
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static void s5k6aa_presets_data_init(struct s5k6aa *s5k6aa)
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struct s5k6aa_preset *preset = &s5k6aa->presets[0];
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for (i = 0; i < S5K6AA_MAX_PRESETS; i++) {
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preset->mbus_fmt.width = S5K6AA_OUT_WIDTH_DEF;
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preset->mbus_fmt.height = S5K6AA_OUT_HEIGHT_DEF;
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preset->mbus_fmt.code = s5k6aa_formats[0].code;
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s5k6aa->fiv = &s5k6aa_intervals[S5K6AA_INTERVAL_DEF_INDEX];
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s5k6aa->preset = &s5k6aa->presets[0];
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static int s5k6aa_i2c_read(struct i2c_client *client, u16 addr, u16 *val)
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u8 wbuf[2] = {addr >> 8, addr & 0xFF};
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struct i2c_msg msg[2];
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msg[0].addr = client->addr;
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msg[1].addr = client->addr;
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msg[1].flags = I2C_M_RD;
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ret = i2c_transfer(client->adapter, msg, 2);
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*val = be16_to_cpu(*((u16 *)rbuf));
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v4l2_dbg(3, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val);
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return ret == 2 ? 0 : ret;
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static int s5k6aa_i2c_write(struct i2c_client *client, u16 addr, u16 val)
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u8 buf[4] = {addr >> 8, addr & 0xFF, val >> 8, val & 0xFF};
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int ret = i2c_master_send(client, buf, 4);
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v4l2_dbg(3, debug, client, "i2c_write: 0x%04X : 0x%04x\n", addr, val);
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return ret == 4 ? 0 : ret;
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/* The command register write, assumes Command_Wr_addH = 0x7000. */
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static int s5k6aa_write(struct i2c_client *c, u16 addr, u16 val)
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int ret = s5k6aa_i2c_write(c, REG_CMDWR_ADDRL, addr);
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return s5k6aa_i2c_write(c, REG_CMDBUF0_ADDR, val);
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/* The command register read, assumes Command_Rd_addH = 0x7000. */
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static int s5k6aa_read(struct i2c_client *client, u16 addr, u16 *val)
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int ret = s5k6aa_i2c_write(client, REG_CMDRD_ADDRL, addr);
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return s5k6aa_i2c_read(client, REG_CMDBUF0_ADDR, val);
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static int s5k6aa_write_array(struct v4l2_subdev *sd,
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const struct s5k6aa_regval *msg)
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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while (msg->addr != S5K6AA_TERM) {
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ret = s5k6aa_i2c_write(client, REG_CMDWR_ADDRL,
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ret = s5k6aa_i2c_write(client, REG_CMDBUF0_ADDR, msg->val);
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/* Assume that msg->addr is always less than 0xfffc */
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addr_incr = (msg + 1)->addr - msg->addr;
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/* Configure the AHB high address bytes for GTG registers access */
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static int s5k6aa_set_ahb_address(struct i2c_client *client)
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int ret = s5k6aa_i2c_write(client, AHB_MSB_ADDR_PTR, GEN_REG_OFFSH);
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ret = s5k6aa_i2c_write(client, REG_CMDRD_ADDRH, HOST_SWIF_OFFSH);
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return s5k6aa_i2c_write(client, REG_CMDWR_ADDRH, HOST_SWIF_OFFSH);
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* s5k6aa_configure_pixel_clock - apply ISP main clock/PLL configuration
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* Configure the internal ISP PLL for the required output frequency.
426
* Locking: called with s5k6aa.lock mutex held.
428
static int s5k6aa_configure_pixel_clocks(struct s5k6aa *s5k6aa)
430
struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
431
unsigned long fmclk = s5k6aa->mclk_frequency / 1000;
435
if (WARN(fmclk < MIN_MCLK_FREQ_KHZ || fmclk > MAX_MCLK_FREQ_KHZ,
436
"Invalid clock frequency: %ld\n", fmclk))
439
s5k6aa->pclk_fmin = PCLK_FREQ_MIN;
440
s5k6aa->pclk_fmax = PCLK_FREQ_MAX;
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s5k6aa->clk_fop = SYS_PLL_OUT_FREQ;
443
/* External input clock frequency in kHz */
444
ret = s5k6aa_write(c, REG_I_INCLK_FREQ_H, fmclk >> 16);
446
ret = s5k6aa_write(c, REG_I_INCLK_FREQ_L, fmclk & 0xFFFF);
448
ret = s5k6aa_write(c, REG_I_USE_NPVI_CLOCKS, 1);
449
/* Internal PLL frequency */
451
ret = s5k6aa_write(c, REG_I_OPCLK_4KHZ(0), s5k6aa->clk_fop);
453
ret = s5k6aa_write(c, REG_I_MIN_OUTRATE_4KHZ(0),
456
ret = s5k6aa_write(c, REG_I_MAX_OUTRATE_4KHZ(0),
459
ret = s5k6aa_write(c, REG_I_INIT_PARAMS_UPDATED, 1);
461
ret = s5k6aa_read(c, REG_I_ERROR_INFO, &status);
463
return ret ? ret : (status ? -EINVAL : 0);
466
/* Set horizontal and vertical image flipping */
467
static int s5k6aa_set_mirror(struct s5k6aa *s5k6aa, int horiz_flip)
469
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
470
int index = s5k6aa->preset->index;
472
unsigned int vflip = s5k6aa->ctrls.vflip->val ^ s5k6aa->inv_vflip;
473
unsigned int flip = (horiz_flip ^ s5k6aa->inv_hflip) | (vflip << 1);
475
return s5k6aa_write(client, REG_P_PREV_MIRROR(index), flip);
478
/* Configure auto/manual white balance and R/G/B gains */
479
static int s5k6aa_set_awb(struct s5k6aa *s5k6aa, int awb)
481
struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
482
struct s5k6aa_ctrls *ctrls = &s5k6aa->ctrls;
485
int ret = s5k6aa_read(c, REG_DBG_AUTOALG_EN, ®);
488
ret = s5k6aa_write(c, REG_SF_RGAIN, ctrls->gain_red->val);
490
ret = s5k6aa_write(c, REG_SF_RGAIN_CHG, 1);
494
ret = s5k6aa_write(c, REG_SF_GGAIN, ctrls->gain_green->val);
496
ret = s5k6aa_write(c, REG_SF_GGAIN_CHG, 1);
500
ret = s5k6aa_write(c, REG_SF_BGAIN, ctrls->gain_blue->val);
502
ret = s5k6aa_write(c, REG_SF_BGAIN_CHG, 1);
505
reg = awb ? reg | AALG_WB_EN_MASK : reg & ~AALG_WB_EN_MASK;
506
ret = s5k6aa_write(c, REG_DBG_AUTOALG_EN, reg);
512
/* Program FW with exposure time, 'exposure' in us units */
513
static int s5k6aa_set_user_exposure(struct i2c_client *client, int exposure)
515
unsigned int time = exposure / 10;
517
int ret = s5k6aa_write(client, REG_SF_USR_EXPOSURE_L, time & 0xffff);
519
ret = s5k6aa_write(client, REG_SF_USR_EXPOSURE_H, time >> 16);
522
return s5k6aa_write(client, REG_SF_USR_EXPOSURE_CHG, 1);
525
static int s5k6aa_set_user_gain(struct i2c_client *client, int gain)
527
int ret = s5k6aa_write(client, REG_SF_USR_TOT_GAIN, gain);
530
return s5k6aa_write(client, REG_SF_USR_TOT_GAIN_CHG, 1);
533
/* Set auto/manual exposure and total gain */
534
static int s5k6aa_set_auto_exposure(struct s5k6aa *s5k6aa, int value)
536
struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
537
unsigned int exp_time = s5k6aa->ctrls.exposure->val;
540
int ret = s5k6aa_read(c, REG_DBG_AUTOALG_EN, &auto_alg);
544
v4l2_dbg(1, debug, c, "man_exp: %d, auto_exp: %d, a_alg: 0x%x\n",
545
exp_time, value, auto_alg);
547
if (value == V4L2_EXPOSURE_AUTO) {
548
auto_alg |= AALG_AE_EN_MASK | AALG_DIVLEI_EN_MASK;
550
ret = s5k6aa_set_user_exposure(c, exp_time);
553
ret = s5k6aa_set_user_gain(c, s5k6aa->ctrls.gain->val);
556
auto_alg &= ~(AALG_AE_EN_MASK | AALG_DIVLEI_EN_MASK);
559
return s5k6aa_write(c, REG_DBG_AUTOALG_EN, auto_alg);
562
static int s5k6aa_set_anti_flicker(struct s5k6aa *s5k6aa, int value)
564
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
568
ret = s5k6aa_read(client, REG_DBG_AUTOALG_EN, &auto_alg);
572
if (value == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
573
auto_alg |= AALG_FLICKER_EN_MASK;
575
auto_alg &= ~AALG_FLICKER_EN_MASK;
576
/* The V4L2_CID_LINE_FREQUENCY control values match
577
* the register values */
578
ret = s5k6aa_write(client, REG_SF_FLICKER_QUANT, value);
581
ret = s5k6aa_write(client, REG_SF_FLICKER_QUANT_CHG, 1);
586
return s5k6aa_write(client, REG_DBG_AUTOALG_EN, auto_alg);
589
static int s5k6aa_set_colorfx(struct s5k6aa *s5k6aa, int val)
591
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
592
static const struct v4l2_control colorfx[] = {
593
{ V4L2_COLORFX_NONE, 0 },
594
{ V4L2_COLORFX_BW, 1 },
595
{ V4L2_COLORFX_NEGATIVE, 2 },
596
{ V4L2_COLORFX_SEPIA, 3 },
597
{ V4L2_COLORFX_SKY_BLUE, 4 },
598
{ V4L2_COLORFX_SKETCH, 5 },
602
for (i = 0; i < ARRAY_SIZE(colorfx); i++) {
603
if (colorfx[i].id == val)
604
return s5k6aa_write(client, REG_G_SPEC_EFFECTS,
610
static int s5k6aa_preview_config_status(struct i2c_client *client)
613
int ret = s5k6aa_read(client, REG_G_PREV_CFG_ERROR, &error);
615
v4l2_dbg(1, debug, client, "error: 0x%x (%d)\n", error, ret);
616
return ret ? ret : (error ? -EINVAL : 0);
619
static int s5k6aa_get_pixfmt_index(struct s5k6aa *s5k6aa,
620
struct v4l2_mbus_framefmt *mf)
624
for (i = 0; i < ARRAY_SIZE(s5k6aa_formats); i++)
625
if (mf->colorspace == s5k6aa_formats[i].colorspace &&
626
mf->code == s5k6aa_formats[i].code)
631
static int s5k6aa_set_output_framefmt(struct s5k6aa *s5k6aa,
632
struct s5k6aa_preset *preset)
634
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
635
int fmt_index = s5k6aa_get_pixfmt_index(s5k6aa, &preset->mbus_fmt);
638
ret = s5k6aa_write(client, REG_P_OUT_WIDTH(preset->index),
639
preset->mbus_fmt.width);
641
ret = s5k6aa_write(client, REG_P_OUT_HEIGHT(preset->index),
642
preset->mbus_fmt.height);
644
ret = s5k6aa_write(client, REG_P_FMT(preset->index),
645
s5k6aa_formats[fmt_index].reg_p_fmt);
649
static int s5k6aa_set_input_params(struct s5k6aa *s5k6aa)
651
struct i2c_client *c = v4l2_get_subdevdata(&s5k6aa->sd);
652
struct v4l2_rect *r = &s5k6aa->ccd_rect;
655
ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_WIDTH, r->width);
657
ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_HEIGHT, r->height);
659
ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_XOFFS, r->left);
661
ret = s5k6aa_write(c, REG_G_PREVZOOM_IN_YOFFS, r->top);
663
ret = s5k6aa_write(c, REG_G_INPUTS_CHANGE_REQ, 1);
665
s5k6aa->apply_crop = 0;
671
* s5k6aa_configure_video_bus - configure the video output interface
672
* @bus_type: video bus type: parallel or MIPI-CSI
673
* @nlanes: number of MIPI lanes to be used (MIPI-CSI only)
675
* Note: Only parallel bus operation has been tested.
677
static int s5k6aa_configure_video_bus(struct s5k6aa *s5k6aa,
678
enum v4l2_mbus_type bus_type, int nlanes)
680
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
685
* TODO: The sensor is supposed to support BT.601 and BT.656
686
* but there is nothing indicating how to switch between both
687
* in the datasheet. For now default BT.601 interface is assumed.
689
if (bus_type == V4L2_MBUS_CSI2)
691
else if (bus_type != V4L2_MBUS_PARALLEL)
694
ret = s5k6aa_write(client, REG_OIF_EN_MIPI_LANES, cfg);
697
return s5k6aa_write(client, REG_OIF_CFG_CHG, 1);
700
/* This function should be called when switching to new user configuration set*/
701
static int s5k6aa_new_config_sync(struct i2c_client *client, int timeout,
704
unsigned long end = jiffies + msecs_to_jiffies(timeout);
708
ret = s5k6aa_write(client, REG_G_ACTIVE_PREV_CFG, cid);
710
ret = s5k6aa_write(client, REG_G_PREV_CFG_CHG, 1);
712
ret = s5k6aa_write(client, REG_G_NEW_CFG_SYNC, 1);
716
while (ret >= 0 && time_is_after_jiffies(end)) {
717
ret = s5k6aa_read(client, REG_G_NEW_CFG_SYNC, ®);
720
usleep_range(1000, 5000);
722
return ret ? ret : -ETIMEDOUT;
726
* s5k6aa_set_prev_config - write user preview register set
728
* Configure output resolution and color fromat, pixel clock
729
* frequency range, device frame rate type and frame period range.
731
static int s5k6aa_set_prev_config(struct s5k6aa *s5k6aa,
732
struct s5k6aa_preset *preset)
734
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
735
int idx = preset->index;
739
if (s5k6aa->fiv->reg_fr_time >= S5K6AA_MAX_HIGHRES_FR_TIME)
740
frame_rate_q = FR_RATE_Q_BEST_FRRATE;
742
frame_rate_q = FR_RATE_Q_BEST_QUALITY;
744
ret = s5k6aa_set_output_framefmt(s5k6aa, preset);
746
ret = s5k6aa_write(client, REG_P_MAX_OUT_RATE(idx),
749
ret = s5k6aa_write(client, REG_P_MIN_OUT_RATE(idx),
752
ret = s5k6aa_write(client, REG_P_CLK_INDEX(idx),
755
ret = s5k6aa_write(client, REG_P_FR_RATE_TYPE(idx),
758
ret = s5k6aa_write(client, REG_P_FR_RATE_Q_TYPE(idx),
761
ret = s5k6aa_write(client, REG_P_MAX_FR_TIME(idx),
762
s5k6aa->fiv->reg_fr_time + 33);
764
ret = s5k6aa_write(client, REG_P_MIN_FR_TIME(idx),
765
s5k6aa->fiv->reg_fr_time - 33);
767
ret = s5k6aa_new_config_sync(client, 250, idx);
769
ret = s5k6aa_preview_config_status(client);
771
s5k6aa->apply_cfg = 0;
773
v4l2_dbg(1, debug, client, "Frame interval: %d +/- 3.3ms. (%d)\n",
774
s5k6aa->fiv->reg_fr_time, ret);
779
* s5k6aa_initialize_isp - basic ISP MCU initialization
781
* Configure AHB addresses for registers read/write; configure PLLs for
782
* required output pixel clock. The ISP power supply needs to be already
783
* enabled, with an optional H/W reset.
784
* Locking: called with s5k6aa.lock mutex held.
786
static int s5k6aa_initialize_isp(struct v4l2_subdev *sd)
788
struct i2c_client *client = v4l2_get_subdevdata(sd);
789
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
792
s5k6aa->apply_crop = 1;
793
s5k6aa->apply_cfg = 1;
796
ret = s5k6aa_set_ahb_address(client);
799
ret = s5k6aa_configure_video_bus(s5k6aa, s5k6aa->bus_type,
803
ret = s5k6aa_write_array(sd, s5k6aa_analog_config);
808
return s5k6aa_configure_pixel_clocks(s5k6aa);
811
static int s5k6aa_gpio_set_value(struct s5k6aa *priv, int id, u32 val)
813
if (!gpio_is_valid(priv->gpio[id].gpio))
815
gpio_set_value(priv->gpio[id].gpio, !!val);
819
static int s5k6aa_gpio_assert(struct s5k6aa *priv, int id)
821
return s5k6aa_gpio_set_value(priv, id, priv->gpio[id].level);
824
static int s5k6aa_gpio_deassert(struct s5k6aa *priv, int id)
826
return s5k6aa_gpio_set_value(priv, id, !priv->gpio[id].level);
829
static int __s5k6aa_power_on(struct s5k6aa *s5k6aa)
833
ret = regulator_bulk_enable(S5K6AA_NUM_SUPPLIES, s5k6aa->supplies);
836
if (s5k6aa_gpio_deassert(s5k6aa, STBY))
837
usleep_range(150, 200);
840
ret = s5k6aa->s_power(1);
841
usleep_range(4000, 4000);
843
if (s5k6aa_gpio_deassert(s5k6aa, RST))
849
static int __s5k6aa_power_off(struct s5k6aa *s5k6aa)
853
if (s5k6aa_gpio_assert(s5k6aa, RST))
854
usleep_range(100, 150);
856
if (s5k6aa->s_power) {
857
ret = s5k6aa->s_power(0);
861
if (s5k6aa_gpio_assert(s5k6aa, STBY))
862
usleep_range(50, 100);
863
s5k6aa->streaming = 0;
865
return regulator_bulk_disable(S5K6AA_NUM_SUPPLIES, s5k6aa->supplies);
869
* V4L2 subdev core and video operations
871
static int s5k6aa_set_power(struct v4l2_subdev *sd, int on)
873
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
876
mutex_lock(&s5k6aa->lock);
878
if (!on == s5k6aa->power) {
880
ret = __s5k6aa_power_on(s5k6aa);
882
ret = s5k6aa_initialize_isp(sd);
884
ret = __s5k6aa_power_off(s5k6aa);
888
s5k6aa->power += on ? 1 : -1;
891
mutex_unlock(&s5k6aa->lock);
893
if (!on || ret || s5k6aa->power != 1)
896
return v4l2_ctrl_handler_setup(sd->ctrl_handler);
899
static int __s5k6aa_stream(struct s5k6aa *s5k6aa, int enable)
901
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
904
ret = s5k6aa_write(client, REG_G_ENABLE_PREV, enable);
906
ret = s5k6aa_write(client, REG_G_ENABLE_PREV_CHG, 1);
908
s5k6aa->streaming = enable;
913
static int s5k6aa_s_stream(struct v4l2_subdev *sd, int on)
915
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
918
mutex_lock(&s5k6aa->lock);
920
if (s5k6aa->streaming == !on) {
921
if (!ret && s5k6aa->apply_cfg)
922
ret = s5k6aa_set_prev_config(s5k6aa, s5k6aa->preset);
923
if (s5k6aa->apply_crop)
924
ret = s5k6aa_set_input_params(s5k6aa);
926
ret = __s5k6aa_stream(s5k6aa, !!on);
928
mutex_unlock(&s5k6aa->lock);
933
static int s5k6aa_g_frame_interval(struct v4l2_subdev *sd,
934
struct v4l2_subdev_frame_interval *fi)
936
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
938
mutex_lock(&s5k6aa->lock);
939
fi->interval = s5k6aa->fiv->interval;
940
mutex_unlock(&s5k6aa->lock);
945
static int __s5k6aa_set_frame_interval(struct s5k6aa *s5k6aa,
946
struct v4l2_subdev_frame_interval *fi)
948
struct v4l2_mbus_framefmt *mbus_fmt = &s5k6aa->preset->mbus_fmt;
949
const struct s5k6aa_interval *fiv = &s5k6aa_intervals[0];
950
unsigned int err, min_err = UINT_MAX;
951
unsigned int i, fr_time;
953
if (fi->interval.denominator == 0)
956
fr_time = fi->interval.numerator * 10000 / fi->interval.denominator;
958
for (i = 0; i < ARRAY_SIZE(s5k6aa_intervals); i++) {
959
const struct s5k6aa_interval *iv = &s5k6aa_intervals[i];
961
if (mbus_fmt->width > iv->size.width ||
962
mbus_fmt->height > iv->size.height)
965
err = abs(iv->reg_fr_time - fr_time);
973
v4l2_dbg(1, debug, &s5k6aa->sd, "Changed frame interval to %d us\n",
974
fiv->reg_fr_time * 100);
978
static int s5k6aa_s_frame_interval(struct v4l2_subdev *sd,
979
struct v4l2_subdev_frame_interval *fi)
981
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
984
v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n",
985
fi->interval.numerator, fi->interval.denominator);
987
mutex_lock(&s5k6aa->lock);
988
ret = __s5k6aa_set_frame_interval(s5k6aa, fi);
989
s5k6aa->apply_cfg = 1;
991
mutex_unlock(&s5k6aa->lock);
996
* V4L2 subdev pad level and video operations
998
static int s5k6aa_enum_frame_interval(struct v4l2_subdev *sd,
999
struct v4l2_subdev_fh *fh,
1000
struct v4l2_subdev_frame_interval_enum *fie)
1002
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1003
const struct s5k6aa_interval *fi;
1006
if (fie->index > ARRAY_SIZE(s5k6aa_intervals))
1009
v4l_bound_align_image(&fie->width, S5K6AA_WIN_WIDTH_MIN,
1010
S5K6AA_WIN_WIDTH_MAX, 1,
1011
&fie->height, S5K6AA_WIN_HEIGHT_MIN,
1012
S5K6AA_WIN_HEIGHT_MAX, 1, 0);
1014
mutex_lock(&s5k6aa->lock);
1015
fi = &s5k6aa_intervals[fie->index];
1016
if (fie->width > fi->size.width || fie->height > fi->size.height)
1019
fie->interval = fi->interval;
1020
mutex_unlock(&s5k6aa->lock);
1025
static int s5k6aa_enum_mbus_code(struct v4l2_subdev *sd,
1026
struct v4l2_subdev_fh *fh,
1027
struct v4l2_subdev_mbus_code_enum *code)
1029
if (code->index >= ARRAY_SIZE(s5k6aa_formats))
1032
code->code = s5k6aa_formats[code->index].code;
1036
static int s5k6aa_enum_frame_size(struct v4l2_subdev *sd,
1037
struct v4l2_subdev_fh *fh,
1038
struct v4l2_subdev_frame_size_enum *fse)
1040
int i = ARRAY_SIZE(s5k6aa_formats);
1046
if (fse->code == s5k6aa_formats[i].code)
1049
fse->code = s5k6aa_formats[i].code;
1050
fse->min_width = S5K6AA_WIN_WIDTH_MIN;
1051
fse->max_width = S5K6AA_WIN_WIDTH_MAX;
1052
fse->max_height = S5K6AA_WIN_HEIGHT_MIN;
1053
fse->min_height = S5K6AA_WIN_HEIGHT_MAX;
1058
static struct v4l2_rect *
1059
__s5k6aa_get_crop_rect(struct s5k6aa *s5k6aa, struct v4l2_subdev_fh *fh,
1060
enum v4l2_subdev_format_whence which)
1062
if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
1063
return &s5k6aa->ccd_rect;
1064
if (which == V4L2_SUBDEV_FORMAT_TRY)
1065
return v4l2_subdev_get_try_crop(fh, 0);
1070
static void s5k6aa_try_format(struct s5k6aa *s5k6aa,
1071
struct v4l2_mbus_framefmt *mf)
1075
v4l_bound_align_image(&mf->width, S5K6AA_WIN_WIDTH_MIN,
1076
S5K6AA_WIN_WIDTH_MAX, 1,
1077
&mf->height, S5K6AA_WIN_HEIGHT_MIN,
1078
S5K6AA_WIN_HEIGHT_MAX, 1, 0);
1080
if (mf->colorspace != V4L2_COLORSPACE_JPEG &&
1081
mf->colorspace != V4L2_COLORSPACE_REC709)
1082
mf->colorspace = V4L2_COLORSPACE_JPEG;
1084
index = s5k6aa_get_pixfmt_index(s5k6aa, mf);
1086
mf->colorspace = s5k6aa_formats[index].colorspace;
1087
mf->code = s5k6aa_formats[index].code;
1088
mf->field = V4L2_FIELD_NONE;
1091
static int s5k6aa_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1092
struct v4l2_subdev_format *fmt)
1094
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1095
struct v4l2_mbus_framefmt *mf;
1097
memset(fmt->reserved, 0, sizeof(fmt->reserved));
1099
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1100
mf = v4l2_subdev_get_try_format(fh, 0);
1105
mutex_lock(&s5k6aa->lock);
1106
fmt->format = s5k6aa->preset->mbus_fmt;
1107
mutex_unlock(&s5k6aa->lock);
1112
static int s5k6aa_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1113
struct v4l2_subdev_format *fmt)
1115
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1116
struct s5k6aa_preset *preset = s5k6aa->preset;
1117
struct v4l2_mbus_framefmt *mf;
1118
struct v4l2_rect *crop;
1121
mutex_lock(&s5k6aa->lock);
1122
s5k6aa_try_format(s5k6aa, &fmt->format);
1124
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1125
mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1126
crop = v4l2_subdev_get_try_crop(fh, 0);
1128
if (s5k6aa->streaming) {
1131
mf = &preset->mbus_fmt;
1132
crop = &s5k6aa->ccd_rect;
1133
s5k6aa->apply_cfg = 1;
1138
struct v4l2_subdev_frame_interval fiv = {
1144
* Make sure the crop window is valid, i.e. its size is
1145
* greater than the output window, as the ISP supports
1146
* only down-scaling.
1148
crop->width = clamp_t(unsigned int, crop->width, mf->width,
1149
S5K6AA_WIN_WIDTH_MAX);
1150
crop->height = clamp_t(unsigned int, crop->height, mf->height,
1151
S5K6AA_WIN_HEIGHT_MAX);
1152
crop->left = clamp_t(unsigned int, crop->left, 0,
1153
S5K6AA_WIN_WIDTH_MAX - crop->width);
1154
crop->top = clamp_t(unsigned int, crop->top, 0,
1155
S5K6AA_WIN_HEIGHT_MAX - crop->height);
1157
/* Reset to minimum possible frame interval */
1158
ret = __s5k6aa_set_frame_interval(s5k6aa, &fiv);
1160
mutex_unlock(&s5k6aa->lock);
1165
static int s5k6aa_get_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1166
struct v4l2_subdev_crop *crop)
1168
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1169
struct v4l2_rect *rect;
1171
memset(crop->reserved, 0, sizeof(crop->reserved));
1172
mutex_lock(&s5k6aa->lock);
1174
rect = __s5k6aa_get_crop_rect(s5k6aa, fh, crop->which);
1178
mutex_unlock(&s5k6aa->lock);
1180
v4l2_dbg(1, debug, sd, "Current crop rectangle: (%d,%d)/%dx%d\n",
1181
rect->left, rect->top, rect->width, rect->height);
1186
static int s5k6aa_set_crop(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1187
struct v4l2_subdev_crop *crop)
1189
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1190
struct v4l2_mbus_framefmt *mf;
1191
unsigned int max_x, max_y;
1192
struct v4l2_rect *crop_r;
1194
mutex_lock(&s5k6aa->lock);
1195
crop_r = __s5k6aa_get_crop_rect(s5k6aa, fh, crop->which);
1197
if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1198
mf = &s5k6aa->preset->mbus_fmt;
1199
s5k6aa->apply_crop = 1;
1201
mf = v4l2_subdev_get_try_format(fh, 0);
1203
v4l_bound_align_image(&crop->rect.width, mf->width,
1204
S5K6AA_WIN_WIDTH_MAX, 1,
1205
&crop->rect.height, mf->height,
1206
S5K6AA_WIN_HEIGHT_MAX, 1, 0);
1208
max_x = (S5K6AA_WIN_WIDTH_MAX - crop->rect.width) & ~1;
1209
max_y = (S5K6AA_WIN_HEIGHT_MAX - crop->rect.height) & ~1;
1211
crop->rect.left = clamp_t(unsigned int, crop->rect.left, 0, max_x);
1212
crop->rect.top = clamp_t(unsigned int, crop->rect.top, 0, max_y);
1214
*crop_r = crop->rect;
1216
mutex_unlock(&s5k6aa->lock);
1218
v4l2_dbg(1, debug, sd, "Set crop rectangle: (%d,%d)/%dx%d\n",
1219
crop_r->left, crop_r->top, crop_r->width, crop_r->height);
1224
static const struct v4l2_subdev_pad_ops s5k6aa_pad_ops = {
1225
.enum_mbus_code = s5k6aa_enum_mbus_code,
1226
.enum_frame_size = s5k6aa_enum_frame_size,
1227
.enum_frame_interval = s5k6aa_enum_frame_interval,
1228
.get_fmt = s5k6aa_get_fmt,
1229
.set_fmt = s5k6aa_set_fmt,
1230
.get_crop = s5k6aa_get_crop,
1231
.set_crop = s5k6aa_set_crop,
1234
static const struct v4l2_subdev_video_ops s5k6aa_video_ops = {
1235
.g_frame_interval = s5k6aa_g_frame_interval,
1236
.s_frame_interval = s5k6aa_s_frame_interval,
1237
.s_stream = s5k6aa_s_stream,
1241
* V4L2 subdev controls
1244
static int s5k6aa_s_ctrl(struct v4l2_ctrl *ctrl)
1246
struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
1247
struct i2c_client *client = v4l2_get_subdevdata(sd);
1248
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1251
v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val);
1253
mutex_lock(&s5k6aa->lock);
1255
* If the device is not powered up by the host driver do
1256
* not apply any controls to H/W at this time. Instead
1257
* the controls will be restored right after power-up.
1259
if (s5k6aa->power == 0)
1261
idx = s5k6aa->preset->index;
1264
case V4L2_CID_AUTO_WHITE_BALANCE:
1265
err = s5k6aa_set_awb(s5k6aa, ctrl->val);
1268
case V4L2_CID_BRIGHTNESS:
1269
err = s5k6aa_write(client, REG_USER_BRIGHTNESS, ctrl->val);
1272
case V4L2_CID_COLORFX:
1273
err = s5k6aa_set_colorfx(s5k6aa, ctrl->val);
1276
case V4L2_CID_CONTRAST:
1277
err = s5k6aa_write(client, REG_USER_CONTRAST, ctrl->val);
1280
case V4L2_CID_EXPOSURE_AUTO:
1281
err = s5k6aa_set_auto_exposure(s5k6aa, ctrl->val);
1284
case V4L2_CID_HFLIP:
1285
err = s5k6aa_set_mirror(s5k6aa, ctrl->val);
1288
err = s5k6aa_write(client, REG_G_PREV_CFG_CHG, 1);
1291
case V4L2_CID_POWER_LINE_FREQUENCY:
1292
err = s5k6aa_set_anti_flicker(s5k6aa, ctrl->val);
1295
case V4L2_CID_SATURATION:
1296
err = s5k6aa_write(client, REG_USER_SATURATION, ctrl->val);
1299
case V4L2_CID_SHARPNESS:
1300
err = s5k6aa_write(client, REG_USER_SHARPBLUR, ctrl->val);
1303
case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
1304
err = s5k6aa_write(client, REG_P_COLORTEMP(idx), ctrl->val);
1307
err = s5k6aa_write(client, REG_G_PREV_CFG_CHG, 1);
1311
mutex_unlock(&s5k6aa->lock);
1315
static const struct v4l2_ctrl_ops s5k6aa_ctrl_ops = {
1316
.s_ctrl = s5k6aa_s_ctrl,
1319
static int s5k6aa_log_status(struct v4l2_subdev *sd)
1321
v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
1325
#define V4L2_CID_RED_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1001)
1326
#define V4L2_CID_GREEN_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1002)
1327
#define V4L2_CID_BLUE_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1003)
1329
static const struct v4l2_ctrl_config s5k6aa_ctrls[] = {
1331
.ops = &s5k6aa_ctrl_ops,
1332
.id = V4L2_CID_RED_GAIN,
1333
.type = V4L2_CTRL_TYPE_INTEGER,
1334
.name = "Gain, Red",
1340
.ops = &s5k6aa_ctrl_ops,
1341
.id = V4L2_CID_GREEN_GAIN,
1342
.type = V4L2_CTRL_TYPE_INTEGER,
1343
.name = "Gain, Green",
1349
.ops = &s5k6aa_ctrl_ops,
1350
.id = V4L2_CID_BLUE_GAIN,
1351
.type = V4L2_CTRL_TYPE_INTEGER,
1352
.name = "Gain, Blue",
1360
static int s5k6aa_initialize_ctrls(struct s5k6aa *s5k6aa)
1362
const struct v4l2_ctrl_ops *ops = &s5k6aa_ctrl_ops;
1363
struct s5k6aa_ctrls *ctrls = &s5k6aa->ctrls;
1364
struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1366
int ret = v4l2_ctrl_handler_init(hdl, 16);
1369
/* Auto white balance cluster */
1370
ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE,
1372
ctrls->gain_red = v4l2_ctrl_new_custom(hdl, &s5k6aa_ctrls[0], NULL);
1373
ctrls->gain_green = v4l2_ctrl_new_custom(hdl, &s5k6aa_ctrls[1], NULL);
1374
ctrls->gain_blue = v4l2_ctrl_new_custom(hdl, &s5k6aa_ctrls[2], NULL);
1375
v4l2_ctrl_auto_cluster(4, &ctrls->awb, 0, false);
1377
ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1378
ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1379
v4l2_ctrl_cluster(2, &ctrls->hflip);
1381
ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
1382
V4L2_CID_EXPOSURE_AUTO,
1383
V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1384
/* Exposure time: x 1 us */
1385
ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
1386
0, 6000000U, 1, 100000U);
1387
/* Total gain: 256 <=> 1x */
1388
ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1390
v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false);
1392
v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
1393
V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
1394
V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
1396
v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX,
1397
V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE);
1399
v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE,
1402
v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
1403
v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0);
1404
v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
1405
v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0);
1409
v4l2_ctrl_handler_free(hdl);
1413
s5k6aa->sd.ctrl_handler = hdl;
1418
* V4L2 subdev internal operations
1420
static int s5k6aa_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1422
struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
1423
struct v4l2_rect *crop = v4l2_subdev_get_try_crop(fh, 0);
1425
format->colorspace = s5k6aa_formats[0].colorspace;
1426
format->code = s5k6aa_formats[0].code;
1427
format->width = S5K6AA_OUT_WIDTH_DEF;
1428
format->height = S5K6AA_OUT_HEIGHT_DEF;
1429
format->field = V4L2_FIELD_NONE;
1431
crop->width = S5K6AA_WIN_WIDTH_MAX;
1432
crop->height = S5K6AA_WIN_HEIGHT_MAX;
1439
int s5k6aa_check_fw_revision(struct s5k6aa *s5k6aa)
1441
struct i2c_client *client = v4l2_get_subdevdata(&s5k6aa->sd);
1442
u16 api_ver = 0, fw_rev = 0;
1444
int ret = s5k6aa_set_ahb_address(client);
1447
ret = s5k6aa_read(client, REG_FW_APIVER, &api_ver);
1449
ret = s5k6aa_read(client, REG_FW_REVISION, &fw_rev);
1451
v4l2_err(&s5k6aa->sd, "FW revision check failed!\n");
1455
v4l2_info(&s5k6aa->sd, "FW API ver.: 0x%X, FW rev.: 0x%X\n",
1458
return api_ver == S5K6AAFX_FW_APIVER ? 0 : -ENODEV;
1461
static int s5k6aa_registered(struct v4l2_subdev *sd)
1463
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1466
mutex_lock(&s5k6aa->lock);
1467
ret = __s5k6aa_power_on(s5k6aa);
1470
ret = s5k6aa_check_fw_revision(s5k6aa);
1471
__s5k6aa_power_off(s5k6aa);
1473
mutex_unlock(&s5k6aa->lock);
1478
static const struct v4l2_subdev_internal_ops s5k6aa_subdev_internal_ops = {
1479
.registered = s5k6aa_registered,
1480
.open = s5k6aa_open,
1483
static const struct v4l2_subdev_core_ops s5k6aa_core_ops = {
1484
.s_power = s5k6aa_set_power,
1485
.log_status = s5k6aa_log_status,
1488
static const struct v4l2_subdev_ops s5k6aa_subdev_ops = {
1489
.core = &s5k6aa_core_ops,
1490
.pad = &s5k6aa_pad_ops,
1491
.video = &s5k6aa_video_ops,
1497
static int s5k6aa_configure_gpio(int nr, int val, const char *name)
1499
unsigned long flags = val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
1502
if (!gpio_is_valid(nr))
1504
ret = gpio_request_one(nr, flags, name);
1510
static void s5k6aa_free_gpios(struct s5k6aa *s5k6aa)
1514
for (i = 0; i < ARRAY_SIZE(s5k6aa->gpio); i++) {
1515
if (!gpio_is_valid(s5k6aa->gpio[i].gpio))
1517
gpio_free(s5k6aa->gpio[i].gpio);
1518
s5k6aa->gpio[i].gpio = -EINVAL;
1522
static int s5k6aa_configure_gpios(struct s5k6aa *s5k6aa,
1523
const struct s5k6aa_platform_data *pdata)
1525
const struct s5k6aa_gpio *gpio = &pdata->gpio_stby;
1528
s5k6aa->gpio[STBY].gpio = -EINVAL;
1529
s5k6aa->gpio[RST].gpio = -EINVAL;
1531
ret = s5k6aa_configure_gpio(gpio->gpio, gpio->level, "S5K6AA_STBY");
1533
s5k6aa_free_gpios(s5k6aa);
1536
s5k6aa->gpio[STBY] = *gpio;
1537
if (gpio_is_valid(gpio->gpio))
1538
gpio_set_value(gpio->gpio, 0);
1540
gpio = &pdata->gpio_reset;
1541
ret = s5k6aa_configure_gpio(gpio->gpio, gpio->level, "S5K6AA_RST");
1543
s5k6aa_free_gpios(s5k6aa);
1546
s5k6aa->gpio[RST] = *gpio;
1547
if (gpio_is_valid(gpio->gpio))
1548
gpio_set_value(gpio->gpio, 0);
1553
static int s5k6aa_probe(struct i2c_client *client,
1554
const struct i2c_device_id *id)
1556
const struct s5k6aa_platform_data *pdata = client->dev.platform_data;
1557
struct v4l2_subdev *sd;
1558
struct s5k6aa *s5k6aa;
1561
if (pdata == NULL) {
1562
dev_err(&client->dev, "Platform data not specified\n");
1566
if (pdata->mclk_frequency == 0) {
1567
dev_err(&client->dev, "MCLK frequency not specified\n");
1571
s5k6aa = kzalloc(sizeof(*s5k6aa), GFP_KERNEL);
1575
mutex_init(&s5k6aa->lock);
1577
s5k6aa->mclk_frequency = pdata->mclk_frequency;
1578
s5k6aa->bus_type = pdata->bus_type;
1579
s5k6aa->mipi_lanes = pdata->nlanes;
1580
s5k6aa->s_power = pdata->set_power;
1581
s5k6aa->inv_hflip = pdata->horiz_flip;
1582
s5k6aa->inv_vflip = pdata->vert_flip;
1585
strlcpy(sd->name, DRIVER_NAME, sizeof(sd->name));
1586
v4l2_i2c_subdev_init(sd, client, &s5k6aa_subdev_ops);
1588
sd->internal_ops = &s5k6aa_subdev_internal_ops;
1589
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1591
s5k6aa->pad.flags = MEDIA_PAD_FL_SOURCE;
1592
sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
1593
ret = media_entity_init(&sd->entity, 1, &s5k6aa->pad, 0);
1597
ret = s5k6aa_configure_gpios(s5k6aa, pdata);
1601
for (i = 0; i < S5K6AA_NUM_SUPPLIES; i++)
1602
s5k6aa->supplies[i].supply = s5k6aa_supply_names[i];
1604
ret = regulator_bulk_get(&client->dev, S5K6AA_NUM_SUPPLIES,
1607
dev_err(&client->dev, "Failed to get regulators\n");
1611
ret = s5k6aa_initialize_ctrls(s5k6aa);
1615
s5k6aa_presets_data_init(s5k6aa);
1617
s5k6aa->ccd_rect.width = S5K6AA_WIN_WIDTH_MAX;
1618
s5k6aa->ccd_rect.height = S5K6AA_WIN_HEIGHT_MAX;
1619
s5k6aa->ccd_rect.left = 0;
1620
s5k6aa->ccd_rect.top = 0;
1625
regulator_bulk_free(S5K6AA_NUM_SUPPLIES, s5k6aa->supplies);
1627
s5k6aa_free_gpios(s5k6aa);
1629
media_entity_cleanup(&s5k6aa->sd.entity);
1635
static int s5k6aa_remove(struct i2c_client *client)
1637
struct v4l2_subdev *sd = i2c_get_clientdata(client);
1638
struct s5k6aa *s5k6aa = to_s5k6aa(sd);
1640
v4l2_device_unregister_subdev(sd);
1641
v4l2_ctrl_handler_free(sd->ctrl_handler);
1642
media_entity_cleanup(&sd->entity);
1643
regulator_bulk_free(S5K6AA_NUM_SUPPLIES, s5k6aa->supplies);
1644
s5k6aa_free_gpios(s5k6aa);
1650
static const struct i2c_device_id s5k6aa_id[] = {
1654
MODULE_DEVICE_TABLE(i2c, s5k6aa_id);
1657
static struct i2c_driver s5k6aa_i2c_driver = {
1661
.probe = s5k6aa_probe,
1662
.remove = s5k6aa_remove,
1663
.id_table = s5k6aa_id,
1666
static int __init s5k6aa_init(void)
1668
return i2c_add_driver(&s5k6aa_i2c_driver);
1671
static void __exit s5k6aa_exit(void)
1673
i2c_del_driver(&s5k6aa_i2c_driver);
1676
module_init(s5k6aa_init);
1677
module_exit(s5k6aa_exit);
1679
MODULE_DESCRIPTION("Samsung S5K6AA(FX) SXGA camera driver");
1680
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1681
MODULE_LICENSE("GPL");