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* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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#include <rdma/ib_umem.h>
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#include <linux/atomic.h>
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#define T4_ULPTX_MIN_IO 32
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#define C4IW_MAX_INLINE_SIZE 96
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static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
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struct ulp_mem_io *req;
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struct ulptx_idata *sc;
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u8 wr_len, *to_dp, *from_dp;
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int copy_len, num_wqe, i, ret = 0;
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struct c4iw_wr_wait wr_wait;
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PDBG("%s addr 0x%x len %u\n", __func__, addr, len);
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num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
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c4iw_init_wr_wait(&wr_wait);
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for (i = 0; i < num_wqe; i++) {
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copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
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wr_len = roundup(sizeof *req + sizeof *sc +
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roundup(copy_len, T4_ULPTX_MIN_IO), 16);
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skb = alloc_skb(wr_len, GFP_KERNEL);
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set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
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req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
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memset(req, 0, wr_len);
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INIT_ULPTX_WR(req, wr_len, 0, 0);
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if (i == (num_wqe-1)) {
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req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR) |
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req->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait;
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req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR));
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req->wr.wr_mid = cpu_to_be32(
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FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16)));
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req->cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE) | (1<<23));
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req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN(
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DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
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req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
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req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR(addr + i * 3));
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sc = (struct ulptx_idata *)(req + 1);
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sc->cmd_more = cpu_to_be32(ULPTX_CMD(ULP_TX_SC_IMM));
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sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
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to_dp = (u8 *)(sc + 1);
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from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
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memcpy(to_dp, from_dp, copy_len);
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memset(to_dp, 0, copy_len);
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if (copy_len % T4_ULPTX_MIN_IO)
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memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
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(copy_len % T4_ULPTX_MIN_IO));
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ret = c4iw_ofld_send(rdev, skb);
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len -= C4IW_MAX_INLINE_SIZE;
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ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
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* Build and write a TPT entry.
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* IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
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* pbl_size and pbl_addr
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static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
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u32 *stag, u8 stag_state, u32 pdid,
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enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
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int bind_enabled, u32 zbva, u64 to,
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u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr)
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struct fw_ri_tpte tpt;
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if (c4iw_fatal_error(rdev))
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stag_state = stag_state > 0;
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stag_idx = (*stag) >> 8;
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if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
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stag_idx = c4iw_get_resource(&rdev->resource.tpt_fifo,
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&rdev->resource.tpt_fifo_lock);
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*stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
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PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
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__func__, stag_state, type, pdid, stag_idx);
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/* write TPT entry */
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memset(&tpt, 0, sizeof(tpt));
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tpt.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID |
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V_FW_RI_TPTE_STAGKEY((*stag & M_FW_RI_TPTE_STAGKEY)) |
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V_FW_RI_TPTE_STAGSTATE(stag_state) |
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V_FW_RI_TPTE_STAGTYPE(type) | V_FW_RI_TPTE_PDID(pdid));
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tpt.locread_to_qpid = cpu_to_be32(V_FW_RI_TPTE_PERM(perm) |
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(bind_enabled ? F_FW_RI_TPTE_MWBINDEN : 0) |
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V_FW_RI_TPTE_ADDRTYPE((zbva ? FW_RI_ZERO_BASED_TO :
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V_FW_RI_TPTE_PS(page_size));
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tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
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V_FW_RI_TPTE_PBLADDR(PBL_OFF(rdev, pbl_addr)>>3));
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tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
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tpt.va_hi = cpu_to_be32((u32)(to >> 32));
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tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
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tpt.dca_mwbcnt_pstag = cpu_to_be32(0);
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tpt.len_hi = cpu_to_be32((u32)(len >> 32));
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err = write_adapter_mem(rdev, stag_idx +
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(rdev->lldi.vr->stag.start >> 5),
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c4iw_put_resource(&rdev->resource.tpt_fifo, stag_idx,
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&rdev->resource.tpt_fifo_lock);
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static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
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u32 pbl_addr, u32 pbl_size)
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PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
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__func__, pbl_addr, rdev->lldi.vr->pbl.start,
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err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl);
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static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
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return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
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static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid)
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*stag = T4_STAG_UNSET;
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return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
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static int deallocate_window(struct c4iw_rdev *rdev, u32 stag)
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return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
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static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
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u32 pbl_size, u32 pbl_addr)
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*stag = T4_STAG_UNSET;
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return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
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0UL, 0, 0, pbl_size, pbl_addr);
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static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
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mhp->attr.stag = stag;
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mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
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PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp);
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return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
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static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
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struct c4iw_mr *mhp, int shift)
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u32 stag = T4_STAG_UNSET;
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ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
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FW_RI_STAG_NSMR, mhp->attr.perms,
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mhp->attr.mw_bind_enable, mhp->attr.zbva,
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mhp->attr.va_fbo, mhp->attr.len, shift - 12,
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mhp->attr.pbl_size, mhp->attr.pbl_addr);
241
ret = finish_mem_reg(mhp, stag);
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dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
248
static int reregister_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
249
struct c4iw_mr *mhp, int shift, int npages)
254
if (npages > mhp->attr.pbl_size)
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stag = mhp->attr.stag;
258
ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
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FW_RI_STAG_NSMR, mhp->attr.perms,
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mhp->attr.mw_bind_enable, mhp->attr.zbva,
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mhp->attr.va_fbo, mhp->attr.len, shift - 12,
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mhp->attr.pbl_size, mhp->attr.pbl_addr);
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ret = finish_mem_reg(mhp, stag);
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dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
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static int alloc_pbl(struct c4iw_mr *mhp, int npages)
276
mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
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if (!mhp->attr.pbl_addr)
282
mhp->attr.pbl_size = npages;
287
static int build_phys_page_list(struct ib_phys_buf *buffer_list,
288
int num_phys_buf, u64 *iova_start,
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u64 *total_size, int *npages,
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int *shift, __be64 **page_list)
297
for (i = 0; i < num_phys_buf; ++i) {
298
if (i != 0 && buffer_list[i].addr & ~PAGE_MASK)
300
if (i != 0 && i != num_phys_buf - 1 &&
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(buffer_list[i].size & ~PAGE_MASK))
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*total_size += buffer_list[i].size;
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mask |= buffer_list[i].addr;
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mask |= buffer_list[i].addr & PAGE_MASK;
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if (i != num_phys_buf - 1)
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mask |= buffer_list[i].addr + buffer_list[i].size;
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mask |= (buffer_list[i].addr + buffer_list[i].size +
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PAGE_SIZE - 1) & PAGE_MASK;
315
if (*total_size > 0xFFFFFFFFULL)
318
/* Find largest page shift we can use to cover buffers */
319
for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift))
320
if ((1ULL << *shift) & mask)
323
buffer_list[0].size += buffer_list[0].addr & ((1ULL << *shift) - 1);
324
buffer_list[0].addr &= ~0ull << *shift;
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for (i = 0; i < num_phys_buf; ++i)
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*npages += (buffer_list[i].size +
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(1ULL << *shift) - 1) >> *shift;
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*page_list = kmalloc(sizeof(u64) * *npages, GFP_KERNEL);
339
for (i = 0; i < num_phys_buf; ++i)
341
j < (buffer_list[i].size + (1ULL << *shift) - 1) >> *shift;
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(*page_list)[n++] = cpu_to_be64(buffer_list[i].addr +
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((u64) j << *shift));
346
PDBG("%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d\n",
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__func__, (unsigned long long)*iova_start,
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(unsigned long long)mask, *shift, (unsigned long long)*total_size,
355
int c4iw_reregister_phys_mem(struct ib_mr *mr, int mr_rereg_mask,
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struct ib_pd *pd, struct ib_phys_buf *buffer_list,
357
int num_phys_buf, int acc, u64 *iova_start)
360
struct c4iw_mr mh, *mhp;
362
struct c4iw_dev *rhp;
363
__be64 *page_list = NULL;
369
PDBG("%s ib_mr %p ib_pd %p\n", __func__, mr, pd);
371
/* There can be no memory windows */
372
if (atomic_read(&mr->usecnt))
375
mhp = to_c4iw_mr(mr);
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php = to_c4iw_pd(mr->pd);
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/* make sure we are on the same adapter */
383
memcpy(&mh, mhp, sizeof *mhp);
385
if (mr_rereg_mask & IB_MR_REREG_PD)
386
php = to_c4iw_pd(pd);
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if (mr_rereg_mask & IB_MR_REREG_ACCESS) {
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mh.attr.perms = c4iw_ib_to_tpt_access(acc);
389
mh.attr.mw_bind_enable = (acc & IB_ACCESS_MW_BIND) ==
392
if (mr_rereg_mask & IB_MR_REREG_TRANS) {
393
ret = build_phys_page_list(buffer_list, num_phys_buf,
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&total_size, &npages,
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ret = reregister_mem(rhp, php, &mh, shift, npages);
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if (mr_rereg_mask & IB_MR_REREG_PD)
406
mhp->attr.pdid = php->pdid;
407
if (mr_rereg_mask & IB_MR_REREG_ACCESS)
408
mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
409
if (mr_rereg_mask & IB_MR_REREG_TRANS) {
411
mhp->attr.va_fbo = *iova_start;
412
mhp->attr.page_size = shift - 12;
413
mhp->attr.len = (u32) total_size;
414
mhp->attr.pbl_size = npages;
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struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
421
struct ib_phys_buf *buffer_list,
422
int num_phys_buf, int acc, u64 *iova_start)
428
struct c4iw_dev *rhp;
433
PDBG("%s ib_pd %p\n", __func__, pd);
434
php = to_c4iw_pd(pd);
437
mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
439
return ERR_PTR(-ENOMEM);
443
/* First check that we have enough alignment */
444
if ((*iova_start & ~PAGE_MASK) != (buffer_list[0].addr & ~PAGE_MASK)) {
449
if (num_phys_buf > 1 &&
450
((buffer_list[0].addr + buffer_list[0].size) & ~PAGE_MASK)) {
455
ret = build_phys_page_list(buffer_list, num_phys_buf, iova_start,
456
&total_size, &npages, &shift,
461
ret = alloc_pbl(mhp, npages);
467
ret = write_pbl(&mhp->rhp->rdev, page_list, mhp->attr.pbl_addr,
473
mhp->attr.pdid = php->pdid;
476
mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
477
mhp->attr.va_fbo = *iova_start;
478
mhp->attr.page_size = shift - 12;
480
mhp->attr.len = (u32) total_size;
481
mhp->attr.pbl_size = npages;
482
ret = register_mem(rhp, php, mhp, shift);
489
c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
490
mhp->attr.pbl_size << 3);
498
struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
500
struct c4iw_dev *rhp;
504
u32 stag = T4_STAG_UNSET;
506
PDBG("%s ib_pd %p\n", __func__, pd);
507
php = to_c4iw_pd(pd);
510
mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
512
return ERR_PTR(-ENOMEM);
515
mhp->attr.pdid = php->pdid;
516
mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
517
mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
519
mhp->attr.va_fbo = 0;
520
mhp->attr.page_size = 0;
521
mhp->attr.len = ~0UL;
522
mhp->attr.pbl_size = 0;
524
ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
525
FW_RI_STAG_NSMR, mhp->attr.perms,
526
mhp->attr.mw_bind_enable, 0, 0, ~0UL, 0, 0, 0);
530
ret = finish_mem_reg(mhp, stag);
535
dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
542
struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
543
u64 virt, int acc, struct ib_udata *udata)
549
struct ib_umem_chunk *chunk;
550
struct c4iw_dev *rhp;
554
PDBG("%s ib_pd %p\n", __func__, pd);
557
return ERR_PTR(-EINVAL);
559
if ((length + start) < start)
560
return ERR_PTR(-EINVAL);
562
php = to_c4iw_pd(pd);
564
mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
566
return ERR_PTR(-ENOMEM);
570
mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
571
if (IS_ERR(mhp->umem)) {
572
err = PTR_ERR(mhp->umem);
577
shift = ffs(mhp->umem->page_size) - 1;
580
list_for_each_entry(chunk, &mhp->umem->chunk_list, list)
583
err = alloc_pbl(mhp, n);
587
pages = (__be64 *) __get_free_page(GFP_KERNEL);
595
list_for_each_entry(chunk, &mhp->umem->chunk_list, list)
596
for (j = 0; j < chunk->nmap; ++j) {
597
len = sg_dma_len(&chunk->page_list[j]) >> shift;
598
for (k = 0; k < len; ++k) {
599
pages[i++] = cpu_to_be64(sg_dma_address(
600
&chunk->page_list[j]) +
601
mhp->umem->page_size * k);
602
if (i == PAGE_SIZE / sizeof *pages) {
603
err = write_pbl(&mhp->rhp->rdev,
605
mhp->attr.pbl_addr + (n << 3), i);
615
err = write_pbl(&mhp->rhp->rdev, pages,
616
mhp->attr.pbl_addr + (n << 3), i);
619
free_page((unsigned long) pages);
623
mhp->attr.pdid = php->pdid;
625
mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
626
mhp->attr.va_fbo = virt;
627
mhp->attr.page_size = shift - 12;
628
mhp->attr.len = length;
630
err = register_mem(rhp, php, mhp, shift);
637
c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
638
mhp->attr.pbl_size << 3);
641
ib_umem_release(mhp->umem);
646
struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd)
648
struct c4iw_dev *rhp;
655
php = to_c4iw_pd(pd);
657
mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
659
return ERR_PTR(-ENOMEM);
660
ret = allocate_window(&rhp->rdev, &stag, php->pdid);
666
mhp->attr.pdid = php->pdid;
667
mhp->attr.type = FW_RI_STAG_MW;
668
mhp->attr.stag = stag;
670
mhp->ibmw.rkey = stag;
671
if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
672
deallocate_window(&rhp->rdev, mhp->attr.stag);
674
return ERR_PTR(-ENOMEM);
676
PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
680
int c4iw_dealloc_mw(struct ib_mw *mw)
682
struct c4iw_dev *rhp;
686
mhp = to_c4iw_mw(mw);
688
mmid = (mw->rkey) >> 8;
689
deallocate_window(&rhp->rdev, mhp->attr.stag);
690
remove_handle(rhp, &rhp->mmidr, mmid);
692
PDBG("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp);
696
struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth)
698
struct c4iw_dev *rhp;
705
php = to_c4iw_pd(pd);
707
mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
714
ret = alloc_pbl(mhp, pbl_depth);
717
mhp->attr.pbl_size = pbl_depth;
718
ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
719
mhp->attr.pbl_size, mhp->attr.pbl_addr);
722
mhp->attr.pdid = php->pdid;
723
mhp->attr.type = FW_RI_STAG_NSMR;
724
mhp->attr.stag = stag;
727
mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
728
if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
733
PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
736
dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
739
c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
740
mhp->attr.pbl_size << 3);
747
struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(struct ib_device *device,
750
struct c4iw_fr_page_list *c4pl;
751
struct c4iw_dev *dev = to_c4iw_dev(device);
753
int size = sizeof *c4pl + page_list_len * sizeof(u64);
755
c4pl = dma_alloc_coherent(&dev->rdev.lldi.pdev->dev, size,
756
&dma_addr, GFP_KERNEL);
758
return ERR_PTR(-ENOMEM);
760
dma_unmap_addr_set(c4pl, mapping, dma_addr);
761
c4pl->dma_addr = dma_addr;
764
c4pl->ibpl.page_list = (u64 *)(c4pl + 1);
765
c4pl->ibpl.max_page_list_len = page_list_len;
770
void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *ibpl)
772
struct c4iw_fr_page_list *c4pl = to_c4iw_fr_page_list(ibpl);
774
dma_free_coherent(&c4pl->dev->rdev.lldi.pdev->dev, c4pl->size,
775
c4pl, dma_unmap_addr(c4pl, mapping));
778
int c4iw_dereg_mr(struct ib_mr *ib_mr)
780
struct c4iw_dev *rhp;
784
PDBG("%s ib_mr %p\n", __func__, ib_mr);
785
/* There can be no memory windows */
786
if (atomic_read(&ib_mr->usecnt))
789
mhp = to_c4iw_mr(ib_mr);
791
mmid = mhp->attr.stag >> 8;
792
dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
794
if (mhp->attr.pbl_size)
795
c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
796
mhp->attr.pbl_size << 3);
797
remove_handle(rhp, &rhp->mmidr, mmid);
799
kfree((void *) (unsigned long) mhp->kva);
801
ib_umem_release(mhp->umem);
802
PDBG("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp);