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* V4L2 Driver for PXA camera host
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* Copyright (C) 2006, Sascha Hauer, Pengutronix
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* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/time.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-dev.h>
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#include <media/videobuf-dma-sg.h>
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#include <media/soc_camera.h>
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#include <media/soc_mediabus.h>
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#include <linux/videodev2.h>
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#include <mach/camera.h>
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#define PXA_CAM_VERSION "0.0.6"
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#define PXA_CAM_DRV_NAME "pxa27x-camera"
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/* Camera Interface */
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#define CICR0_DMAEN (1 << 31) /* DMA request enable */
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#define CICR0_PAR_EN (1 << 30) /* Parity enable */
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#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
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#define CICR0_ENB (1 << 28) /* Camera interface enable */
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#define CICR0_DIS (1 << 27) /* Camera interface disable */
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#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
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#define CICR0_TOM (1 << 9) /* Time-out mask */
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#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
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#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
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#define CICR0_EOLM (1 << 6) /* End-of-line mask */
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#define CICR0_PERRM (1 << 5) /* Parity-error mask */
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#define CICR0_QDM (1 << 4) /* Quick-disable mask */
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#define CICR0_CDM (1 << 3) /* Disable-done mask */
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#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
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#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
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#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
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#define CICR1_TBIT (1 << 31) /* Transparency bit */
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#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
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#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
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#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
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#define CICR1_RGB_F (1 << 11) /* RGB format */
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#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
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#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
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#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
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#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
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#define CICR1_DW (0x7 << 0) /* Data width mask */
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#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
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#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
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#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
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#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
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#define CICR2_FSW (0x7 << 0) /* Frame stabilization
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#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
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#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
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#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
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#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
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#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
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#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
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#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
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#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
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#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
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#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
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#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
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#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
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#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
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#define CISR_FTO (1 << 15) /* FIFO time-out */
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#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
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#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
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#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
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#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
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#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
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#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
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#define CISR_EOL (1 << 8) /* End of line */
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#define CISR_PAR_ERR (1 << 7) /* Parity error */
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#define CISR_CQD (1 << 6) /* Camera interface quick disable */
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#define CISR_CDD (1 << 5) /* Camera interface disable done */
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#define CISR_SOF (1 << 4) /* Start of frame */
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#define CISR_EOF (1 << 3) /* End of frame */
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#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
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#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
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#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
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#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
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#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
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#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
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#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
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#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
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#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
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#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
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#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
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#define CICR0_SIM_MP (0 << 24)
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#define CICR0_SIM_SP (1 << 24)
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#define CICR0_SIM_MS (2 << 24)
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#define CICR0_SIM_EP (3 << 24)
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#define CICR0_SIM_ES (4 << 24)
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#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
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#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
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#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
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#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
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#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
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#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
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#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
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#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
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#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
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#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
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#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
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#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
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#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
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#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
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#define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
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CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
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CICR0_EOFM | CICR0_FOM)
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enum pxa_camera_active_dma {
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/* descriptor needed for the PXA DMA engine */
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struct pxa_dma_desc *sg_cpu;
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/* buffer for one video frame */
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/* common v4l buffer stuff -- must be first */
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struct videobuf_buffer vb;
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enum v4l2_mbus_pixelcode code;
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/* our descriptor lists for Y, U and V channels */
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struct pxa_cam_dma dmas[3];
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enum pxa_camera_active_dma active_dma;
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struct pxa_camera_dev {
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struct soc_camera_host soc_host;
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* PXA27x is only supposed to handle one camera on its Quick Capture
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* interface. If anyone ever builds hardware to enable more than
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* one camera, they will have to modify this driver too
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struct soc_camera_device *icd;
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unsigned int dma_chans[3];
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struct pxacamera_platform_data *pdata;
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struct resource *res;
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unsigned long platform_flags;
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u16 width_flags; /* max 10 bits */
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struct list_head capture;
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struct pxa_buffer *active;
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struct pxa_dma_desc *sg_tail[3];
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static const char *pxa_cam_driver_description = "PXA_Camera";
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static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
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* Videobuf operations
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static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
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struct soc_camera_device *icd = vq->priv_data;
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int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
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icd->current_fmt->host_fmt);
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if (bytes_per_line < 0)
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return bytes_per_line;
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dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
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*size = bytes_per_line * icd->user_height;
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if (*size * *count > vid_limit * 1024 * 1024)
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*count = (vid_limit * 1024 * 1024) / *size;
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static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
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struct soc_camera_device *icd = vq->priv_data;
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struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
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struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
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BUG_ON(in_interrupt());
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dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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&buf->vb, buf->vb.baddr, buf->vb.bsize);
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* This waits until this buffer is out of danger, i.e., until it is no
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* longer in STATE_QUEUED or STATE_ACTIVE
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videobuf_waiton(vq, &buf->vb, 0, 0);
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videobuf_dma_unmap(vq->dev, dma);
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videobuf_dma_free(dma);
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for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
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if (buf->dmas[i].sg_cpu)
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dma_free_coherent(ici->v4l2_dev.dev,
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buf->dmas[i].sg_size,
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buf->dmas[i].sg_dma);
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buf->dmas[i].sg_cpu = NULL;
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buf->vb.state = VIDEOBUF_NEEDS_INIT;
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static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
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int sg_first_ofs, int size)
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int i, offset, dma_len, xfer_len;
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struct scatterlist *sg;
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offset = sg_first_ofs;
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for_each_sg(sglist, sg, sglen, i) {
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dma_len = sg_dma_len(sg);
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/* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
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xfer_len = roundup(min(dma_len - offset, size), 8);
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size = max(0, size - xfer_len);
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* pxa_init_dma_channel - init dma descriptors
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* @pcdev: pxa camera device
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* @buf: pxa buffer to find pxa dma channel
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* @dma: dma video buffer
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* @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
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* @cibr: camera Receive Buffer Register
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* @size: bytes to transfer
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* @sg_first: first element of sg_list
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* @sg_first_ofs: offset in first element of sg_list
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* Prepares the pxa dma descriptors to transfer one camera channel.
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* Beware sg_first and sg_first_ofs are both input and output parameters.
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* Returns 0 or -ENOMEM if no coherent memory is available
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static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
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struct pxa_buffer *buf,
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struct videobuf_dmabuf *dma, int channel,
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struct scatterlist **sg_first, int *sg_first_ofs)
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struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
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struct device *dev = pcdev->soc_host.v4l2_dev.dev;
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struct scatterlist *sg;
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int i, offset, sglen;
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int dma_len = 0, xfer_len = 0;
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dma_free_coherent(dev, pxa_dma->sg_size,
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pxa_dma->sg_cpu, pxa_dma->sg_dma);
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sglen = calculate_dma_sglen(*sg_first, dma->sglen,
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*sg_first_ofs, size);
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pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
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pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
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&pxa_dma->sg_dma, GFP_KERNEL);
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if (!pxa_dma->sg_cpu)
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pxa_dma->sglen = sglen;
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offset = *sg_first_ofs;
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dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
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*sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
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for_each_sg(*sg_first, sg, sglen, i) {
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dma_len = sg_dma_len(sg);
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/* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
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xfer_len = roundup(min(dma_len - offset, size), 8);
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size = max(0, size - xfer_len);
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pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
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pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
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pxa_dma->sg_cpu[i].dcmd =
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DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
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pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
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pxa_dma->sg_cpu[i].ddadr =
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pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
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dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
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pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
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sg_dma_address(sg) + offset, xfer_len);
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pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
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pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
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* Handle 1 special case :
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* - in 3 planes (YUV422P format), we might finish with xfer_len equal
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* to dma_len (end on PAGE boundary). In this case, the sg element
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* for next plane should be the next after the last used to store the
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* last scatter gather RAM page
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if (xfer_len >= dma_len) {
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*sg_first_ofs = xfer_len - dma_len;
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*sg_first = sg_next(sg);
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*sg_first_ofs = xfer_len;
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static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
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struct pxa_buffer *buf)
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buf->active_dma = DMA_Y;
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if (pcdev->channels == 3)
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buf->active_dma |= DMA_U | DMA_V;
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* Please check the DMA prepared buffer structure in :
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* Documentation/video4linux/pxa_camera.txt
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* Please check also in pxa_camera_check_link_miss() to understand why DMA chain
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* modification while DMA chain is running will work anyway.
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static int pxa_videobuf_prepare(struct videobuf_queue *vq,
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struct videobuf_buffer *vb, enum v4l2_field field)
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struct soc_camera_device *icd = vq->priv_data;
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struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
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struct pxa_camera_dev *pcdev = ici->priv;
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struct device *dev = pcdev->soc_host.v4l2_dev.dev;
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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int size_y, size_u = 0, size_v = 0;
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int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
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icd->current_fmt->host_fmt);
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if (bytes_per_line < 0)
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return bytes_per_line;
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dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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vb, vb->baddr, vb->bsize);
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/* Added list head initialization on alloc */
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WARN_ON(!list_empty(&vb->queue));
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* This can be useful if you want to see if we actually fill
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* the buffer with something
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memset((void *)vb->baddr, 0xaa, vb->bsize);
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BUG_ON(NULL == icd->current_fmt);
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* I think, in buf_prepare you only have to protect global data,
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* the actual buffer is yours
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if (buf->code != icd->current_fmt->code ||
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vb->width != icd->user_width ||
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vb->height != icd->user_height ||
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vb->field != field) {
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buf->code = icd->current_fmt->code;
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vb->width = icd->user_width;
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vb->height = icd->user_height;
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vb->state = VIDEOBUF_NEEDS_INIT;
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vb->size = bytes_per_line * vb->height;
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if (0 != vb->baddr && vb->bsize < vb->size) {
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if (vb->state == VIDEOBUF_NEEDS_INIT) {
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struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
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struct scatterlist *sg;
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ret = videobuf_iolock(vq, vb, NULL);
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if (pcdev->channels == 3) {
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size_u = size_v = size / 4;
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/* init DMA for Y channel */
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ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
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dev_err(dev, "DMA initialization for Y/RGB failed\n");
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/* init DMA for U channel */
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ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
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size_u, &sg, &next_ofs);
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dev_err(dev, "DMA initialization for U failed\n");
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/* init DMA for V channel */
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ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
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size_v, &sg, &next_ofs);
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dev_err(dev, "DMA initialization for V failed\n");
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vb->state = VIDEOBUF_PREPARED;
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pxa_videobuf_set_actdma(pcdev, buf);
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dma_free_coherent(dev, buf->dmas[1].sg_size,
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buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
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dma_free_coherent(dev, buf->dmas[0].sg_size,
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buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
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free_buffer(vq, buf);
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* pxa_dma_start_channels - start DMA channel for active buffer
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* @pcdev: pxa camera device
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* Initialize DMA channels to the beginning of the active video buffer, and
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* start these channels.
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static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
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struct pxa_buffer *active;
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active = pcdev->active;
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for (i = 0; i < pcdev->channels; i++) {
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dev_dbg(pcdev->soc_host.v4l2_dev.dev,
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"%s (channel=%d) ddadr=%08x\n", __func__,
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i, active->dmas[i].sg_dma);
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DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
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DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
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static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
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for (i = 0; i < pcdev->channels; i++) {
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dev_dbg(pcdev->soc_host.v4l2_dev.dev,
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"%s (channel=%d)\n", __func__, i);
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DCSR(pcdev->dma_chans[i]) = 0;
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static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
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struct pxa_buffer *buf)
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struct pxa_dma_desc *buf_last_desc;
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for (i = 0; i < pcdev->channels; i++) {
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buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
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buf_last_desc->ddadr = DDADR_STOP;
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if (pcdev->sg_tail[i])
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/* Link the new buffer to the old tail */
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pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
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/* Update the channel tail */
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pcdev->sg_tail[i] = buf_last_desc;
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* pxa_camera_start_capture - start video capturing
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* @pcdev: camera device
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* Launch capturing. DMA channels should not be active yet. They should get
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* activated at the end of frame interrupt, to capture only whole frames, and
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* never begin the capture of a partial frame.
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static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
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dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
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/* Enable End-Of-Frame Interrupt */
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cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
617
cicr0 &= ~CICR0_EOFM;
618
__raw_writel(cicr0, pcdev->base + CICR0);
621
static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
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pxa_dma_stop_channels(pcdev);
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cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
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__raw_writel(cicr0, pcdev->base + CICR0);
630
pcdev->active = NULL;
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dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
634
/* Called under spinlock_irqsave(&pcdev->lock, ...) */
635
static void pxa_videobuf_queue(struct videobuf_queue *vq,
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struct videobuf_buffer *vb)
638
struct soc_camera_device *icd = vq->priv_data;
639
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
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struct pxa_camera_dev *pcdev = ici->priv;
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
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__func__, vb, vb->baddr, vb->bsize, pcdev->active);
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list_add_tail(&vb->queue, &pcdev->capture);
648
vb->state = VIDEOBUF_ACTIVE;
649
pxa_dma_add_tail_buf(pcdev, buf);
652
pxa_camera_start_capture(pcdev);
655
static void pxa_videobuf_release(struct videobuf_queue *vq,
656
struct videobuf_buffer *vb)
658
struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
660
struct soc_camera_device *icd = vq->priv_data;
661
struct device *dev = icd->parent;
663
dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
664
vb, vb->baddr, vb->bsize);
667
case VIDEOBUF_ACTIVE:
668
dev_dbg(dev, "%s (active)\n", __func__);
670
case VIDEOBUF_QUEUED:
671
dev_dbg(dev, "%s (queued)\n", __func__);
673
case VIDEOBUF_PREPARED:
674
dev_dbg(dev, "%s (prepared)\n", __func__);
677
dev_dbg(dev, "%s (unknown)\n", __func__);
682
free_buffer(vq, buf);
685
static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
686
struct videobuf_buffer *vb,
687
struct pxa_buffer *buf)
691
/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
692
list_del_init(&vb->queue);
693
vb->state = VIDEOBUF_DONE;
694
do_gettimeofday(&vb->ts);
697
dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
700
if (list_empty(&pcdev->capture)) {
701
pxa_camera_stop_capture(pcdev);
702
for (i = 0; i < pcdev->channels; i++)
703
pcdev->sg_tail[i] = NULL;
707
pcdev->active = list_entry(pcdev->capture.next,
708
struct pxa_buffer, vb.queue);
712
* pxa_camera_check_link_miss - check missed DMA linking
713
* @pcdev: camera device
715
* The DMA chaining is done with DMA running. This means a tiny temporal window
716
* remains, where a buffer is queued on the chain, while the chain is already
717
* stopped. This means the tailed buffer would never be transferred by DMA.
718
* This function restarts the capture for this corner case, where :
719
* - DADR() == DADDR_STOP
720
* - a videobuffer is queued on the pcdev->capture list
722
* Please check the "DMA hot chaining timeslice issue" in
723
* Documentation/video4linux/pxa_camera.txt
725
* Context: should only be called within the dma irq handler
727
static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
729
int i, is_dma_stopped = 1;
731
for (i = 0; i < pcdev->channels; i++)
732
if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
734
dev_dbg(pcdev->soc_host.v4l2_dev.dev,
735
"%s : top queued buffer=%p, dma_stopped=%d\n",
736
__func__, pcdev->active, is_dma_stopped);
737
if (pcdev->active && is_dma_stopped)
738
pxa_camera_start_capture(pcdev);
741
static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
742
enum pxa_camera_active_dma act_dma)
744
struct device *dev = pcdev->soc_host.v4l2_dev.dev;
745
struct pxa_buffer *buf;
747
u32 status, camera_status, overrun;
748
struct videobuf_buffer *vb;
750
spin_lock_irqsave(&pcdev->lock, flags);
752
status = DCSR(channel);
753
DCSR(channel) = status;
755
camera_status = __raw_readl(pcdev->base + CISR);
756
overrun = CISR_IFO_0;
757
if (pcdev->channels == 3)
758
overrun |= CISR_IFO_1 | CISR_IFO_2;
760
if (status & DCSR_BUSERR) {
761
dev_err(dev, "DMA Bus Error IRQ!\n");
765
if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
766
dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
772
* pcdev->active should not be NULL in DMA irq handler.
774
* But there is one corner case : if capture was stopped due to an
775
* overrun of channel 1, and at that same channel 2 was completed.
777
* When handling the overrun in DMA irq for channel 1, we'll stop the
778
* capture and restart it (and thus set pcdev->active to NULL). But the
779
* DMA irq handler will already be pending for channel 2. So on entering
780
* the DMA irq handler for channel 2 there will be no active buffer, yet
786
vb = &pcdev->active->vb;
787
buf = container_of(vb, struct pxa_buffer, vb);
788
WARN_ON(buf->inwork || list_empty(&vb->queue));
790
dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
791
__func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
792
status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
794
if (status & DCSR_ENDINTR) {
796
* It's normal if the last frame creates an overrun, as there
797
* are no more DMA descriptors to fetch from QCI fifos
799
if (camera_status & overrun &&
800
!list_is_last(pcdev->capture.next, &pcdev->capture)) {
801
dev_dbg(dev, "FIFO overrun! CISR: %x\n",
803
pxa_camera_stop_capture(pcdev);
804
pxa_camera_start_capture(pcdev);
807
buf->active_dma &= ~act_dma;
808
if (!buf->active_dma) {
809
pxa_camera_wakeup(pcdev, vb, buf);
810
pxa_camera_check_link_miss(pcdev);
815
spin_unlock_irqrestore(&pcdev->lock, flags);
818
static void pxa_camera_dma_irq_y(int channel, void *data)
820
struct pxa_camera_dev *pcdev = data;
821
pxa_camera_dma_irq(channel, pcdev, DMA_Y);
824
static void pxa_camera_dma_irq_u(int channel, void *data)
826
struct pxa_camera_dev *pcdev = data;
827
pxa_camera_dma_irq(channel, pcdev, DMA_U);
830
static void pxa_camera_dma_irq_v(int channel, void *data)
832
struct pxa_camera_dev *pcdev = data;
833
pxa_camera_dma_irq(channel, pcdev, DMA_V);
836
static struct videobuf_queue_ops pxa_videobuf_ops = {
837
.buf_setup = pxa_videobuf_setup,
838
.buf_prepare = pxa_videobuf_prepare,
839
.buf_queue = pxa_videobuf_queue,
840
.buf_release = pxa_videobuf_release,
843
static void pxa_camera_init_videobuf(struct videobuf_queue *q,
844
struct soc_camera_device *icd)
846
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
847
struct pxa_camera_dev *pcdev = ici->priv;
850
* We must pass NULL as dev pointer, then all pci_* dma operations
851
* transform to normal dma_* ones.
853
videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
854
V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
855
sizeof(struct pxa_buffer), icd, &icd->video_lock);
858
static u32 mclk_get_divisor(struct platform_device *pdev,
859
struct pxa_camera_dev *pcdev)
861
unsigned long mclk = pcdev->mclk;
862
struct device *dev = &pdev->dev;
864
unsigned long lcdclk;
866
lcdclk = clk_get_rate(pcdev->clk);
867
pcdev->ciclk = lcdclk;
869
/* mclk <= ciclk / 4 (27.4.2) */
870
if (mclk > lcdclk / 4) {
872
dev_warn(dev, "Limiting master clock to %lu\n", mclk);
875
/* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
876
div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
878
/* If we're not supplying MCLK, leave it at 0 */
879
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
880
pcdev->mclk = lcdclk / (2 * (div + 1));
882
dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
888
static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
891
/* We want a timeout > 1 pixel time, not ">=" */
892
u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
894
__raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
897
static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
901
/* disable all interrupts */
902
__raw_writel(0x3ff, pcdev->base + CICR0);
904
if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
905
cicr4 |= CICR4_PCLK_EN;
906
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
907
cicr4 |= CICR4_MCLK_EN;
908
if (pcdev->platform_flags & PXA_CAMERA_PCP)
910
if (pcdev->platform_flags & PXA_CAMERA_HSP)
912
if (pcdev->platform_flags & PXA_CAMERA_VSP)
915
__raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
917
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
918
/* Initialise the timeout under the assumption pclk = mclk */
919
recalculate_fifo_timeout(pcdev, pcdev->mclk);
921
/* "Safe default" - 13MHz */
922
recalculate_fifo_timeout(pcdev, 13000000);
924
clk_enable(pcdev->clk);
927
static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
929
clk_disable(pcdev->clk);
932
static irqreturn_t pxa_camera_irq(int irq, void *data)
934
struct pxa_camera_dev *pcdev = data;
935
unsigned long status, cifr, cicr0;
936
struct pxa_buffer *buf;
937
struct videobuf_buffer *vb;
939
status = __raw_readl(pcdev->base + CISR);
940
dev_dbg(pcdev->soc_host.v4l2_dev.dev,
941
"Camera interrupt status 0x%lx\n", status);
946
__raw_writel(status, pcdev->base + CISR);
948
if (status & CISR_EOF) {
949
/* Reset the FIFOs */
950
cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
951
__raw_writel(cifr, pcdev->base + CIFR);
953
pcdev->active = list_first_entry(&pcdev->capture,
954
struct pxa_buffer, vb.queue);
955
vb = &pcdev->active->vb;
956
buf = container_of(vb, struct pxa_buffer, vb);
957
pxa_videobuf_set_actdma(pcdev, buf);
959
pxa_dma_start_channels(pcdev);
961
cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
962
__raw_writel(cicr0, pcdev->base + CICR0);
969
* The following two functions absolutely depend on the fact, that
970
* there can be only one camera on PXA quick capture interface
971
* Called with .video_lock held
973
static int pxa_camera_add_device(struct soc_camera_device *icd)
975
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
976
struct pxa_camera_dev *pcdev = ici->priv;
981
pxa_camera_activate(pcdev);
985
dev_info(icd->parent, "PXA Camera driver attached to camera %d\n",
991
/* Called with .video_lock held */
992
static void pxa_camera_remove_device(struct soc_camera_device *icd)
994
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
995
struct pxa_camera_dev *pcdev = ici->priv;
997
BUG_ON(icd != pcdev->icd);
999
dev_info(icd->parent, "PXA Camera driver detached from camera %d\n",
1002
/* disable capture, disable interrupts */
1003
__raw_writel(0x3ff, pcdev->base + CICR0);
1005
/* Stop DMA engine */
1006
DCSR(pcdev->dma_chans[0]) = 0;
1007
DCSR(pcdev->dma_chans[1]) = 0;
1008
DCSR(pcdev->dma_chans[2]) = 0;
1010
pxa_camera_deactivate(pcdev);
1015
static int test_platform_param(struct pxa_camera_dev *pcdev,
1016
unsigned char buswidth, unsigned long *flags)
1019
* Platform specified synchronization and pixel clock polarities are
1020
* only a recommendation and are only used during probing. The PXA270
1021
* quick capture interface supports both.
1023
*flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1024
V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1025
V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1026
V4L2_MBUS_HSYNC_ACTIVE_LOW |
1027
V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1028
V4L2_MBUS_VSYNC_ACTIVE_LOW |
1029
V4L2_MBUS_DATA_ACTIVE_HIGH |
1030
V4L2_MBUS_PCLK_SAMPLE_RISING |
1031
V4L2_MBUS_PCLK_SAMPLE_FALLING;
1033
/* If requested data width is supported by the platform, use it */
1034
if ((1 << (buswidth - 1)) & pcdev->width_flags)
1040
static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1041
unsigned long flags, __u32 pixfmt)
1043
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1044
struct pxa_camera_dev *pcdev = ici->priv;
1045
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1046
unsigned long dw, bpp;
1047
u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1048
int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
1054
* Datawidth is now guaranteed to be equal to one of the three values.
1055
* We fix bit-per-pixel equal to data-width...
1057
switch (icd->current_fmt->host_fmt->bits_per_sample) {
1068
* Actually it can only be 8 now,
1069
* default is just to silence compiler warnings
1076
if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1077
cicr4 |= CICR4_PCLK_EN;
1078
if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1079
cicr4 |= CICR4_MCLK_EN;
1080
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1082
if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1084
if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1087
cicr0 = __raw_readl(pcdev->base + CICR0);
1088
if (cicr0 & CICR0_ENB)
1089
__raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1091
cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1094
case V4L2_PIX_FMT_YUV422P:
1095
pcdev->channels = 3;
1096
cicr1 |= CICR1_YCBCR_F;
1098
* Normally, pxa bus wants as input UYVY format. We allow all
1099
* reorderings of the YUV422 format, as no processing is done,
1100
* and the YUV stream is just passed through without any
1101
* transformation. Note that UYVY is the only format that
1102
* should be used if pxa framebuffer Overlay2 is used.
1104
case V4L2_PIX_FMT_UYVY:
1105
case V4L2_PIX_FMT_VYUY:
1106
case V4L2_PIX_FMT_YUYV:
1107
case V4L2_PIX_FMT_YVYU:
1108
cicr1 |= CICR1_COLOR_SP_VAL(2);
1110
case V4L2_PIX_FMT_RGB555:
1111
cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1112
CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1114
case V4L2_PIX_FMT_RGB565:
1115
cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1120
cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1121
CICR3_BFW_VAL(min((u32)255, y_skip_top));
1122
cicr4 |= pcdev->mclk_divisor;
1124
__raw_writel(cicr1, pcdev->base + CICR1);
1125
__raw_writel(cicr2, pcdev->base + CICR2);
1126
__raw_writel(cicr3, pcdev->base + CICR3);
1127
__raw_writel(cicr4, pcdev->base + CICR4);
1129
/* CIF interrupts are not used, only DMA */
1130
cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1131
CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1132
cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1133
__raw_writel(cicr0, pcdev->base + CICR0);
1136
static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1138
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1139
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1140
struct pxa_camera_dev *pcdev = ici->priv;
1141
struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1142
unsigned long bus_flags, common_flags;
1144
struct pxa_cam *cam = icd->host_priv;
1146
ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
1151
ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1153
common_flags = soc_mbus_config_compatible(&cfg,
1155
if (!common_flags) {
1156
dev_warn(icd->parent,
1157
"Flags incompatible: camera 0x%x, host 0x%lx\n",
1158
cfg.flags, bus_flags);
1161
} else if (ret != -ENOIOCTLCMD) {
1164
common_flags = bus_flags;
1167
pcdev->channels = 1;
1169
/* Make choises, based on platform preferences */
1170
if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1171
(common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1172
if (pcdev->platform_flags & PXA_CAMERA_HSP)
1173
common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1175
common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1178
if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1179
(common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1180
if (pcdev->platform_flags & PXA_CAMERA_VSP)
1181
common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1183
common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1186
if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1187
(common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1188
if (pcdev->platform_flags & PXA_CAMERA_PCP)
1189
common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1191
common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1194
cfg.flags = common_flags;
1195
ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1196
if (ret < 0 && ret != -ENOIOCTLCMD) {
1197
dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1202
cam->flags = common_flags;
1204
pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1209
static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1210
unsigned char buswidth)
1212
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1213
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1214
struct pxa_camera_dev *pcdev = ici->priv;
1215
struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1216
unsigned long bus_flags, common_flags;
1217
int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1222
ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1224
common_flags = soc_mbus_config_compatible(&cfg,
1226
if (!common_flags) {
1227
dev_warn(icd->parent,
1228
"Flags incompatible: camera 0x%x, host 0x%lx\n",
1229
cfg.flags, bus_flags);
1232
} else if (ret == -ENOIOCTLCMD) {
1239
static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1241
.fourcc = V4L2_PIX_FMT_YUV422P,
1242
.name = "Planar YUV422 16 bit",
1243
.bits_per_sample = 8,
1244
.packing = SOC_MBUS_PACKING_2X8_PADHI,
1245
.order = SOC_MBUS_ORDER_LE,
1249
/* This will be corrected as we get more formats */
1250
static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1252
return fmt->packing == SOC_MBUS_PACKING_NONE ||
1253
(fmt->bits_per_sample == 8 &&
1254
fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1255
(fmt->bits_per_sample > 8 &&
1256
fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1259
static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
1260
struct soc_camera_format_xlate *xlate)
1262
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1263
struct device *dev = icd->parent;
1264
int formats = 0, ret;
1265
struct pxa_cam *cam;
1266
enum v4l2_mbus_pixelcode code;
1267
const struct soc_mbus_pixelfmt *fmt;
1269
ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1271
/* No more formats */
1274
fmt = soc_mbus_get_fmtdesc(code);
1276
dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1280
/* This also checks support for the requested bits-per-sample */
1281
ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1285
if (!icd->host_priv) {
1286
cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1290
icd->host_priv = cam;
1292
cam = icd->host_priv;
1296
case V4L2_MBUS_FMT_UYVY8_2X8:
1299
xlate->host_fmt = &pxa_camera_formats[0];
1302
dev_dbg(dev, "Providing format %s using code %d\n",
1303
pxa_camera_formats[0].name, code);
1305
case V4L2_MBUS_FMT_VYUY8_2X8:
1306
case V4L2_MBUS_FMT_YUYV8_2X8:
1307
case V4L2_MBUS_FMT_YVYU8_2X8:
1308
case V4L2_MBUS_FMT_RGB565_2X8_LE:
1309
case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
1311
dev_dbg(dev, "Providing format %s packed\n",
1315
if (!pxa_camera_packing_supported(fmt))
1319
"Providing format %s in pass-through mode\n",
1323
/* Generic pass-through */
1326
xlate->host_fmt = fmt;
1334
static void pxa_camera_put_formats(struct soc_camera_device *icd)
1336
kfree(icd->host_priv);
1337
icd->host_priv = NULL;
1340
static int pxa_camera_check_frame(u32 width, u32 height)
1342
/* limit to pxa hardware capabilities */
1343
return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1347
static int pxa_camera_set_crop(struct soc_camera_device *icd,
1348
struct v4l2_crop *a)
1350
struct v4l2_rect *rect = &a->c;
1351
struct device *dev = icd->parent;
1352
struct soc_camera_host *ici = to_soc_camera_host(dev);
1353
struct pxa_camera_dev *pcdev = ici->priv;
1354
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1355
struct soc_camera_sense sense = {
1356
.master_clock = pcdev->mclk,
1357
.pixel_clock_max = pcdev->ciclk / 4,
1359
struct v4l2_mbus_framefmt mf;
1360
struct pxa_cam *cam = icd->host_priv;
1361
u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1364
/* If PCLK is used to latch data from the sensor, check sense */
1365
if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1366
icd->sense = &sense;
1368
ret = v4l2_subdev_call(sd, video, s_crop, a);
1373
dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1374
rect->width, rect->height, rect->left, rect->top);
1378
ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1382
if (pxa_camera_check_frame(mf.width, mf.height)) {
1384
* Camera cropping produced a frame beyond our capabilities.
1385
* FIXME: just extract a subframe, that we can process.
1387
v4l_bound_align_image(&mf.width, 48, 2048, 1,
1388
&mf.height, 32, 2048, 0,
1389
fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1390
ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1394
if (pxa_camera_check_frame(mf.width, mf.height)) {
1395
dev_warn(icd->parent,
1396
"Inconsistent state. Use S_FMT to repair\n");
1401
if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1402
if (sense.pixel_clock > sense.pixel_clock_max) {
1404
"pixel clock %lu set by the camera too high!",
1408
recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1411
icd->user_width = mf.width;
1412
icd->user_height = mf.height;
1414
pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1419
static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1420
struct v4l2_format *f)
1422
struct device *dev = icd->parent;
1423
struct soc_camera_host *ici = to_soc_camera_host(dev);
1424
struct pxa_camera_dev *pcdev = ici->priv;
1425
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1426
const struct soc_camera_format_xlate *xlate = NULL;
1427
struct soc_camera_sense sense = {
1428
.master_clock = pcdev->mclk,
1429
.pixel_clock_max = pcdev->ciclk / 4,
1431
struct v4l2_pix_format *pix = &f->fmt.pix;
1432
struct v4l2_mbus_framefmt mf;
1435
xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1437
dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1441
/* If PCLK is used to latch data from the sensor, check sense */
1442
if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1443
/* The caller holds a mutex. */
1444
icd->sense = &sense;
1446
mf.width = pix->width;
1447
mf.height = pix->height;
1448
mf.field = pix->field;
1449
mf.colorspace = pix->colorspace;
1450
mf.code = xlate->code;
1452
ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1454
if (mf.code != xlate->code)
1460
dev_warn(dev, "Failed to configure for format %x\n",
1462
} else if (pxa_camera_check_frame(mf.width, mf.height)) {
1464
"Camera driver produced an unsupported frame %dx%d\n",
1465
mf.width, mf.height);
1467
} else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1468
if (sense.pixel_clock > sense.pixel_clock_max) {
1470
"pixel clock %lu set by the camera too high!",
1474
recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1480
pix->width = mf.width;
1481
pix->height = mf.height;
1482
pix->field = mf.field;
1483
pix->colorspace = mf.colorspace;
1484
icd->current_fmt = xlate;
1489
static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1490
struct v4l2_format *f)
1492
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1493
const struct soc_camera_format_xlate *xlate;
1494
struct v4l2_pix_format *pix = &f->fmt.pix;
1495
struct v4l2_mbus_framefmt mf;
1496
__u32 pixfmt = pix->pixelformat;
1499
xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1501
dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1506
* Limit to pxa hardware capabilities. YUV422P planar format requires
1507
* images size to be a multiple of 16 bytes. If not, zeros will be
1508
* inserted between Y and U planes, and U and V planes, which violates
1509
* the YUV422P standard.
1511
v4l_bound_align_image(&pix->width, 48, 2048, 1,
1512
&pix->height, 32, 2048, 0,
1513
pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1515
/* limit to sensor capabilities */
1516
mf.width = pix->width;
1517
mf.height = pix->height;
1518
/* Only progressive video supported so far */
1519
mf.field = V4L2_FIELD_NONE;
1520
mf.colorspace = pix->colorspace;
1521
mf.code = xlate->code;
1523
ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1527
pix->width = mf.width;
1528
pix->height = mf.height;
1529
pix->colorspace = mf.colorspace;
1532
case V4L2_FIELD_ANY:
1533
case V4L2_FIELD_NONE:
1534
pix->field = V4L2_FIELD_NONE;
1537
/* TODO: support interlaced at least in pass-through mode */
1538
dev_err(icd->parent, "Field type %d unsupported.\n",
1546
static int pxa_camera_reqbufs(struct soc_camera_device *icd,
1547
struct v4l2_requestbuffers *p)
1552
* This is for locking debugging only. I removed spinlocks and now I
1553
* check whether .prepare is ever called on a linked buffer, or whether
1554
* a dma IRQ can occur for an in-work or unlinked buffer. Until now
1555
* it hadn't triggered
1557
for (i = 0; i < p->count; i++) {
1558
struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1559
struct pxa_buffer, vb);
1561
INIT_LIST_HEAD(&buf->vb.queue);
1567
static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1569
struct soc_camera_device *icd = file->private_data;
1570
struct pxa_buffer *buf;
1572
buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer,
1575
poll_wait(file, &buf->vb.done, pt);
1577
if (buf->vb.state == VIDEOBUF_DONE ||
1578
buf->vb.state == VIDEOBUF_ERROR)
1579
return POLLIN|POLLRDNORM;
1584
static int pxa_camera_querycap(struct soc_camera_host *ici,
1585
struct v4l2_capability *cap)
1587
/* cap->name is set by the firendly caller:-> */
1588
strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1589
cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1594
static int pxa_camera_suspend(struct device *dev)
1596
struct soc_camera_host *ici = to_soc_camera_host(dev);
1597
struct pxa_camera_dev *pcdev = ici->priv;
1600
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1601
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1602
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1603
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1604
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1607
struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd);
1608
ret = v4l2_subdev_call(sd, core, s_power, 0);
1609
if (ret == -ENOIOCTLCMD)
1616
static int pxa_camera_resume(struct device *dev)
1618
struct soc_camera_host *ici = to_soc_camera_host(dev);
1619
struct pxa_camera_dev *pcdev = ici->priv;
1622
DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1623
DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1624
DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1626
__raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1627
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1628
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1629
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1630
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1633
struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->icd);
1634
ret = v4l2_subdev_call(sd, core, s_power, 1);
1635
if (ret == -ENOIOCTLCMD)
1639
/* Restart frame capture if active buffer exists */
1640
if (!ret && pcdev->active)
1641
pxa_camera_start_capture(pcdev);
1646
static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1647
.owner = THIS_MODULE,
1648
.add = pxa_camera_add_device,
1649
.remove = pxa_camera_remove_device,
1650
.set_crop = pxa_camera_set_crop,
1651
.get_formats = pxa_camera_get_formats,
1652
.put_formats = pxa_camera_put_formats,
1653
.set_fmt = pxa_camera_set_fmt,
1654
.try_fmt = pxa_camera_try_fmt,
1655
.init_videobuf = pxa_camera_init_videobuf,
1656
.reqbufs = pxa_camera_reqbufs,
1657
.poll = pxa_camera_poll,
1658
.querycap = pxa_camera_querycap,
1659
.set_bus_param = pxa_camera_set_bus_param,
1662
static int __devinit pxa_camera_probe(struct platform_device *pdev)
1664
struct pxa_camera_dev *pcdev;
1665
struct resource *res;
1670
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1671
irq = platform_get_irq(pdev, 0);
1672
if (!res || irq < 0) {
1677
pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1679
dev_err(&pdev->dev, "Could not allocate pcdev\n");
1684
pcdev->clk = clk_get(&pdev->dev, NULL);
1685
if (IS_ERR(pcdev->clk)) {
1686
err = PTR_ERR(pcdev->clk);
1692
pcdev->pdata = pdev->dev.platform_data;
1693
pcdev->platform_flags = pcdev->pdata->flags;
1694
if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1695
PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1697
* Platform hasn't set available data widths. This is bad.
1698
* Warn and use a default.
1700
dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1701
"data widths, using default 10 bit\n");
1702
pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1704
if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
1705
pcdev->width_flags = 1 << 7;
1706
if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
1707
pcdev->width_flags |= 1 << 8;
1708
if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
1709
pcdev->width_flags |= 1 << 9;
1710
pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1712
dev_warn(&pdev->dev,
1713
"mclk == 0! Please, fix your platform data. "
1714
"Using default 20MHz\n");
1715
pcdev->mclk = 20000000;
1718
pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1720
INIT_LIST_HEAD(&pcdev->capture);
1721
spin_lock_init(&pcdev->lock);
1724
* Request the regions.
1726
if (!request_mem_region(res->start, resource_size(res),
1727
PXA_CAM_DRV_NAME)) {
1732
base = ioremap(res->start, resource_size(res));
1741
err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1742
pxa_camera_dma_irq_y, pcdev);
1744
dev_err(&pdev->dev, "Can't request DMA for Y\n");
1747
pcdev->dma_chans[0] = err;
1748
dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1750
err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1751
pxa_camera_dma_irq_u, pcdev);
1753
dev_err(&pdev->dev, "Can't request DMA for U\n");
1754
goto exit_free_dma_y;
1756
pcdev->dma_chans[1] = err;
1757
dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1759
err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1760
pxa_camera_dma_irq_v, pcdev);
1762
dev_err(&pdev->dev, "Can't request DMA for V\n");
1763
goto exit_free_dma_u;
1765
pcdev->dma_chans[2] = err;
1766
dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1768
DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1769
DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1770
DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1773
err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1776
dev_err(&pdev->dev, "Camera interrupt register failed \n");
1780
pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1781
pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1782
pcdev->soc_host.priv = pcdev;
1783
pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1784
pcdev->soc_host.nr = pdev->id;
1786
err = soc_camera_host_register(&pcdev->soc_host);
1793
free_irq(pcdev->irq, pcdev);
1795
pxa_free_dma(pcdev->dma_chans[2]);
1797
pxa_free_dma(pcdev->dma_chans[1]);
1799
pxa_free_dma(pcdev->dma_chans[0]);
1803
release_mem_region(res->start, resource_size(res));
1805
clk_put(pcdev->clk);
1812
static int __devexit pxa_camera_remove(struct platform_device *pdev)
1814
struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1815
struct pxa_camera_dev *pcdev = container_of(soc_host,
1816
struct pxa_camera_dev, soc_host);
1817
struct resource *res;
1819
clk_put(pcdev->clk);
1821
pxa_free_dma(pcdev->dma_chans[0]);
1822
pxa_free_dma(pcdev->dma_chans[1]);
1823
pxa_free_dma(pcdev->dma_chans[2]);
1824
free_irq(pcdev->irq, pcdev);
1826
soc_camera_host_unregister(soc_host);
1828
iounmap(pcdev->base);
1831
release_mem_region(res->start, resource_size(res));
1835
dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1840
static struct dev_pm_ops pxa_camera_pm = {
1841
.suspend = pxa_camera_suspend,
1842
.resume = pxa_camera_resume,
1845
static struct platform_driver pxa_camera_driver = {
1847
.name = PXA_CAM_DRV_NAME,
1848
.pm = &pxa_camera_pm,
1850
.probe = pxa_camera_probe,
1851
.remove = __devexit_p(pxa_camera_remove),
1855
static int __init pxa_camera_init(void)
1857
return platform_driver_register(&pxa_camera_driver);
1860
static void __exit pxa_camera_exit(void)
1862
platform_driver_unregister(&pxa_camera_driver);
1865
module_init(pxa_camera_init);
1866
module_exit(pxa_camera_exit);
1868
MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1869
MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1870
MODULE_LICENSE("GPL");
1871
MODULE_VERSION(PXA_CAM_VERSION);
1872
MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);