2
* Driver for PowerMac Z85c30 based ESCC cell found in the
3
* "macio" ASICs of various PowerMac models
5
* Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7
* Derived from drivers/macintosh/macserial.c by Paul Mackerras
8
* and drivers/serial/sunzilog.c by David S. Miller
10
* Hrm... actually, I ripped most of sunzilog (Thanks David !) and
11
* adapted special tweaks needed for us. I don't think it's worth
12
* merging back those though. The DMA code still has to get in
13
* and once done, I expect that driver to remain fairly stable in
14
* the long term, unless we change the driver model again...
16
* This program is free software; you can redistribute it and/or modify
17
* it under the terms of the GNU General Public License as published by
18
* the Free Software Foundation; either version 2 of the License, or
19
* (at your option) any later version.
21
* This program is distributed in the hope that it will be useful,
22
* but WITHOUT ANY WARRANTY; without even the implied warranty of
23
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24
* GNU General Public License for more details.
26
* You should have received a copy of the GNU General Public License
27
* along with this program; if not, write to the Free Software
28
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30
* 2004-08-06 Harald Welte <laforge@gnumonks.org>
31
* - Enable BREAK interrupt
32
* - Add support for sysreq
34
* TODO: - Add DMA support
35
* - Defer port shutdown to a few seconds after close
36
* - maybe put something right into uap->clk_divisor
41
#undef USE_CTRL_O_SYSRQ
43
#include <linux/module.h>
44
#include <linux/tty.h>
46
#include <linux/tty_flip.h>
47
#include <linux/major.h>
48
#include <linux/string.h>
49
#include <linux/fcntl.h>
51
#include <linux/kernel.h>
52
#include <linux/delay.h>
53
#include <linux/init.h>
54
#include <linux/console.h>
55
#include <linux/adb.h>
56
#include <linux/pmu.h>
57
#include <linux/bitops.h>
58
#include <linux/sysrq.h>
59
#include <linux/mutex.h>
60
#include <asm/sections.h>
64
#ifdef CONFIG_PPC_PMAC
66
#include <asm/machdep.h>
67
#include <asm/pmac_feature.h>
68
#include <asm/dbdma.h>
69
#include <asm/macio.h>
71
#include <linux/platform_device.h>
72
#define of_machine_is_compatible(x) (0)
75
#if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
79
#include <linux/serial.h>
80
#include <linux/serial_core.h>
82
#include "pmac_zilog.h"
84
/* Not yet implemented */
87
static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
88
MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
89
MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
90
MODULE_LICENSE("GPL");
92
#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
93
#define PMACZILOG_MAJOR TTY_MAJOR
94
#define PMACZILOG_MINOR 64
95
#define PMACZILOG_NAME "ttyS"
97
#define PMACZILOG_MAJOR 204
98
#define PMACZILOG_MINOR 192
99
#define PMACZILOG_NAME "ttyPZ"
104
* For the sake of early serial console, we can do a pre-probe
105
* (optional) of the ports at rather early boot time.
107
static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
108
static int pmz_ports_count;
109
static DEFINE_MUTEX(pmz_irq_mutex);
111
static struct uart_driver pmz_uart_reg = {
112
.owner = THIS_MODULE,
113
.driver_name = PMACZILOG_NAME,
114
.dev_name = PMACZILOG_NAME,
115
.major = PMACZILOG_MAJOR,
116
.minor = PMACZILOG_MINOR,
121
* Load all registers to reprogram the port
122
* This function must only be called when the TX is not busy. The UART
123
* port lock must be held and local interrupts disabled.
125
static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
129
if (ZS_IS_ASLEEP(uap))
132
/* Let pending transmits finish. */
133
for (i = 0; i < 1000; i++) {
134
unsigned char stat = read_zsreg(uap, R1);
146
/* Disable all interrupts. */
148
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
150
/* Set parity, sync config, stop bits, and clock divisor. */
151
write_zsreg(uap, R4, regs[R4]);
153
/* Set misc. TX/RX control bits. */
154
write_zsreg(uap, R10, regs[R10]);
156
/* Set TX/RX controls sans the enable bits. */
157
write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
158
write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
160
/* now set R7 "prime" on ESCC */
161
write_zsreg(uap, R15, regs[R15] | EN85C30);
162
write_zsreg(uap, R7, regs[R7P]);
164
/* make sure we use R7 "non-prime" on ESCC */
165
write_zsreg(uap, R15, regs[R15] & ~EN85C30);
167
/* Synchronous mode config. */
168
write_zsreg(uap, R6, regs[R6]);
169
write_zsreg(uap, R7, regs[R7]);
171
/* Disable baud generator. */
172
write_zsreg(uap, R14, regs[R14] & ~BRENAB);
174
/* Clock mode control. */
175
write_zsreg(uap, R11, regs[R11]);
177
/* Lower and upper byte of baud rate generator divisor. */
178
write_zsreg(uap, R12, regs[R12]);
179
write_zsreg(uap, R13, regs[R13]);
181
/* Now rewrite R14, with BRENAB (if set). */
182
write_zsreg(uap, R14, regs[R14]);
184
/* Reset external status interrupts. */
185
write_zsreg(uap, R0, RES_EXT_INT);
186
write_zsreg(uap, R0, RES_EXT_INT);
188
/* Rewrite R3/R5, this time without enables masked. */
189
write_zsreg(uap, R3, regs[R3]);
190
write_zsreg(uap, R5, regs[R5]);
192
/* Rewrite R1, this time without IRQ enabled masked. */
193
write_zsreg(uap, R1, regs[R1]);
195
/* Enable interrupts */
196
write_zsreg(uap, R9, regs[R9]);
200
* We do like sunzilog to avoid disrupting pending Tx
201
* Reprogram the Zilog channel HW registers with the copies found in the
202
* software state struct. If the transmitter is busy, we defer this update
203
* until the next TX complete interrupt. Else, we do it right now.
205
* The UART port lock must be held and local interrupts disabled.
207
static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
209
if (!ZS_REGS_HELD(uap)) {
210
if (ZS_TX_ACTIVE(uap)) {
211
uap->flags |= PMACZILOG_FLAG_REGS_HELD;
213
pmz_debug("pmz: maybe_update_regs: updating\n");
214
pmz_load_zsregs(uap, uap->curregs);
219
static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
221
struct tty_struct *tty = NULL;
222
unsigned char ch, r1, drop, error, flag;
225
/* The interrupt can be enabled when the port isn't open, typically
226
* that happens when using one port is open and the other closed (stale
227
* interrupt) or when one port is used as a console.
229
if (!ZS_IS_OPEN(uap)) {
230
pmz_debug("pmz: draining input\n");
231
/* Port is closed, drain input data */
233
if ((++loops) > 1000)
235
(void)read_zsreg(uap, R1);
236
write_zsreg(uap, R0, ERR_RES);
237
(void)read_zsdata(uap);
238
ch = read_zsreg(uap, R0);
239
if (!(ch & Rx_CH_AV))
245
/* Sanity check, make sure the old bug is no longer happening */
246
if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
248
(void)read_zsdata(uap);
251
tty = uap->port.state->port.tty;
257
r1 = read_zsreg(uap, R1);
258
ch = read_zsdata(uap);
260
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
261
write_zsreg(uap, R0, ERR_RES);
265
ch &= uap->parity_mask;
266
if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
267
uap->flags &= ~PMACZILOG_FLAG_BREAK;
270
#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
271
#ifdef USE_CTRL_O_SYSRQ
272
/* Handle the SysRq ^O Hack */
274
uap->port.sysrq = jiffies + HZ*5;
277
#endif /* USE_CTRL_O_SYSRQ */
278
if (uap->port.sysrq) {
280
spin_unlock(&uap->port.lock);
281
swallow = uart_handle_sysrq_char(&uap->port, ch);
282
spin_lock(&uap->port.lock);
286
#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
288
/* A real serial line, record the character and status. */
293
uap->port.icount.rx++;
295
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
298
pmz_debug("pmz: got break !\n");
299
r1 &= ~(PAR_ERR | CRC_ERR);
300
uap->port.icount.brk++;
301
if (uart_handle_break(&uap->port))
304
else if (r1 & PAR_ERR)
305
uap->port.icount.parity++;
306
else if (r1 & CRC_ERR)
307
uap->port.icount.frame++;
309
uap->port.icount.overrun++;
310
r1 &= uap->port.read_status_mask;
313
else if (r1 & PAR_ERR)
315
else if (r1 & CRC_ERR)
319
if (uap->port.ignore_status_mask == 0xff ||
320
(r1 & uap->port.ignore_status_mask) == 0) {
321
tty_insert_flip_char(tty, ch, flag);
324
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
326
/* We can get stuck in an infinite loop getting char 0 when the
327
* line is in a wrong HW state, we break that here.
328
* When that happens, I disable the receive side of the driver.
329
* Note that what I've been experiencing is a real irq loop where
330
* I'm getting flooded regardless of the actual port speed.
331
* Something strange is going on with the HW
333
if ((++loops) > 1000)
335
ch = read_zsreg(uap, R0);
336
if (!(ch & Rx_CH_AV))
342
uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
343
write_zsreg(uap, R1, uap->curregs[R1]);
345
pmz_error("pmz: rx irq flood !\n");
349
static void pmz_status_handle(struct uart_pmac_port *uap)
351
unsigned char status;
353
status = read_zsreg(uap, R0);
354
write_zsreg(uap, R0, RES_EXT_INT);
357
if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
358
if (status & SYNC_HUNT)
359
uap->port.icount.dsr++;
361
/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
362
* But it does not tell us which bit has changed, we have to keep
363
* track of this ourselves.
364
* The CTS input is inverted for some reason. -- paulus
366
if ((status ^ uap->prev_status) & DCD)
367
uart_handle_dcd_change(&uap->port,
369
if ((status ^ uap->prev_status) & CTS)
370
uart_handle_cts_change(&uap->port,
373
wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
376
if (status & BRK_ABRT)
377
uap->flags |= PMACZILOG_FLAG_BREAK;
379
uap->prev_status = status;
382
static void pmz_transmit_chars(struct uart_pmac_port *uap)
384
struct circ_buf *xmit;
386
if (ZS_IS_ASLEEP(uap))
388
if (ZS_IS_CONS(uap)) {
389
unsigned char status = read_zsreg(uap, R0);
391
/* TX still busy? Just wait for the next TX done interrupt.
393
* It can occur because of how we do serial console writes. It would
394
* be nice to transmit console writes just like we normally would for
395
* a TTY line. (ie. buffered and TX interrupt driven). That is not
396
* easy because console writes cannot sleep. One solution might be
397
* to poll on enough port->xmit space becoming free. -DaveM
399
if (!(status & Tx_BUF_EMP))
403
uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
405
if (ZS_REGS_HELD(uap)) {
406
pmz_load_zsregs(uap, uap->curregs);
407
uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
410
if (ZS_TX_STOPPED(uap)) {
411
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
415
/* Under some circumstances, we see interrupts reported for
416
* a closed channel. The interrupt mask in R1 is clear, but
417
* R3 still signals the interrupts and we see them when taking
418
* an interrupt for the other channel (this could be a qemu
419
* bug but since the ESCC doc doesn't specify precsiely whether
420
* R3 interrup status bits are masked by R1 interrupt enable
421
* bits, better safe than sorry). --BenH.
423
if (!ZS_IS_OPEN(uap))
426
if (uap->port.x_char) {
427
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
428
write_zsdata(uap, uap->port.x_char);
430
uap->port.icount.tx++;
431
uap->port.x_char = 0;
435
if (uap->port.state == NULL)
437
xmit = &uap->port.state->xmit;
438
if (uart_circ_empty(xmit)) {
439
uart_write_wakeup(&uap->port);
442
if (uart_tx_stopped(&uap->port))
445
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
446
write_zsdata(uap, xmit->buf[xmit->tail]);
449
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
450
uap->port.icount.tx++;
452
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
453
uart_write_wakeup(&uap->port);
458
write_zsreg(uap, R0, RES_Tx_P);
462
/* Hrm... we register that twice, fixme later.... */
463
static irqreturn_t pmz_interrupt(int irq, void *dev_id)
465
struct uart_pmac_port *uap = dev_id;
466
struct uart_pmac_port *uap_a;
467
struct uart_pmac_port *uap_b;
469
struct tty_struct *tty;
472
uap_a = pmz_get_port_A(uap);
475
spin_lock(&uap_a->port.lock);
476
r3 = read_zsreg(uap_a, R3);
479
pmz_debug("irq, r3: %x\n", r3);
483
if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
484
write_zsreg(uap_a, R0, RES_H_IUS);
487
pmz_status_handle(uap_a);
489
tty = pmz_receive_chars(uap_a);
491
pmz_transmit_chars(uap_a);
494
spin_unlock(&uap_a->port.lock);
496
tty_flip_buffer_push(tty);
498
if (uap_b->node == NULL)
501
spin_lock(&uap_b->port.lock);
503
if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
504
write_zsreg(uap_b, R0, RES_H_IUS);
507
pmz_status_handle(uap_b);
509
tty = pmz_receive_chars(uap_b);
511
pmz_transmit_chars(uap_b);
514
spin_unlock(&uap_b->port.lock);
516
tty_flip_buffer_push(tty);
520
pmz_debug("irq done.\n");
526
* Peek the status register, lock not held by caller
528
static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
533
spin_lock_irqsave(&uap->port.lock, flags);
534
status = read_zsreg(uap, R0);
535
spin_unlock_irqrestore(&uap->port.lock, flags);
541
* Check if transmitter is empty
542
* The port lock is not held.
544
static unsigned int pmz_tx_empty(struct uart_port *port)
546
struct uart_pmac_port *uap = to_pmz(port);
547
unsigned char status;
549
if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
552
status = pmz_peek_status(to_pmz(port));
553
if (status & Tx_BUF_EMP)
559
* Set Modem Control (RTS & DTR) bits
560
* The port lock is held and interrupts are disabled.
561
* Note: Shall we really filter out RTS on external ports or
562
* should that be dealt at higher level only ?
564
static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
566
struct uart_pmac_port *uap = to_pmz(port);
567
unsigned char set_bits, clear_bits;
569
/* Do nothing for irda for now... */
572
/* We get called during boot with a port not up yet */
573
if (ZS_IS_ASLEEP(uap) ||
574
!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
577
set_bits = clear_bits = 0;
579
if (ZS_IS_INTMODEM(uap)) {
580
if (mctrl & TIOCM_RTS)
585
if (mctrl & TIOCM_DTR)
590
/* NOTE: Not subject to 'transmitter active' rule. */
591
uap->curregs[R5] |= set_bits;
592
uap->curregs[R5] &= ~clear_bits;
593
if (ZS_IS_ASLEEP(uap))
595
write_zsreg(uap, R5, uap->curregs[R5]);
596
pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
597
set_bits, clear_bits, uap->curregs[R5]);
602
* Get Modem Control bits (only the input ones, the core will
603
* or that with a cached value of the control ones)
604
* The port lock is held and interrupts are disabled.
606
static unsigned int pmz_get_mctrl(struct uart_port *port)
608
struct uart_pmac_port *uap = to_pmz(port);
609
unsigned char status;
612
if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
615
status = read_zsreg(uap, R0);
620
if (status & SYNC_HUNT)
629
* Stop TX side. Dealt like sunzilog at next Tx interrupt,
630
* though for DMA, we will have to do a bit more.
631
* The port lock is held and interrupts are disabled.
633
static void pmz_stop_tx(struct uart_port *port)
635
to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
640
* The port lock is held and interrupts are disabled.
642
static void pmz_start_tx(struct uart_port *port)
644
struct uart_pmac_port *uap = to_pmz(port);
645
unsigned char status;
647
pmz_debug("pmz: start_tx()\n");
649
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
650
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
652
if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
655
status = read_zsreg(uap, R0);
657
/* TX busy? Just wait for the TX done interrupt. */
658
if (!(status & Tx_BUF_EMP))
661
/* Send the first character to jump-start the TX done
662
* IRQ sending engine.
665
write_zsdata(uap, port->x_char);
670
struct circ_buf *xmit = &port->state->xmit;
672
write_zsdata(uap, xmit->buf[xmit->tail]);
674
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
677
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
678
uart_write_wakeup(&uap->port);
680
pmz_debug("pmz: start_tx() done.\n");
684
* Stop Rx side, basically disable emitting of
685
* Rx interrupts on the port. We don't disable the rx
686
* side of the chip proper though
687
* The port lock is held.
689
static void pmz_stop_rx(struct uart_port *port)
691
struct uart_pmac_port *uap = to_pmz(port);
693
if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
696
pmz_debug("pmz: stop_rx()()\n");
698
/* Disable all RX interrupts. */
699
uap->curregs[R1] &= ~RxINT_MASK;
700
pmz_maybe_update_regs(uap);
702
pmz_debug("pmz: stop_rx() done.\n");
706
* Enable modem status change interrupts
707
* The port lock is held.
709
static void pmz_enable_ms(struct uart_port *port)
711
struct uart_pmac_port *uap = to_pmz(port);
712
unsigned char new_reg;
714
if (ZS_IS_IRDA(uap) || uap->node == NULL)
716
new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
717
if (new_reg != uap->curregs[R15]) {
718
uap->curregs[R15] = new_reg;
720
if (ZS_IS_ASLEEP(uap))
722
/* NOTE: Not subject to 'transmitter active' rule. */
723
write_zsreg(uap, R15, uap->curregs[R15]);
728
* Control break state emission
729
* The port lock is not held.
731
static void pmz_break_ctl(struct uart_port *port, int break_state)
733
struct uart_pmac_port *uap = to_pmz(port);
734
unsigned char set_bits, clear_bits, new_reg;
737
if (uap->node == NULL)
739
set_bits = clear_bits = 0;
744
clear_bits |= SND_BRK;
746
spin_lock_irqsave(&port->lock, flags);
748
new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
749
if (new_reg != uap->curregs[R5]) {
750
uap->curregs[R5] = new_reg;
752
/* NOTE: Not subject to 'transmitter active' rule. */
753
if (ZS_IS_ASLEEP(uap)) {
754
spin_unlock_irqrestore(&port->lock, flags);
757
write_zsreg(uap, R5, uap->curregs[R5]);
760
spin_unlock_irqrestore(&port->lock, flags);
763
#ifdef CONFIG_PPC_PMAC
766
* Turn power on or off to the SCC and associated stuff
767
* (port drivers, modem, IR port, etc.)
768
* Returns the number of milliseconds we should wait before
769
* trying to use the port.
771
static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
777
rc = pmac_call_feature(
778
PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
779
pmz_debug("port power on result: %d\n", rc);
780
if (ZS_IS_INTMODEM(uap)) {
781
rc = pmac_call_feature(
782
PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
783
delay = 2500; /* wait for 2.5s before using */
784
pmz_debug("modem power result: %d\n", rc);
787
/* TODO: Make that depend on a timer, don't power down
790
if (ZS_IS_INTMODEM(uap)) {
791
rc = pmac_call_feature(
792
PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
793
pmz_debug("port power off result: %d\n", rc);
795
pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
802
static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
807
#endif /* !CONFIG_PPC_PMAC */
810
* FixZeroBug....Works around a bug in the SCC receiving channel.
811
* Inspired from Darwin code, 15 Sept. 2000 -DanM
813
* The following sequence prevents a problem that is seen with O'Hare ASICs
814
* (most versions -- also with some Heathrow and Hydra ASICs) where a zero
815
* at the input to the receiver becomes 'stuck' and locks up the receiver.
816
* This problem can occur as a result of a zero bit at the receiver input
817
* coincident with any of the following events:
819
* The SCC is initialized (hardware or software).
820
* A framing error is detected.
821
* The clocking option changes from synchronous or X1 asynchronous
822
* clocking to X16, X32, or X64 asynchronous clocking.
823
* The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
825
* This workaround attempts to recover from the lockup condition by placing
826
* the SCC in synchronous loopback mode with a fast clock before programming
827
* any of the asynchronous modes.
829
static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
831
write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
834
write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
837
write_zsreg(uap, 4, X1CLK | MONSYNC);
838
write_zsreg(uap, 3, Rx8);
839
write_zsreg(uap, 5, Tx8 | RTS);
840
write_zsreg(uap, 9, NV); /* Didn't we already do this? */
841
write_zsreg(uap, 11, RCBR | TCBR);
842
write_zsreg(uap, 12, 0);
843
write_zsreg(uap, 13, 0);
844
write_zsreg(uap, 14, (LOOPBAK | BRSRC));
845
write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
846
write_zsreg(uap, 3, Rx8 | RxENABLE);
847
write_zsreg(uap, 0, RES_EXT_INT);
848
write_zsreg(uap, 0, RES_EXT_INT);
849
write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
851
/* The channel should be OK now, but it is probably receiving
853
* Switch to asynchronous mode, disable the receiver,
854
* and discard everything in the receive buffer.
856
write_zsreg(uap, 9, NV);
857
write_zsreg(uap, 4, X16CLK | SB_MASK);
858
write_zsreg(uap, 3, Rx8);
860
while (read_zsreg(uap, 0) & Rx_CH_AV) {
861
(void)read_zsreg(uap, 8);
862
write_zsreg(uap, 0, RES_EXT_INT);
863
write_zsreg(uap, 0, ERR_RES);
868
* Real startup routine, powers up the hardware and sets up
869
* the SCC. Returns a delay in ms where you need to wait before
870
* actually using the port, this is typically the internal modem
871
* powerup delay. This routine expect the lock to be taken.
873
static int __pmz_startup(struct uart_pmac_port *uap)
877
memset(&uap->curregs, 0, sizeof(uap->curregs));
879
/* Power up the SCC & underlying hardware (modem/irda) */
880
pwr_delay = pmz_set_scc_power(uap, 1);
882
/* Nice buggy HW ... */
883
pmz_fix_zero_bug_scc(uap);
885
/* Reset the channel */
886
uap->curregs[R9] = 0;
887
write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
890
write_zsreg(uap, 9, 0);
893
/* Clear the interrupt registers */
894
write_zsreg(uap, R1, 0);
895
write_zsreg(uap, R0, ERR_RES);
896
write_zsreg(uap, R0, ERR_RES);
897
write_zsreg(uap, R0, RES_H_IUS);
898
write_zsreg(uap, R0, RES_H_IUS);
900
/* Setup some valid baud rate */
901
uap->curregs[R4] = X16CLK | SB1;
902
uap->curregs[R3] = Rx8;
903
uap->curregs[R5] = Tx8 | RTS;
904
if (!ZS_IS_IRDA(uap))
905
uap->curregs[R5] |= DTR;
906
uap->curregs[R12] = 0;
907
uap->curregs[R13] = 0;
908
uap->curregs[R14] = BRENAB;
910
/* Clear handshaking, enable BREAK interrupts */
911
uap->curregs[R15] = BRKIE;
913
/* Master interrupt enable */
914
uap->curregs[R9] |= NV | MIE;
916
pmz_load_zsregs(uap, uap->curregs);
918
/* Enable receiver and transmitter. */
919
write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
920
write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
922
/* Remember status for DCD/CTS changes */
923
uap->prev_status = read_zsreg(uap, R0);
928
static void pmz_irda_reset(struct uart_pmac_port *uap)
930
uap->curregs[R5] |= DTR;
931
write_zsreg(uap, R5, uap->curregs[R5]);
934
uap->curregs[R5] &= ~DTR;
935
write_zsreg(uap, R5, uap->curregs[R5]);
941
* This is the "normal" startup routine, using the above one
942
* wrapped with the lock and doing a schedule delay
944
static int pmz_startup(struct uart_port *port)
946
struct uart_pmac_port *uap = to_pmz(port);
950
pmz_debug("pmz: startup()\n");
952
if (ZS_IS_ASLEEP(uap))
954
if (uap->node == NULL)
957
mutex_lock(&pmz_irq_mutex);
959
uap->flags |= PMACZILOG_FLAG_IS_OPEN;
961
/* A console is never powered down. Else, power up and
962
* initialize the chip
964
if (!ZS_IS_CONS(uap)) {
965
spin_lock_irqsave(&port->lock, flags);
966
pwr_delay = __pmz_startup(uap);
967
spin_unlock_irqrestore(&port->lock, flags);
970
pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
971
if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
973
pmz_error("Unable to register zs interrupt handler.\n");
974
pmz_set_scc_power(uap, 0);
975
mutex_unlock(&pmz_irq_mutex);
979
mutex_unlock(&pmz_irq_mutex);
981
/* Right now, we deal with delay by blocking here, I'll be
984
if (pwr_delay != 0) {
985
pmz_debug("pmz: delaying %d ms\n", pwr_delay);
989
/* IrDA reset is done now */
993
/* Enable interrupts emission from the chip */
994
spin_lock_irqsave(&port->lock, flags);
995
uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
996
if (!ZS_IS_EXTCLK(uap))
997
uap->curregs[R1] |= EXT_INT_ENAB;
998
write_zsreg(uap, R1, uap->curregs[R1]);
999
spin_unlock_irqrestore(&port->lock, flags);
1001
pmz_debug("pmz: startup() done.\n");
1006
static void pmz_shutdown(struct uart_port *port)
1008
struct uart_pmac_port *uap = to_pmz(port);
1009
unsigned long flags;
1011
pmz_debug("pmz: shutdown()\n");
1013
if (uap->node == NULL)
1016
mutex_lock(&pmz_irq_mutex);
1018
/* Release interrupt handler */
1019
free_irq(uap->port.irq, uap);
1021
spin_lock_irqsave(&port->lock, flags);
1023
uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1025
if (!ZS_IS_OPEN(uap->mate))
1026
pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1028
/* Disable interrupts */
1029
if (!ZS_IS_ASLEEP(uap)) {
1030
uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1031
write_zsreg(uap, R1, uap->curregs[R1]);
1035
if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1036
spin_unlock_irqrestore(&port->lock, flags);
1037
mutex_unlock(&pmz_irq_mutex);
1041
/* Disable receiver and transmitter. */
1042
uap->curregs[R3] &= ~RxENABLE;
1043
uap->curregs[R5] &= ~TxENABLE;
1045
/* Disable all interrupts and BRK assertion. */
1046
uap->curregs[R5] &= ~SND_BRK;
1047
pmz_maybe_update_regs(uap);
1049
/* Shut the chip down */
1050
pmz_set_scc_power(uap, 0);
1052
spin_unlock_irqrestore(&port->lock, flags);
1054
mutex_unlock(&pmz_irq_mutex);
1056
pmz_debug("pmz: shutdown() done.\n");
1059
/* Shared by TTY driver and serial console setup. The port lock is held
1060
* and local interrupts are disabled.
1062
static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1063
unsigned int iflag, unsigned long baud)
1067
/* Switch to external clocking for IrDA high clock rates. That
1068
* code could be re-used for Midi interfaces with different
1071
if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1072
uap->curregs[R4] = X1CLK;
1073
uap->curregs[R11] = RCTRxCP | TCTRxCP;
1074
uap->curregs[R14] = 0; /* BRG off */
1075
uap->curregs[R12] = 0;
1076
uap->curregs[R13] = 0;
1077
uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1080
case ZS_CLOCK/16: /* 230400 */
1081
uap->curregs[R4] = X16CLK;
1082
uap->curregs[R11] = 0;
1083
uap->curregs[R14] = 0;
1085
case ZS_CLOCK/32: /* 115200 */
1086
uap->curregs[R4] = X32CLK;
1087
uap->curregs[R11] = 0;
1088
uap->curregs[R14] = 0;
1091
uap->curregs[R4] = X16CLK;
1092
uap->curregs[R11] = TCBR | RCBR;
1093
brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1094
uap->curregs[R12] = (brg & 255);
1095
uap->curregs[R13] = ((brg >> 8) & 255);
1096
uap->curregs[R14] = BRENAB;
1098
uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1101
/* Character size, stop bits, and parity. */
1102
uap->curregs[3] &= ~RxN_MASK;
1103
uap->curregs[5] &= ~TxN_MASK;
1105
switch (cflag & CSIZE) {
1107
uap->curregs[3] |= Rx5;
1108
uap->curregs[5] |= Tx5;
1109
uap->parity_mask = 0x1f;
1112
uap->curregs[3] |= Rx6;
1113
uap->curregs[5] |= Tx6;
1114
uap->parity_mask = 0x3f;
1117
uap->curregs[3] |= Rx7;
1118
uap->curregs[5] |= Tx7;
1119
uap->parity_mask = 0x7f;
1123
uap->curregs[3] |= Rx8;
1124
uap->curregs[5] |= Tx8;
1125
uap->parity_mask = 0xff;
1128
uap->curregs[4] &= ~(SB_MASK);
1130
uap->curregs[4] |= SB2;
1132
uap->curregs[4] |= SB1;
1134
uap->curregs[4] |= PAR_ENAB;
1136
uap->curregs[4] &= ~PAR_ENAB;
1137
if (!(cflag & PARODD))
1138
uap->curregs[4] |= PAR_EVEN;
1140
uap->curregs[4] &= ~PAR_EVEN;
1142
uap->port.read_status_mask = Rx_OVR;
1144
uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1145
if (iflag & (BRKINT | PARMRK))
1146
uap->port.read_status_mask |= BRK_ABRT;
1148
uap->port.ignore_status_mask = 0;
1150
uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1151
if (iflag & IGNBRK) {
1152
uap->port.ignore_status_mask |= BRK_ABRT;
1154
uap->port.ignore_status_mask |= Rx_OVR;
1157
if ((cflag & CREAD) == 0)
1158
uap->port.ignore_status_mask = 0xff;
1163
* Set the irda codec on the imac to the specified baud rate.
1165
static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1193
/* The FIR modes aren't really supported at this point, how
1194
* do we select the speed ? via the FCR on KeyLargo ?
1208
/* Wait for transmitter to drain */
1210
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1211
|| (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1213
pmz_error("transmitter didn't drain\n");
1219
/* Drain the receiver too */
1221
(void)read_zsdata(uap);
1222
(void)read_zsdata(uap);
1223
(void)read_zsdata(uap);
1225
while (read_zsreg(uap, R0) & Rx_CH_AV) {
1229
pmz_error("receiver didn't drain\n");
1234
/* Switch to command mode */
1235
uap->curregs[R5] |= DTR;
1236
write_zsreg(uap, R5, uap->curregs[R5]);
1240
/* Switch SCC to 19200 */
1241
pmz_convert_to_zs(uap, CS8, 0, 19200);
1242
pmz_load_zsregs(uap, uap->curregs);
1245
/* Write get_version command byte */
1246
write_zsdata(uap, 1);
1248
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1250
pmz_error("irda_setup timed out on get_version byte\n");
1255
version = read_zsdata(uap);
1258
pmz_info("IrDA: dongle version %d not supported\n", version);
1262
/* Send speed mode */
1263
write_zsdata(uap, cmdbyte);
1265
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1267
pmz_error("irda_setup timed out on speed mode byte\n");
1272
t = read_zsdata(uap);
1274
pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1276
pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1279
(void)read_zsdata(uap);
1280
(void)read_zsdata(uap);
1281
(void)read_zsdata(uap);
1284
/* Switch back to data mode */
1285
uap->curregs[R5] &= ~DTR;
1286
write_zsreg(uap, R5, uap->curregs[R5]);
1289
(void)read_zsdata(uap);
1290
(void)read_zsdata(uap);
1291
(void)read_zsdata(uap);
1295
static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1296
struct ktermios *old)
1298
struct uart_pmac_port *uap = to_pmz(port);
1301
pmz_debug("pmz: set_termios()\n");
1303
if (ZS_IS_ASLEEP(uap))
1306
memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1308
/* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1309
* on the IR dongle. Note that the IRTTY driver currently doesn't know
1310
* about the FIR mode and high speed modes. So these are unused. For
1311
* implementing proper support for these, we should probably add some
1312
* DMA as well, at least on the Rx side, which isn't a simple thing
1315
if (ZS_IS_IRDA(uap)) {
1316
/* Calc baud rate */
1317
baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1318
pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1319
/* Cet the irda codec to the right rate */
1320
pmz_irda_setup(uap, &baud);
1321
/* Set final baud rate */
1322
pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1323
pmz_load_zsregs(uap, uap->curregs);
1326
baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1327
pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1328
/* Make sure modem status interrupts are correctly configured */
1329
if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1330
uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1331
uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1333
uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1334
uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1337
/* Load registers to the chip */
1338
pmz_maybe_update_regs(uap);
1340
uart_update_timeout(port, termios->c_cflag, baud);
1342
pmz_debug("pmz: set_termios() done.\n");
1345
/* The port lock is not held. */
1346
static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1347
struct ktermios *old)
1349
struct uart_pmac_port *uap = to_pmz(port);
1350
unsigned long flags;
1352
spin_lock_irqsave(&port->lock, flags);
1354
/* Disable IRQs on the port */
1355
uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1356
write_zsreg(uap, R1, uap->curregs[R1]);
1358
/* Setup new port configuration */
1359
__pmz_set_termios(port, termios, old);
1361
/* Re-enable IRQs on the port */
1362
if (ZS_IS_OPEN(uap)) {
1363
uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1364
if (!ZS_IS_EXTCLK(uap))
1365
uap->curregs[R1] |= EXT_INT_ENAB;
1366
write_zsreg(uap, R1, uap->curregs[R1]);
1368
spin_unlock_irqrestore(&port->lock, flags);
1371
static const char *pmz_type(struct uart_port *port)
1373
struct uart_pmac_port *uap = to_pmz(port);
1375
if (ZS_IS_IRDA(uap))
1376
return "Z85c30 ESCC - Infrared port";
1377
else if (ZS_IS_INTMODEM(uap))
1378
return "Z85c30 ESCC - Internal modem";
1379
return "Z85c30 ESCC - Serial port";
1382
/* We do not request/release mappings of the registers here, this
1383
* happens at early serial probe time.
1385
static void pmz_release_port(struct uart_port *port)
1389
static int pmz_request_port(struct uart_port *port)
1394
/* These do not need to do anything interesting either. */
1395
static void pmz_config_port(struct uart_port *port, int flags)
1399
/* We do not support letting the user mess with the divisor, IRQ, etc. */
1400
static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1405
#ifdef CONFIG_CONSOLE_POLL
1407
static int pmz_poll_get_char(struct uart_port *port)
1409
struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1411
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0)
1413
return read_zsdata(uap);
1416
static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1418
struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1420
/* Wait for the transmit buffer to empty. */
1421
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1423
write_zsdata(uap, c);
1426
#endif /* CONFIG_CONSOLE_POLL */
1428
static struct uart_ops pmz_pops = {
1429
.tx_empty = pmz_tx_empty,
1430
.set_mctrl = pmz_set_mctrl,
1431
.get_mctrl = pmz_get_mctrl,
1432
.stop_tx = pmz_stop_tx,
1433
.start_tx = pmz_start_tx,
1434
.stop_rx = pmz_stop_rx,
1435
.enable_ms = pmz_enable_ms,
1436
.break_ctl = pmz_break_ctl,
1437
.startup = pmz_startup,
1438
.shutdown = pmz_shutdown,
1439
.set_termios = pmz_set_termios,
1441
.release_port = pmz_release_port,
1442
.request_port = pmz_request_port,
1443
.config_port = pmz_config_port,
1444
.verify_port = pmz_verify_port,
1445
#ifdef CONFIG_CONSOLE_POLL
1446
.poll_get_char = pmz_poll_get_char,
1447
.poll_put_char = pmz_poll_put_char,
1451
#ifdef CONFIG_PPC_PMAC
1454
* Setup one port structure after probing, HW is down at this point,
1455
* Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1456
* register our console before uart_add_one_port() is called
1458
static int __init pmz_init_port(struct uart_pmac_port *uap)
1460
struct device_node *np = uap->node;
1462
const struct slot_names_prop {
1467
struct resource r_ports, r_rxdma, r_txdma;
1470
* Request & map chip registers
1472
if (of_address_to_resource(np, 0, &r_ports))
1474
uap->port.mapbase = r_ports.start;
1475
uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1477
uap->control_reg = uap->port.membase;
1478
uap->data_reg = uap->control_reg + 0x10;
1481
* Request & map DBDMA registers
1484
if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1485
of_address_to_resource(np, 2, &r_rxdma) == 0)
1486
uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1488
memset(&r_txdma, 0, sizeof(struct resource));
1489
memset(&r_rxdma, 0, sizeof(struct resource));
1491
if (ZS_HAS_DMA(uap)) {
1492
uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1493
if (uap->tx_dma_regs == NULL) {
1494
uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1497
uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1498
if (uap->rx_dma_regs == NULL) {
1499
iounmap(uap->tx_dma_regs);
1500
uap->tx_dma_regs = NULL;
1501
uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1504
uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1505
uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1512
if (of_device_is_compatible(np, "cobalt"))
1513
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1514
conn = of_get_property(np, "AAPL,connector", &len);
1515
if (conn && (strcmp(conn, "infrared") == 0))
1516
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1517
uap->port_type = PMAC_SCC_ASYNC;
1518
/* 1999 Powerbook G3 has slot-names property instead */
1519
slots = of_get_property(np, "slot-names", &len);
1520
if (slots && slots->count > 0) {
1521
if (strcmp(slots->name, "IrDA") == 0)
1522
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1523
else if (strcmp(slots->name, "Modem") == 0)
1524
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1526
if (ZS_IS_IRDA(uap))
1527
uap->port_type = PMAC_SCC_IRDA;
1528
if (ZS_IS_INTMODEM(uap)) {
1529
struct device_node* i2c_modem =
1530
of_find_node_by_name(NULL, "i2c-modem");
1533
of_get_property(i2c_modem, "modem-id", NULL);
1534
if (mid) switch(*mid) {
1541
uap->port_type = PMAC_SCC_I2S1;
1543
printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1545
of_node_put(i2c_modem);
1547
printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1552
* Init remaining bits of "port" structure
1554
uap->port.iotype = UPIO_MEM;
1555
uap->port.irq = irq_of_parse_and_map(np, 0);
1556
uap->port.uartclk = ZS_CLOCK;
1557
uap->port.fifosize = 1;
1558
uap->port.ops = &pmz_pops;
1559
uap->port.type = PORT_PMAC_ZILOG;
1560
uap->port.flags = 0;
1563
* Fixup for the port on Gatwick for which the device-tree has
1564
* missing interrupts. Normally, the macio_dev would contain
1565
* fixed up interrupt info, but we use the device-tree directly
1566
* here due to early probing so we need the fixup too.
1568
if (uap->port.irq == NO_IRQ &&
1569
np->parent && np->parent->parent &&
1570
of_device_is_compatible(np->parent->parent, "gatwick")) {
1571
/* IRQs on gatwick are offset by 64 */
1572
uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1573
uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1574
uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1577
/* Setup some valid baud rate information in the register
1578
* shadows so we don't write crap there before baud rate is
1579
* first initialized.
1581
pmz_convert_to_zs(uap, CS8, 0, 9600);
1587
* Get rid of a port on module removal
1589
static void pmz_dispose_port(struct uart_pmac_port *uap)
1591
struct device_node *np;
1594
iounmap(uap->rx_dma_regs);
1595
iounmap(uap->tx_dma_regs);
1596
iounmap(uap->control_reg);
1599
memset(uap, 0, sizeof(struct uart_pmac_port));
1603
* Called upon match with an escc node in the device-tree.
1605
static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1609
/* Iterate the pmz_ports array to find a matching entry
1611
for (i = 0; i < MAX_ZS_PORTS; i++)
1612
if (pmz_ports[i].node == mdev->ofdev.dev.of_node) {
1613
struct uart_pmac_port *uap = &pmz_ports[i];
1616
dev_set_drvdata(&mdev->ofdev.dev, uap);
1617
if (macio_request_resources(uap->dev, "pmac_zilog"))
1618
printk(KERN_WARNING "%s: Failed to request resource"
1619
", port still active\n",
1622
uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1629
* That one should not be called, macio isn't really a hotswap device,
1630
* we don't expect one of those serial ports to go away...
1632
static int pmz_detach(struct macio_dev *mdev)
1634
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1639
if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1640
macio_release_resources(uap->dev);
1641
uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1643
dev_set_drvdata(&mdev->ofdev.dev, NULL);
1650
static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1652
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1653
struct uart_state *state;
1654
unsigned long flags;
1657
printk("HRM... pmz_suspend with NULL uap\n");
1661
if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1664
pmz_debug("suspend, switching to state %d\n", pm_state.event);
1666
state = pmz_uart_reg.state + uap->port.line;
1668
mutex_lock(&pmz_irq_mutex);
1669
mutex_lock(&state->port.mutex);
1671
spin_lock_irqsave(&uap->port.lock, flags);
1673
if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1674
/* Disable receiver and transmitter. */
1675
uap->curregs[R3] &= ~RxENABLE;
1676
uap->curregs[R5] &= ~TxENABLE;
1678
/* Disable all interrupts and BRK assertion. */
1679
uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1680
uap->curregs[R5] &= ~SND_BRK;
1681
pmz_load_zsregs(uap, uap->curregs);
1682
uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1686
spin_unlock_irqrestore(&uap->port.lock, flags);
1688
if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1689
if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1690
pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1691
disable_irq(uap->port.irq);
1694
if (ZS_IS_CONS(uap))
1695
uap->port.cons->flags &= ~CON_ENABLED;
1697
/* Shut the chip down */
1698
pmz_set_scc_power(uap, 0);
1700
mutex_unlock(&state->port.mutex);
1701
mutex_unlock(&pmz_irq_mutex);
1703
pmz_debug("suspend, switching complete\n");
1705
mdev->ofdev.dev.power.power_state = pm_state;
1711
static int pmz_resume(struct macio_dev *mdev)
1713
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1714
struct uart_state *state;
1715
unsigned long flags;
1721
if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1724
pmz_debug("resume, switching to state 0\n");
1726
state = pmz_uart_reg.state + uap->port.line;
1728
mutex_lock(&pmz_irq_mutex);
1729
mutex_lock(&state->port.mutex);
1731
spin_lock_irqsave(&uap->port.lock, flags);
1732
if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1733
spin_unlock_irqrestore(&uap->port.lock, flags);
1736
pwr_delay = __pmz_startup(uap);
1738
/* Take care of config that may have changed while asleep */
1739
__pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1741
if (ZS_IS_OPEN(uap)) {
1742
/* Enable interrupts */
1743
uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1744
if (!ZS_IS_EXTCLK(uap))
1745
uap->curregs[R1] |= EXT_INT_ENAB;
1746
write_zsreg(uap, R1, uap->curregs[R1]);
1749
spin_unlock_irqrestore(&uap->port.lock, flags);
1751
if (ZS_IS_CONS(uap))
1752
uap->port.cons->flags |= CON_ENABLED;
1754
/* Re-enable IRQ on the controller */
1755
if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1756
pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1757
enable_irq(uap->port.irq);
1761
mutex_unlock(&state->port.mutex);
1762
mutex_unlock(&pmz_irq_mutex);
1764
/* Right now, we deal with delay by blocking here, I'll be
1767
if (pwr_delay != 0) {
1768
pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1772
pmz_debug("resume, switching complete\n");
1774
mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1780
* Probe all ports in the system and build the ports array, we register
1781
* with the serial layer at this point, the macio-type probing is only
1782
* used later to "attach" to the sysfs tree so we get power management
1785
static int __init pmz_probe(void)
1787
struct device_node *node_p, *node_a, *node_b, *np;
1792
* Find all escc chips in the system
1794
node_p = of_find_node_by_name(NULL, "escc");
1797
* First get channel A/B node pointers
1799
* TODO: Add routines with proper locking to do that...
1801
node_a = node_b = NULL;
1802
for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1803
if (strncmp(np->name, "ch-a", 4) == 0)
1804
node_a = of_node_get(np);
1805
else if (strncmp(np->name, "ch-b", 4) == 0)
1806
node_b = of_node_get(np);
1808
if (!node_a && !node_b) {
1809
of_node_put(node_a);
1810
of_node_put(node_b);
1811
printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1812
(!node_a) ? 'a' : 'b', node_p->full_name);
1817
* Fill basic fields in the port structures
1819
pmz_ports[count].mate = &pmz_ports[count+1];
1820
pmz_ports[count+1].mate = &pmz_ports[count];
1821
pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1822
pmz_ports[count].node = node_a;
1823
pmz_ports[count+1].node = node_b;
1824
pmz_ports[count].port.line = count;
1825
pmz_ports[count+1].port.line = count+1;
1828
* Setup the ports for real
1830
rc = pmz_init_port(&pmz_ports[count]);
1831
if (rc == 0 && node_b != NULL)
1832
rc = pmz_init_port(&pmz_ports[count+1]);
1834
of_node_put(node_a);
1835
of_node_put(node_b);
1836
memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1837
memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1842
node_p = of_find_node_by_name(node_p, "escc");
1844
pmz_ports_count = count;
1851
extern struct platform_device scc_a_pdev, scc_b_pdev;
1853
static int __init pmz_init_port(struct uart_pmac_port *uap)
1855
struct resource *r_ports;
1858
r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0);
1859
irq = platform_get_irq(uap->node, 0);
1860
if (!r_ports || !irq)
1863
uap->port.mapbase = r_ports->start;
1864
uap->port.membase = (unsigned char __iomem *) r_ports->start;
1865
uap->port.iotype = UPIO_MEM;
1866
uap->port.irq = irq;
1867
uap->port.uartclk = ZS_CLOCK;
1868
uap->port.fifosize = 1;
1869
uap->port.ops = &pmz_pops;
1870
uap->port.type = PORT_PMAC_ZILOG;
1871
uap->port.flags = 0;
1873
uap->control_reg = uap->port.membase;
1874
uap->data_reg = uap->control_reg + 4;
1877
pmz_convert_to_zs(uap, CS8, 0, 9600);
1882
static int __init pmz_probe(void)
1886
pmz_ports_count = 0;
1888
pmz_ports[0].mate = &pmz_ports[1];
1889
pmz_ports[0].port.line = 0;
1890
pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1891
pmz_ports[0].node = &scc_a_pdev;
1892
err = pmz_init_port(&pmz_ports[0]);
1897
pmz_ports[1].mate = &pmz_ports[0];
1898
pmz_ports[1].port.line = 1;
1899
pmz_ports[1].flags = 0;
1900
pmz_ports[1].node = &scc_b_pdev;
1901
err = pmz_init_port(&pmz_ports[1]);
1909
static void pmz_dispose_port(struct uart_pmac_port *uap)
1911
memset(uap, 0, sizeof(struct uart_pmac_port));
1914
static int __init pmz_attach(struct platform_device *pdev)
1918
for (i = 0; i < pmz_ports_count; i++)
1919
if (pmz_ports[i].node == pdev)
1924
static int __exit pmz_detach(struct platform_device *pdev)
1929
#endif /* !CONFIG_PPC_PMAC */
1931
#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1933
static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1934
static int __init pmz_console_setup(struct console *co, char *options);
1936
static struct console pmz_console = {
1937
.name = PMACZILOG_NAME,
1938
.write = pmz_console_write,
1939
.device = uart_console_device,
1940
.setup = pmz_console_setup,
1941
.flags = CON_PRINTBUFFER,
1943
.data = &pmz_uart_reg,
1946
#define PMACZILOG_CONSOLE &pmz_console
1947
#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1948
#define PMACZILOG_CONSOLE (NULL)
1949
#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1952
* Register the driver, console driver and ports with the serial
1955
static int __init pmz_register(void)
1959
pmz_uart_reg.nr = pmz_ports_count;
1960
pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1963
* Register this driver with the serial core
1965
rc = uart_register_driver(&pmz_uart_reg);
1970
* Register each port with the serial core
1972
for (i = 0; i < pmz_ports_count; i++) {
1973
struct uart_pmac_port *uport = &pmz_ports[i];
1974
/* NULL node may happen on wallstreet */
1975
if (uport->node != NULL)
1976
rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1984
struct uart_pmac_port *uport = &pmz_ports[i];
1985
uart_remove_one_port(&pmz_uart_reg, &uport->port);
1987
uart_unregister_driver(&pmz_uart_reg);
1991
#ifdef CONFIG_PPC_PMAC
1993
static struct of_device_id pmz_match[] =
2003
MODULE_DEVICE_TABLE (of, pmz_match);
2005
static struct macio_driver pmz_driver = {
2007
.name = "pmac_zilog",
2008
.owner = THIS_MODULE,
2009
.of_match_table = pmz_match,
2011
.probe = pmz_attach,
2012
.remove = pmz_detach,
2013
.suspend = pmz_suspend,
2014
.resume = pmz_resume,
2019
static struct platform_driver pmz_driver = {
2020
.remove = __exit_p(pmz_detach),
2023
.owner = THIS_MODULE,
2027
#endif /* !CONFIG_PPC_PMAC */
2029
static int __init init_pmz(void)
2032
printk(KERN_INFO "%s\n", version);
2035
* First, we need to do a direct OF-based probe pass. We
2036
* do that because we want serial console up before the
2037
* macio stuffs calls us back, and since that makes it
2038
* easier to pass the proper number of channels to
2039
* uart_register_driver()
2041
if (pmz_ports_count == 0)
2045
* Bail early if no port found
2047
if (pmz_ports_count == 0)
2051
* Now we register with the serial layer
2053
rc = pmz_register();
2056
"pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
2057
"pmac_zilog: Did another serial driver already claim the minors?\n");
2058
/* effectively "pmz_unprobe()" */
2059
for (i=0; i < pmz_ports_count; i++)
2060
pmz_dispose_port(&pmz_ports[i]);
2065
* Then we register the macio driver itself
2067
#ifdef CONFIG_PPC_PMAC
2068
return macio_register_driver(&pmz_driver);
2070
return platform_driver_probe(&pmz_driver, pmz_attach);
2074
static void __exit exit_pmz(void)
2078
#ifdef CONFIG_PPC_PMAC
2079
/* Get rid of macio-driver (detach from macio) */
2080
macio_unregister_driver(&pmz_driver);
2082
platform_driver_unregister(&pmz_driver);
2085
for (i = 0; i < pmz_ports_count; i++) {
2086
struct uart_pmac_port *uport = &pmz_ports[i];
2087
if (uport->node != NULL) {
2088
uart_remove_one_port(&pmz_uart_reg, &uport->port);
2089
pmz_dispose_port(uport);
2092
/* Unregister UART driver */
2093
uart_unregister_driver(&pmz_uart_reg);
2096
#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
2098
static void pmz_console_putchar(struct uart_port *port, int ch)
2100
struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
2102
/* Wait for the transmit buffer to empty. */
2103
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
2105
write_zsdata(uap, ch);
2109
* Print a string to the serial port trying not to disturb
2110
* any possible real use of the port...
2112
static void pmz_console_write(struct console *con, const char *s, unsigned int count)
2114
struct uart_pmac_port *uap = &pmz_ports[con->index];
2115
unsigned long flags;
2117
if (ZS_IS_ASLEEP(uap))
2119
spin_lock_irqsave(&uap->port.lock, flags);
2121
/* Turn of interrupts and enable the transmitter. */
2122
write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2123
write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2125
uart_console_write(&uap->port, s, count, pmz_console_putchar);
2127
/* Restore the values in the registers. */
2128
write_zsreg(uap, R1, uap->curregs[1]);
2129
/* Don't disable the transmitter. */
2131
spin_unlock_irqrestore(&uap->port.lock, flags);
2135
* Setup the serial console
2137
static int __init pmz_console_setup(struct console *co, char *options)
2139
struct uart_pmac_port *uap;
2140
struct uart_port *port;
2145
unsigned long pwr_delay;
2148
* XServe's default to 57600 bps
2150
if (of_machine_is_compatible("RackMac1,1")
2151
|| of_machine_is_compatible("RackMac1,2")
2152
|| of_machine_is_compatible("MacRISC4"))
2156
* Check whether an invalid uart number has been specified, and
2157
* if so, search for the first available port that does have
2160
if (co->index >= pmz_ports_count)
2162
uap = &pmz_ports[co->index];
2163
if (uap->node == NULL)
2168
* Mark port as beeing a console
2170
uap->flags |= PMACZILOG_FLAG_IS_CONS;
2173
* Temporary fix for uart layer who didn't setup the spinlock yet
2175
spin_lock_init(&port->lock);
2178
* Enable the hardware
2180
pwr_delay = __pmz_startup(uap);
2185
uart_parse_options(options, &baud, &parity, &bits, &flow);
2187
return uart_set_options(port, co, baud, parity, bits, flow);
2190
static int __init pmz_console_init(void)
2195
/* TODO: Autoprobe console based on OF */
2196
/* pmz_console.index = i; */
2197
register_console(&pmz_console);
2202
console_initcall(pmz_console_init);
2203
#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2205
module_init(init_pmz);
2206
module_exit(exit_pmz);