4
* Copyright (C) 2007 Paul Mundt
6
* This file is subject to the terms and conditions of the GNU General Public
7
* License. See the file "COPYING" in the main directory of this archive
10
#include <linux/platform_device.h>
11
#include <linux/init.h>
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#include <linux/serial.h>
13
#include <linux/serial_sci.h>
16
#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <asm/mmzone.h>
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#include <cpu/dma-register.h>
21
static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffea0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
25
.scbrr_algo_id = SCBRR_ALGO_1,
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.irqs = { 40, 40, 40, 40 },
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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static struct platform_device scif0_device = {
35
.platform_data = &scif0_platform_data,
39
static struct plat_sci_port scif1_platform_data = {
40
.mapbase = 0xffeb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
43
.scbrr_algo_id = SCBRR_ALGO_1,
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.irqs = { 44, 44, 44, 44 },
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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static struct platform_device scif1_device = {
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.platform_data = &scif1_platform_data,
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xffec0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_1,
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.irqs = { 60, 60, 60, 60 },
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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static struct platform_device scif2_device = {
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.platform_data = &scif2_platform_data,
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static struct plat_sci_port scif3_platform_data = {
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.mapbase = 0xffed0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_1,
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.irqs = { 61, 61, 61, 61 },
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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static struct platform_device scif3_device = {
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.platform_data = &scif3_platform_data,
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static struct plat_sci_port scif4_platform_data = {
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.mapbase = 0xffee0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_1,
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.irqs = { 62, 62, 62, 62 },
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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static struct platform_device scif4_device = {
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.platform_data = &scif4_platform_data,
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static struct plat_sci_port scif5_platform_data = {
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.mapbase = 0xffef0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_1,
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.irqs = { 63, 63, 63, 63 },
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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static struct platform_device scif5_device = {
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.platform_data = &scif5_platform_data,
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static struct sh_timer_config tmu0_platform_data = {
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.channel_offset = 0x04,
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.clockevent_rating = 200,
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static struct resource tmu0_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_IRQ,
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static struct platform_device tmu0_device = {
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.platform_data = &tmu0_platform_data,
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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static struct sh_timer_config tmu1_platform_data = {
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.channel_offset = 0x10,
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.clocksource_rating = 200,
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static struct resource tmu1_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_IRQ,
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static struct platform_device tmu1_device = {
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.platform_data = &tmu1_platform_data,
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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static struct sh_timer_config tmu2_platform_data = {
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.channel_offset = 0x1c,
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static struct resource tmu2_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_IRQ,
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static struct platform_device tmu2_device = {
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.platform_data = &tmu2_platform_data,
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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static struct sh_timer_config tmu3_platform_data = {
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.channel_offset = 0x04,
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static struct resource tmu3_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_IRQ,
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static struct platform_device tmu3_device = {
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.platform_data = &tmu3_platform_data,
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.resource = tmu3_resources,
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.num_resources = ARRAY_SIZE(tmu3_resources),
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static struct sh_timer_config tmu4_platform_data = {
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.channel_offset = 0x10,
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static struct resource tmu4_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_IRQ,
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static struct platform_device tmu4_device = {
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.platform_data = &tmu4_platform_data,
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.resource = tmu4_resources,
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.num_resources = ARRAY_SIZE(tmu4_resources),
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static struct sh_timer_config tmu5_platform_data = {
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.channel_offset = 0x1c,
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static struct resource tmu5_resources[] = {
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_IRQ,
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static struct platform_device tmu5_device = {
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.platform_data = &tmu5_platform_data,
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.resource = tmu5_resources,
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.num_resources = ARRAY_SIZE(tmu5_resources),
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static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
322
static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
338
static const unsigned int ts_shift[] = TS_SHIFT;
340
static struct sh_dmae_pdata dma0_platform_data = {
341
.channel = sh7785_dmae0_channels,
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.channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
343
.ts_low_shift = CHCR_TS_LOW_SHIFT,
344
.ts_low_mask = CHCR_TS_LOW_MASK,
345
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
346
.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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static struct sh_dmae_pdata dma1_platform_data = {
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.channel = sh7785_dmae1_channels,
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.channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
356
.ts_low_mask = CHCR_TS_LOW_MASK,
357
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
359
.ts_shift = ts_shift,
360
.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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static struct resource sh7785_dmae0_resources[] = {
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/* Channel registers and DMAOR */
369
.flags = IORESOURCE_MEM,
375
.flags = IORESOURCE_MEM,
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/* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
381
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
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static struct resource sh7785_dmae1_resources[] = {
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/* Channel registers and DMAOR */
390
.flags = IORESOURCE_MEM,
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/* DMAC1 has no DMARS */
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/* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
397
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
401
static struct platform_device dma0_device = {
402
.name = "sh-dma-engine",
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.resource = sh7785_dmae0_resources,
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.num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
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.platform_data = &dma0_platform_data,
411
static struct platform_device dma1_device = {
412
.name = "sh-dma-engine",
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.resource = sh7785_dmae1_resources,
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.num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
417
.platform_data = &dma1_platform_data,
421
static struct platform_device *sh7785_devices[] __initdata = {
438
static int __init sh7785_devices_setup(void)
440
return platform_add_devices(sh7785_devices,
441
ARRAY_SIZE(sh7785_devices));
443
arch_initcall(sh7785_devices_setup);
445
static struct platform_device *sh7785_early_devices[] __initdata = {
460
void __init plat_early_device_setup(void)
462
early_platform_add_devices(sh7785_early_devices,
463
ARRAY_SIZE(sh7785_early_devices));
469
/* interrupt sources */
471
IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
472
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
473
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
474
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
476
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
477
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
478
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
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IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
482
WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
483
HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
484
SCIF2, SCIF3, SCIF4, SCIF5,
485
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
486
SIOF, MMCIF, DU, GDTA,
492
/* interrupt groups */
497
static struct intc_vect vectors[] __initdata = {
498
INTC_VECT(WDT, 0x560),
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INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
500
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
501
INTC_VECT(HUDI, 0x600),
502
INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
503
INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
504
INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
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INTC_VECT(DMAC0, 0x6e0),
506
INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
507
INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
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INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
509
INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
510
INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
511
INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
512
INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
513
INTC_VECT(DMAC1, 0x940),
514
INTC_VECT(HSPI, 0x960),
515
INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
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INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
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INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
518
INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
519
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
520
INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
521
INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
522
INTC_VECT(SIOF, 0xc00),
523
INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
524
INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
525
INTC_VECT(DU, 0xd80),
526
INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
527
INTC_VECT(GDTA, 0xde0),
528
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
529
INTC_VECT(TMU5, 0xe40),
530
INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
531
INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
532
INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
533
INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
534
INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
535
INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
538
static struct intc_group groups[] __initdata = {
539
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
540
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
543
static struct intc_mask_reg mask_registers[] __initdata = {
544
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
545
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
547
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
548
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
549
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
550
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
551
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
552
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
553
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
554
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
555
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
557
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
558
{ 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
559
FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
560
PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
561
SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
564
static struct intc_prio_reg prio_registers[] __initdata = {
565
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
566
IRQ4, IRQ5, IRQ6, IRQ7 } },
567
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
568
TMU2, TMU2_TICPI } },
569
{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
570
{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
572
{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
573
{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
574
{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
575
PCISERR, PCIINTA } },
576
{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
578
{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
579
{ 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
580
{ 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
583
static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
584
mask_registers, prio_registers, NULL);
586
/* Support for external interrupt pins in IRQ mode */
588
static struct intc_vect vectors_irq0123[] __initdata = {
589
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
590
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
593
static struct intc_vect vectors_irq4567[] __initdata = {
594
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
595
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
598
static struct intc_sense_reg sense_registers[] __initdata = {
599
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
600
IRQ4, IRQ5, IRQ6, IRQ7 } },
603
static struct intc_mask_reg ack_registers[] __initdata = {
604
{ 0xffd00024, 0, 32, /* INTREQ */
605
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
608
static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
609
vectors_irq0123, NULL, mask_registers,
610
prio_registers, sense_registers, ack_registers);
612
static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
613
vectors_irq4567, NULL, mask_registers,
614
prio_registers, sense_registers, ack_registers);
616
/* External interrupt pins in IRL mode */
618
static struct intc_vect vectors_irl0123[] __initdata = {
619
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
620
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
621
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
622
INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
623
INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
624
INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
625
INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
626
INTC_VECT(IRL0_HHHL, 0x3c0),
629
static struct intc_vect vectors_irl4567[] __initdata = {
630
INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
631
INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
632
INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
633
INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
634
INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
635
INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
636
INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
637
INTC_VECT(IRL4_HHHL, 0xcc0),
640
static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
641
NULL, mask_registers, NULL, NULL);
643
static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
644
NULL, mask_registers, NULL, NULL);
646
#define INTC_ICR0 0xffd00000
647
#define INTC_INTMSK0 0xffd00044
648
#define INTC_INTMSK1 0xffd00048
649
#define INTC_INTMSK2 0xffd40080
650
#define INTC_INTMSKCLR1 0xffd00068
651
#define INTC_INTMSKCLR2 0xffd40084
653
void __init plat_irq_setup(void)
655
/* disable IRQ3-0 + IRQ7-4 */
656
__raw_writel(0xff000000, INTC_INTMSK0);
658
/* disable IRL3-0 + IRL7-4 */
659
__raw_writel(0xc0000000, INTC_INTMSK1);
660
__raw_writel(0xfffefffe, INTC_INTMSK2);
662
/* select IRL mode for IRL3-0 + IRL7-4 */
663
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
665
/* disable holding function, ie enable "SH-4 Mode" */
666
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
668
register_intc_controller(&intc_desc);
671
void __init plat_irq_setup_pins(int mode)
674
case IRQ_MODE_IRQ7654:
675
/* select IRQ mode for IRL7-4 */
676
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
677
register_intc_controller(&intc_desc_irq4567);
679
case IRQ_MODE_IRQ3210:
680
/* select IRQ mode for IRL3-0 */
681
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
682
register_intc_controller(&intc_desc_irq0123);
684
case IRQ_MODE_IRL7654:
685
/* enable IRL7-4 but don't provide any masking */
686
__raw_writel(0x40000000, INTC_INTMSKCLR1);
687
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
689
case IRQ_MODE_IRL3210:
690
/* enable IRL0-3 but don't provide any masking */
691
__raw_writel(0x80000000, INTC_INTMSKCLR1);
692
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
694
case IRQ_MODE_IRL7654_MASK:
695
/* enable IRL7-4 and mask using cpu intc controller */
696
__raw_writel(0x40000000, INTC_INTMSKCLR1);
697
register_intc_controller(&intc_desc_irl4567);
699
case IRQ_MODE_IRL3210_MASK:
700
/* enable IRL0-3 and mask using cpu intc controller */
701
__raw_writel(0x80000000, INTC_INTMSKCLR1);
702
register_intc_controller(&intc_desc_irl0123);
709
void __init plat_mem_setup(void)
711
/* Register the URAM space as Node 1 */
712
setup_bootmem_node(1, 0xe55f0000, 0xe5610000);