2
* Table of the DAVINCI register configurations for the PINMUX combinations
4
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
6
* Based on linux/include/asm-arm/arch-omap/mux.h:
7
* Copyright (C) 2003 - 2005 Nokia Corporation
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* Written by Tony Lindgren
11
* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* Copyright (C) 2008 Texas Instruments.
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#ifndef __INC_MACH_MUX_H
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#define __INC_MACH_MUX_H
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const char *mux_reg_name;
25
const unsigned char mux_reg;
26
const unsigned char mask_offset;
27
const unsigned char mask;
28
const unsigned char mode;
32
enum davinci_dm644x_index {
33
/* ATA and HDDIR functions */
78
/* EMAC and MDIO function */
81
/* GPIO3V[0:16] pins */
98
enum davinci_dm646x_index {
110
DM646X_STSOMUX_DISABLE,
111
DM646X_STSIMUX_DISABLE,
112
DM646X_PTSOMUX_DISABLE,
113
DM646X_PTSIMUX_DISABLE,
118
DM646X_PTSOMUX_PARALLEL,
119
DM646X_PTSIMUX_PARALLEL,
120
DM646X_PTSOMUX_SERIAL,
121
DM646X_PTSIMUX_SERIAL,
124
enum davinci_dm355_index {
155
DM355_INT_EDMA_TC0_ERR,
156
DM355_INT_EDMA_TC1_ERR,
158
/* EDMA event muxing */
165
DM355_VOUT_FIELD_G70,
170
/* Video In Pin Mux */
180
enum davinci_dm365_index {
309
DM365_VOUT_FIELD_G81,
321
DM365_INT_EDMA_TC0_ERR,
322
DM365_INT_EDMA_TC1_ERR,
323
DM365_INT_EDMA_TC2_ERR,
324
DM365_INT_EDMA_TC3_ERR,
326
DM365_INT_EMAC_RXTHRESH,
327
DM365_INT_EMAC_RXPULSE,
328
DM365_INT_EMAC_TXPULSE,
329
DM365_INT_EMAC_MISCPULSE,
330
DM365_INT_IMX0_ENABLE,
331
DM365_INT_IMX0_DISABLE,
332
DM365_INT_HDVICP_ENABLE,
333
DM365_INT_HDVICP_DISABLE,
334
DM365_INT_IMX1_ENABLE,
335
DM365_INT_IMX1_DISABLE,
336
DM365_INT_NSF_ENABLE,
337
DM365_INT_NSF_DISABLE,
339
/* EDMA event muxing */
495
DA830_RMII_MHZ_50_CLK,
702
DA830_NLCD_AC_ENB_CS,
751
enum davinci_da850_index {
803
DA850_RMII_MHZ_50_CLK,
850
DA850_NLCD_AC_ENB_CS,
852
/* MMC/SD0 function */
860
/* MMC/SD1 function */
868
/* EMIF2.5/EMIFA function */
933
enum davinci_tnetv107x_index {
957
TNETV107X_BOOT_STRP_0,
959
TNETV107X_BOOT_STRP_1,
972
TNETV107X_SDIO1_DATA3_0,
975
TNETV107X_SDIO1_DATA2_0,
978
TNETV107X_SDIO1_DATA1_0,
981
TNETV107X_SDIO1_DATA0_0,
984
TNETV107X_SDIO1_CMD_0,
987
TNETV107X_SDIO1_CLK_0,
990
TNETV107X_SYS_PLL_CLK,
994
TNETV107X_TDM_PLL_CLK,
996
TNETV107X_ETH_PHY_CLK,
1018
TNETV107X_SDIO1_DATA3_1,
1020
TNETV107X_SDIO1_DATA2_1,
1022
TNETV107X_SDIO1_DATA1_1,
1024
TNETV107X_SDIO1_DATA0_1,
1026
TNETV107X_SDIO1_CMD_1,
1028
TNETV107X_SDIO1_CLK_1,
1030
TNETV107X_BOOT_STRP_2,
1036
TNETV107X_BOOT_STRP_3,
1037
TNETV107X_ASR_WE_DQM0,
1039
TNETV107X_LCD_PD17_0,
1040
TNETV107X_ASR_WE_DQM1,
1041
TNETV107X_ASR_BA0_0,
1042
TNETV107X_VLYNQ_CLK,
1044
TNETV107X_LCD_PD19_0,
1045
TNETV107X_VLYNQ_RXD0,
1047
TNETV107X_LCD_PD20_0,
1048
TNETV107X_VLYNQ_RXD1,
1050
TNETV107X_LCD_PD21_0,
1051
TNETV107X_VLYNQ_TXD0,
1053
TNETV107X_LCD_PD22_0,
1054
TNETV107X_VLYNQ_TXD1,
1056
TNETV107X_LCD_PD23_0,
1057
TNETV107X_SDIO0_CLK,
1059
TNETV107X_SDIO0_CMD,
1061
TNETV107X_SDIO0_DATA0,
1063
TNETV107X_SDIO0_DATA1,
1065
TNETV107X_SDIO0_DATA2,
1067
TNETV107X_SDIO0_DATA3,
1081
TNETV107X_KEYPAD_R0,
1082
TNETV107X_KEYPAD_R1,
1083
TNETV107X_KEYPAD_R2,
1084
TNETV107X_KEYPAD_R3,
1085
TNETV107X_KEYPAD_R4,
1086
TNETV107X_KEYPAD_R5,
1087
TNETV107X_KEYPAD_R6,
1089
TNETV107X_KEYPAD_R7,
1091
TNETV107X_KEYPAD_C0,
1092
TNETV107X_KEYPAD_C1,
1093
TNETV107X_KEYPAD_C2,
1094
TNETV107X_KEYPAD_C3,
1095
TNETV107X_KEYPAD_C4,
1096
TNETV107X_KEYPAD_C5,
1097
TNETV107X_KEYPAD_C6,
1099
TNETV107X_TEST_CLK_IN,
1100
TNETV107X_KEYPAD_C7,
1104
TNETV107X_LCD_PD20_1,
1107
TNETV107X_LCD_PD21_1,
1110
TNETV107X_LCD_PD22_1,
1112
TNETV107X_SCC_RESETN,
1113
TNETV107X_LCD_PD23_1,
1116
TNETV107X_UART2_CTS,
1122
TNETV107X_UART2_RTS,
1126
TNETV107X_UART0_CTS,
1128
TNETV107X_UART0_RTS,
1132
TNETV107X_LCD_AC_NCS,
1133
TNETV107X_LCD_HSYNC_RNW,
1134
TNETV107X_LCD_VSYNC_A0,
1136
TNETV107X_LCD_PD16_0,
1137
TNETV107X_LCD_PCLK_E,
1151
TNETV107X_ASR_BA0_1,
1168
TNETV107X_LCD_PD20_2,
1169
TNETV107X_TDM_CLK_IN_2,
1171
TNETV107X_LCD_PD21_2,
1172
TNETV107X_24M_CLK_OUT_1,
1174
TNETV107X_LCD_PD22_2,
1176
TNETV107X_LCD_PD23_2,
1178
TNETV107X_LCD_PD16_1,
1179
TNETV107X_USB0_RXERR,
1181
TNETV107X_LCD_PD17_1,
1182
TNETV107X_TDM_CLK_IN_1,
1185
TNETV107X_24M_CLK_OUT_2,
1187
TNETV107X_LCD_PD19_1,
1188
TNETV107X_USB1_RXERR,
1189
TNETV107X_ETH_PLL_CLK,
1192
TNETV107X_AIC_MUTE_STAT_N,
1194
TNETV107X_AIC_HNS_EN_N,
1196
TNETV107X_AIC_HDS_EN_STAT_N,
1198
TNETV107X_AIC_HNF_EN_STAT_N,
1202
#define PINMUX(x) (4 * (x))
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#ifdef CONFIG_DAVINCI_MUX
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/* setup pin muxing */
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extern int davinci_cfg_reg(unsigned long reg_cfg);
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extern int davinci_cfg_reg_list(const short pins[]);
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/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
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static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
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static inline int davinci_cfg_reg_list(const short pins[])
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#endif /* __INC_MACH_MUX_H */