2
* Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4
* FIXME According to the usermanual the status bits in the status register
5
* are only updated when the peripherals access the FIFO and not when the
6
* CPU access them. So since we use this bits to know when we stop writing
7
* and reading, they may not be updated in-time and a race condition may
8
* exists. But I haven't be able to prove this and I don't care. But if
9
* any problem arises, it might worth checking. The TX/RX FIFO Stats
10
* registers should be used in addition.
11
* Update: Actually, they seem updated ... At least the bits we use.
14
* Maintainer : Sylvain Munaut <tnt@246tNt.com>
16
* Some of the code has been inspired/copied from the 2.4 code written
17
* by Dale Farnsworth <dfarnsworth@mvista.com>.
19
* Copyright (C) 2008 Freescale Semiconductor Inc.
20
* John Rigby <jrigby@gmail.com>
21
* Added support for MPC5121
22
* Copyright (C) 2006 Secret Lab Technologies Ltd.
23
* Grant Likely <grant.likely@secretlab.ca>
24
* Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25
* Copyright (C) 2003 MontaVista, Software, Inc.
27
* This file is licensed under the terms of the GNU General Public License
28
* version 2. This program is licensed "as is" without any warranty of any
29
* kind, whether express or implied.
34
#include <linux/device.h>
35
#include <linux/module.h>
36
#include <linux/tty.h>
37
#include <linux/tty_flip.h>
38
#include <linux/serial.h>
39
#include <linux/sysrq.h>
40
#include <linux/console.h>
41
#include <linux/delay.h>
44
#include <linux/of_platform.h>
45
#include <linux/clk.h>
47
#include <asm/mpc52xx.h>
48
#include <asm/mpc52xx_psc.h>
50
#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54
#include <linux/serial_core.h>
57
/* We've been assigned a range on the "Low-density serial ports" major */
58
#define SERIAL_PSC_MAJOR 204
59
#define SERIAL_PSC_MINOR 148
62
#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
65
static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
66
/* Rem: - We use the read_status_mask as a shadow of
67
* psc->mpc52xx_psc_imr
68
* - It's important that is array is all zero on start as we
69
* use it to know if it's initialized or not ! If it's not sure
70
* it's cleared, then a memset(...,0,...) should be added to
74
/* lookup table for matching device nodes to index numbers */
75
static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
77
static void mpc52xx_uart_of_enumerate(void);
80
#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
83
/* Forward declaration of the interruption handling routine */
84
static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
85
static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
88
/* Simple macro to test if a port is console or not. This one is taken
89
* for serial_core.c and maybe should be moved to serial_core.h ? */
90
#ifdef CONFIG_SERIAL_CORE_CONSOLE
91
#define uart_console(port) \
92
((port)->cons && (port)->cons->index == (port)->line)
94
#define uart_console(port) (0)
97
/* ======================================================================== */
98
/* PSC fifo operations for isolating differences between 52xx and 512x */
99
/* ======================================================================== */
102
void (*fifo_init)(struct uart_port *port);
103
int (*raw_rx_rdy)(struct uart_port *port);
104
int (*raw_tx_rdy)(struct uart_port *port);
105
int (*rx_rdy)(struct uart_port *port);
106
int (*tx_rdy)(struct uart_port *port);
107
int (*tx_empty)(struct uart_port *port);
108
void (*stop_rx)(struct uart_port *port);
109
void (*start_tx)(struct uart_port *port);
110
void (*stop_tx)(struct uart_port *port);
111
void (*rx_clr_irq)(struct uart_port *port);
112
void (*tx_clr_irq)(struct uart_port *port);
113
void (*write_char)(struct uart_port *port, unsigned char c);
114
unsigned char (*read_char)(struct uart_port *port);
115
void (*cw_disable_ints)(struct uart_port *port);
116
void (*cw_restore_ints)(struct uart_port *port);
117
unsigned int (*set_baudrate)(struct uart_port *port,
118
struct ktermios *new,
119
struct ktermios *old);
120
int (*clock)(struct uart_port *port, int enable);
121
int (*fifoc_init)(void);
122
void (*fifoc_uninit)(void);
123
void (*get_irq)(struct uart_port *, struct device_node *);
124
irqreturn_t (*handle_irq)(struct uart_port *port);
127
/* setting the prescaler and divisor reg is common for all chips */
128
static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
129
u16 prescaler, unsigned int divisor)
131
/* select prescaler */
132
out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
133
out_8(&psc->ctur, divisor >> 8);
134
out_8(&psc->ctlr, divisor & 0xff);
137
#ifdef CONFIG_PPC_MPC52xx
138
#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
139
static void mpc52xx_psc_fifo_init(struct uart_port *port)
141
struct mpc52xx_psc __iomem *psc = PSC(port);
142
struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
144
out_8(&fifo->rfcntl, 0x00);
145
out_be16(&fifo->rfalarm, 0x1ff);
146
out_8(&fifo->tfcntl, 0x07);
147
out_be16(&fifo->tfalarm, 0x80);
149
port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
150
out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
153
static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
155
return in_be16(&PSC(port)->mpc52xx_psc_status)
156
& MPC52xx_PSC_SR_RXRDY;
159
static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
161
return in_be16(&PSC(port)->mpc52xx_psc_status)
162
& MPC52xx_PSC_SR_TXRDY;
166
static int mpc52xx_psc_rx_rdy(struct uart_port *port)
168
return in_be16(&PSC(port)->mpc52xx_psc_isr)
169
& port->read_status_mask
170
& MPC52xx_PSC_IMR_RXRDY;
173
static int mpc52xx_psc_tx_rdy(struct uart_port *port)
175
return in_be16(&PSC(port)->mpc52xx_psc_isr)
176
& port->read_status_mask
177
& MPC52xx_PSC_IMR_TXRDY;
180
static int mpc52xx_psc_tx_empty(struct uart_port *port)
182
return in_be16(&PSC(port)->mpc52xx_psc_status)
183
& MPC52xx_PSC_SR_TXEMP;
186
static void mpc52xx_psc_start_tx(struct uart_port *port)
188
port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
189
out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
192
static void mpc52xx_psc_stop_tx(struct uart_port *port)
194
port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
195
out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
198
static void mpc52xx_psc_stop_rx(struct uart_port *port)
200
port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
201
out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
204
static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
208
static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
212
static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
214
out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
217
static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
219
return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
222
static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
224
out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
227
static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
229
out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
232
static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
233
struct ktermios *new,
234
struct ktermios *old)
237
unsigned int divisor;
239
/* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
240
baud = uart_get_baud_rate(port, new, old,
241
port->uartclk / (32 * 0xffff) + 1,
243
divisor = (port->uartclk + 16 * baud) / (32 * baud);
245
/* enable the /32 prescaler and set the divisor */
246
mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
250
static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
251
struct ktermios *new,
252
struct ktermios *old)
255
unsigned int divisor;
258
/* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
260
baud = uart_get_baud_rate(port, new, old,
261
port->uartclk / (32 * 0xffff) + 1,
263
divisor = (port->uartclk + 2 * baud) / (4 * baud);
265
/* select the proper prescaler and set the divisor */
266
if (divisor > 0xffff) {
267
divisor = (divisor + 4) / 8;
268
prescaler = 0xdd00; /* /32 */
270
prescaler = 0xff00; /* /4 */
271
mpc52xx_set_divisor(PSC(port), prescaler, divisor);
275
static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
278
port->irq = irq_of_parse_and_map(np, 0);
281
/* 52xx specific interrupt handler. The caller holds the port lock */
282
static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
284
return mpc5xxx_uart_process_int(port);
287
static struct psc_ops mpc52xx_psc_ops = {
288
.fifo_init = mpc52xx_psc_fifo_init,
289
.raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
290
.raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
291
.rx_rdy = mpc52xx_psc_rx_rdy,
292
.tx_rdy = mpc52xx_psc_tx_rdy,
293
.tx_empty = mpc52xx_psc_tx_empty,
294
.stop_rx = mpc52xx_psc_stop_rx,
295
.start_tx = mpc52xx_psc_start_tx,
296
.stop_tx = mpc52xx_psc_stop_tx,
297
.rx_clr_irq = mpc52xx_psc_rx_clr_irq,
298
.tx_clr_irq = mpc52xx_psc_tx_clr_irq,
299
.write_char = mpc52xx_psc_write_char,
300
.read_char = mpc52xx_psc_read_char,
301
.cw_disable_ints = mpc52xx_psc_cw_disable_ints,
302
.cw_restore_ints = mpc52xx_psc_cw_restore_ints,
303
.set_baudrate = mpc5200_psc_set_baudrate,
304
.get_irq = mpc52xx_psc_get_irq,
305
.handle_irq = mpc52xx_psc_handle_irq,
308
static struct psc_ops mpc5200b_psc_ops = {
309
.fifo_init = mpc52xx_psc_fifo_init,
310
.raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
311
.raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
312
.rx_rdy = mpc52xx_psc_rx_rdy,
313
.tx_rdy = mpc52xx_psc_tx_rdy,
314
.tx_empty = mpc52xx_psc_tx_empty,
315
.stop_rx = mpc52xx_psc_stop_rx,
316
.start_tx = mpc52xx_psc_start_tx,
317
.stop_tx = mpc52xx_psc_stop_tx,
318
.rx_clr_irq = mpc52xx_psc_rx_clr_irq,
319
.tx_clr_irq = mpc52xx_psc_tx_clr_irq,
320
.write_char = mpc52xx_psc_write_char,
321
.read_char = mpc52xx_psc_read_char,
322
.cw_disable_ints = mpc52xx_psc_cw_disable_ints,
323
.cw_restore_ints = mpc52xx_psc_cw_restore_ints,
324
.set_baudrate = mpc5200b_psc_set_baudrate,
325
.get_irq = mpc52xx_psc_get_irq,
326
.handle_irq = mpc52xx_psc_handle_irq,
329
#endif /* CONFIG_MPC52xx */
331
#ifdef CONFIG_PPC_MPC512x
332
#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
334
/* PSC FIFO Controller for mpc512x */
343
static struct psc_fifoc __iomem *psc_fifoc;
344
static unsigned int psc_fifoc_irq;
346
static void mpc512x_psc_fifo_init(struct uart_port *port)
349
out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
351
out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
352
out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
353
out_be32(&FIFO_512x(port)->txalarm, 1);
354
out_be32(&FIFO_512x(port)->tximr, 0);
356
out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
357
out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
358
out_be32(&FIFO_512x(port)->rxalarm, 1);
359
out_be32(&FIFO_512x(port)->rximr, 0);
361
out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
362
out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
365
static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
367
return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
370
static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
372
return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
375
static int mpc512x_psc_rx_rdy(struct uart_port *port)
377
return in_be32(&FIFO_512x(port)->rxsr)
378
& in_be32(&FIFO_512x(port)->rximr)
379
& MPC512x_PSC_FIFO_ALARM;
382
static int mpc512x_psc_tx_rdy(struct uart_port *port)
384
return in_be32(&FIFO_512x(port)->txsr)
385
& in_be32(&FIFO_512x(port)->tximr)
386
& MPC512x_PSC_FIFO_ALARM;
389
static int mpc512x_psc_tx_empty(struct uart_port *port)
391
return in_be32(&FIFO_512x(port)->txsr)
392
& MPC512x_PSC_FIFO_EMPTY;
395
static void mpc512x_psc_stop_rx(struct uart_port *port)
397
unsigned long rx_fifo_imr;
399
rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
400
rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
401
out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
404
static void mpc512x_psc_start_tx(struct uart_port *port)
406
unsigned long tx_fifo_imr;
408
tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
409
tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
410
out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
413
static void mpc512x_psc_stop_tx(struct uart_port *port)
415
unsigned long tx_fifo_imr;
417
tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
418
tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
419
out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
422
static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
424
out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
427
static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
429
out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
432
static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
434
out_8(&FIFO_512x(port)->txdata_8, c);
437
static unsigned char mpc512x_psc_read_char(struct uart_port *port)
439
return in_8(&FIFO_512x(port)->rxdata_8);
442
static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
444
port->read_status_mask =
445
in_be32(&FIFO_512x(port)->tximr) << 16 |
446
in_be32(&FIFO_512x(port)->rximr);
447
out_be32(&FIFO_512x(port)->tximr, 0);
448
out_be32(&FIFO_512x(port)->rximr, 0);
451
static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
453
out_be32(&FIFO_512x(port)->tximr,
454
(port->read_status_mask >> 16) & 0x7f);
455
out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
458
static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
459
struct ktermios *new,
460
struct ktermios *old)
463
unsigned int divisor;
466
* The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
467
* pg. 30-10 that the chip supports a /32 and a /10 prescaler.
468
* Furthermore, it states that "After reset, the prescaler by 10
469
* for the UART mode is selected", but the reset register value is
470
* 0x0000 which means a /32 prescaler. This is wrong.
472
* In reality using /32 prescaler doesn't work, as it is not supported!
473
* Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
474
* Chapter 4.1 PSC in UART Mode.
475
* Calculate with a /16 prescaler here.
478
/* uartclk contains the ips freq */
479
baud = uart_get_baud_rate(port, new, old,
480
port->uartclk / (16 * 0xffff) + 1,
482
divisor = (port->uartclk + 8 * baud) / (16 * baud);
484
/* enable the /16 prescaler and set the divisor */
485
mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
489
/* Init PSC FIFO Controller */
490
static int __init mpc512x_psc_fifoc_init(void)
492
struct device_node *np;
494
np = of_find_compatible_node(NULL, NULL,
495
"fsl,mpc5121-psc-fifo");
497
pr_err("%s: Can't find FIFOC node\n", __func__);
501
psc_fifoc = of_iomap(np, 0);
503
pr_err("%s: Can't map FIFOC\n", __func__);
508
psc_fifoc_irq = irq_of_parse_and_map(np, 0);
510
if (psc_fifoc_irq == NO_IRQ) {
511
pr_err("%s: Can't get FIFOC irq\n", __func__);
519
static void __exit mpc512x_psc_fifoc_uninit(void)
524
/* 512x specific interrupt handler. The caller holds the port lock */
525
static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
527
unsigned long fifoc_int;
530
/* Read pending PSC FIFOC interrupts */
531
fifoc_int = in_be32(&psc_fifoc->fifoc_int);
533
/* Check if it is an interrupt for this port */
534
psc_num = (port->mapbase & 0xf00) >> 8;
535
if (test_bit(psc_num, &fifoc_int) ||
536
test_bit(psc_num + 16, &fifoc_int))
537
return mpc5xxx_uart_process_int(port);
542
static int mpc512x_psc_clock(struct uart_port *port, int enable)
548
if (uart_console(port))
551
psc_num = (port->mapbase & 0xf00) >> 8;
552
snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
553
psc_clk = clk_get(port->dev, clk_name);
554
if (IS_ERR(psc_clk)) {
555
dev_err(port->dev, "Failed to get PSC clock entry!\n");
559
dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
564
clk_disable(psc_clk);
569
static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
571
port->irqflags = IRQF_SHARED;
572
port->irq = psc_fifoc_irq;
575
static struct psc_ops mpc512x_psc_ops = {
576
.fifo_init = mpc512x_psc_fifo_init,
577
.raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
578
.raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
579
.rx_rdy = mpc512x_psc_rx_rdy,
580
.tx_rdy = mpc512x_psc_tx_rdy,
581
.tx_empty = mpc512x_psc_tx_empty,
582
.stop_rx = mpc512x_psc_stop_rx,
583
.start_tx = mpc512x_psc_start_tx,
584
.stop_tx = mpc512x_psc_stop_tx,
585
.rx_clr_irq = mpc512x_psc_rx_clr_irq,
586
.tx_clr_irq = mpc512x_psc_tx_clr_irq,
587
.write_char = mpc512x_psc_write_char,
588
.read_char = mpc512x_psc_read_char,
589
.cw_disable_ints = mpc512x_psc_cw_disable_ints,
590
.cw_restore_ints = mpc512x_psc_cw_restore_ints,
591
.set_baudrate = mpc512x_psc_set_baudrate,
592
.clock = mpc512x_psc_clock,
593
.fifoc_init = mpc512x_psc_fifoc_init,
594
.fifoc_uninit = mpc512x_psc_fifoc_uninit,
595
.get_irq = mpc512x_psc_get_irq,
596
.handle_irq = mpc512x_psc_handle_irq,
600
static struct psc_ops *psc_ops;
602
/* ======================================================================== */
603
/* UART operations */
604
/* ======================================================================== */
607
mpc52xx_uart_tx_empty(struct uart_port *port)
609
return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
613
mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
615
if (mctrl & TIOCM_RTS)
616
out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
618
out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
622
mpc52xx_uart_get_mctrl(struct uart_port *port)
624
unsigned int ret = TIOCM_DSR;
625
u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
627
if (!(status & MPC52xx_PSC_CTS))
629
if (!(status & MPC52xx_PSC_DCD))
636
mpc52xx_uart_stop_tx(struct uart_port *port)
638
/* port->lock taken by caller */
639
psc_ops->stop_tx(port);
643
mpc52xx_uart_start_tx(struct uart_port *port)
645
/* port->lock taken by caller */
646
psc_ops->start_tx(port);
650
mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
653
spin_lock_irqsave(&port->lock, flags);
657
/* Make sure tx interrupts are on */
658
/* Truly necessary ??? They should be anyway */
659
psc_ops->start_tx(port);
662
spin_unlock_irqrestore(&port->lock, flags);
666
mpc52xx_uart_stop_rx(struct uart_port *port)
668
/* port->lock taken by caller */
669
psc_ops->stop_rx(port);
673
mpc52xx_uart_enable_ms(struct uart_port *port)
675
struct mpc52xx_psc __iomem *psc = PSC(port);
677
/* clear D_*-bits by reading them */
678
in_8(&psc->mpc52xx_psc_ipcr);
679
/* enable CTS and DCD as IPC interrupts */
680
out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
682
port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
683
out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
687
mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
690
spin_lock_irqsave(&port->lock, flags);
693
out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
695
out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
697
spin_unlock_irqrestore(&port->lock, flags);
701
mpc52xx_uart_startup(struct uart_port *port)
703
struct mpc52xx_psc __iomem *psc = PSC(port);
706
if (psc_ops->clock) {
707
ret = psc_ops->clock(port, 1);
713
ret = request_irq(port->irq, mpc52xx_uart_int,
714
port->irqflags, "mpc52xx_psc_uart", port);
718
/* Reset/activate the port, clear and enable interrupts */
719
out_8(&psc->command, MPC52xx_PSC_RST_RX);
720
out_8(&psc->command, MPC52xx_PSC_RST_TX);
722
out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
724
psc_ops->fifo_init(port);
726
out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
727
out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
733
mpc52xx_uart_shutdown(struct uart_port *port)
735
struct mpc52xx_psc __iomem *psc = PSC(port);
737
/* Shut down the port. Leave TX active if on a console port */
738
out_8(&psc->command, MPC52xx_PSC_RST_RX);
739
if (!uart_console(port))
740
out_8(&psc->command, MPC52xx_PSC_RST_TX);
742
port->read_status_mask = 0;
743
out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
746
psc_ops->clock(port, 0);
748
/* Release interrupt */
749
free_irq(port->irq, port);
753
mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
754
struct ktermios *old)
756
struct mpc52xx_psc __iomem *psc = PSC(port);
758
unsigned char mr1, mr2;
762
/* Prepare what we're gonna write */
765
switch (new->c_cflag & CSIZE) {
766
case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
768
case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
770
case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
773
default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
776
if (new->c_cflag & PARENB) {
777
mr1 |= (new->c_cflag & PARODD) ?
778
MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
780
mr1 |= MPC52xx_PSC_MODE_PARNONE;
785
if (new->c_cflag & CSTOPB)
786
mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
788
mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
789
MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
790
MPC52xx_PSC_MODE_ONE_STOP;
792
if (new->c_cflag & CRTSCTS) {
793
mr1 |= MPC52xx_PSC_MODE_RXRTS;
794
mr2 |= MPC52xx_PSC_MODE_TXCTS;
798
spin_lock_irqsave(&port->lock, flags);
800
/* Do our best to flush TX & RX, so we don't lose anything */
801
/* But we don't wait indefinitely ! */
802
j = 5000000; /* Maximum wait */
803
/* FIXME Can't receive chars since set_termios might be called at early
804
* boot for the console, all stuff is not yet ready to receive at that
805
* time and that just makes the kernel oops */
806
/* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
807
while (!mpc52xx_uart_tx_empty(port) && --j)
811
printk(KERN_ERR "mpc52xx_uart.c: "
812
"Unable to flush RX & TX fifos in-time in set_termios."
813
"Some chars may have been lost.\n");
815
/* Reset the TX & RX */
816
out_8(&psc->command, MPC52xx_PSC_RST_RX);
817
out_8(&psc->command, MPC52xx_PSC_RST_TX);
819
/* Send new mode settings */
820
out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
821
out_8(&psc->mode, mr1);
822
out_8(&psc->mode, mr2);
823
baud = psc_ops->set_baudrate(port, new, old);
825
/* Update the per-port timeout */
826
uart_update_timeout(port, new->c_cflag, baud);
828
if (UART_ENABLE_MS(port, new->c_cflag))
829
mpc52xx_uart_enable_ms(port);
831
/* Reenable TX & RX */
832
out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
833
out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
835
/* We're all set, release the lock */
836
spin_unlock_irqrestore(&port->lock, flags);
840
mpc52xx_uart_type(struct uart_port *port)
843
* We keep using PORT_MPC52xx for historic reasons although it applies
844
* for MPC512x, too, but print "MPC5xxx" to not irritate users
846
return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
850
mpc52xx_uart_release_port(struct uart_port *port)
852
/* remapped by us ? */
853
if (port->flags & UPF_IOREMAP) {
854
iounmap(port->membase);
855
port->membase = NULL;
858
release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
862
mpc52xx_uart_request_port(struct uart_port *port)
866
if (port->flags & UPF_IOREMAP) /* Need to remap ? */
867
port->membase = ioremap(port->mapbase,
868
sizeof(struct mpc52xx_psc));
873
err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
874
"mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
876
if (err && (port->flags & UPF_IOREMAP)) {
877
iounmap(port->membase);
878
port->membase = NULL;
885
mpc52xx_uart_config_port(struct uart_port *port, int flags)
887
if ((flags & UART_CONFIG_TYPE)
888
&& (mpc52xx_uart_request_port(port) == 0))
889
port->type = PORT_MPC52xx;
893
mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
895
if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
898
if ((ser->irq != port->irq) ||
899
(ser->io_type != UPIO_MEM) ||
900
(ser->baud_base != port->uartclk) ||
901
(ser->iomem_base != (void *)port->mapbase) ||
909
static struct uart_ops mpc52xx_uart_ops = {
910
.tx_empty = mpc52xx_uart_tx_empty,
911
.set_mctrl = mpc52xx_uart_set_mctrl,
912
.get_mctrl = mpc52xx_uart_get_mctrl,
913
.stop_tx = mpc52xx_uart_stop_tx,
914
.start_tx = mpc52xx_uart_start_tx,
915
.send_xchar = mpc52xx_uart_send_xchar,
916
.stop_rx = mpc52xx_uart_stop_rx,
917
.enable_ms = mpc52xx_uart_enable_ms,
918
.break_ctl = mpc52xx_uart_break_ctl,
919
.startup = mpc52xx_uart_startup,
920
.shutdown = mpc52xx_uart_shutdown,
921
.set_termios = mpc52xx_uart_set_termios,
922
/* .pm = mpc52xx_uart_pm, Not supported yet */
923
/* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
924
.type = mpc52xx_uart_type,
925
.release_port = mpc52xx_uart_release_port,
926
.request_port = mpc52xx_uart_request_port,
927
.config_port = mpc52xx_uart_config_port,
928
.verify_port = mpc52xx_uart_verify_port
932
/* ======================================================================== */
933
/* Interrupt handling */
934
/* ======================================================================== */
937
mpc52xx_uart_int_rx_chars(struct uart_port *port)
939
struct tty_struct *tty = port->state->port.tty;
940
unsigned char ch, flag;
941
unsigned short status;
943
/* While we can read, do so ! */
944
while (psc_ops->raw_rx_rdy(port)) {
946
ch = psc_ops->read_char(port);
948
/* Handle sysreq char */
950
if (uart_handle_sysrq_char(port, ch)) {
961
status = in_be16(&PSC(port)->mpc52xx_psc_status);
963
if (status & (MPC52xx_PSC_SR_PE |
965
MPC52xx_PSC_SR_RB)) {
967
if (status & MPC52xx_PSC_SR_RB) {
969
uart_handle_break(port);
971
} else if (status & MPC52xx_PSC_SR_PE) {
973
port->icount.parity++;
975
else if (status & MPC52xx_PSC_SR_FE) {
977
port->icount.frame++;
980
/* Clear error condition */
981
out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
984
tty_insert_flip_char(tty, ch, flag);
985
if (status & MPC52xx_PSC_SR_OE) {
987
* Overrun is special, since it's
988
* reported immediately, and doesn't
989
* affect the current character
991
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
992
port->icount.overrun++;
996
spin_unlock(&port->lock);
997
tty_flip_buffer_push(tty);
998
spin_lock(&port->lock);
1000
return psc_ops->raw_rx_rdy(port);
1004
mpc52xx_uart_int_tx_chars(struct uart_port *port)
1006
struct circ_buf *xmit = &port->state->xmit;
1008
/* Process out of band chars */
1010
psc_ops->write_char(port, port->x_char);
1016
/* Nothing to do ? */
1017
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1018
mpc52xx_uart_stop_tx(port);
1023
while (psc_ops->raw_tx_rdy(port)) {
1024
psc_ops->write_char(port, xmit->buf[xmit->tail]);
1025
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1027
if (uart_circ_empty(xmit))
1032
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1033
uart_write_wakeup(port);
1035
/* Maybe we're done after all */
1036
if (uart_circ_empty(xmit)) {
1037
mpc52xx_uart_stop_tx(port);
1045
mpc5xxx_uart_process_int(struct uart_port *port)
1047
unsigned long pass = ISR_PASS_LIMIT;
1048
unsigned int keepgoing;
1051
/* While we have stuff to do, we continue */
1053
/* If we don't find anything to do, we stop */
1056
psc_ops->rx_clr_irq(port);
1057
if (psc_ops->rx_rdy(port))
1058
keepgoing |= mpc52xx_uart_int_rx_chars(port);
1060
psc_ops->tx_clr_irq(port);
1061
if (psc_ops->tx_rdy(port))
1062
keepgoing |= mpc52xx_uart_int_tx_chars(port);
1064
status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
1065
if (status & MPC52xx_PSC_D_DCD)
1066
uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1068
if (status & MPC52xx_PSC_D_CTS)
1069
uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1071
/* Limit number of iteration */
1075
} while (keepgoing);
1081
mpc52xx_uart_int(int irq, void *dev_id)
1083
struct uart_port *port = dev_id;
1086
spin_lock(&port->lock);
1088
ret = psc_ops->handle_irq(port);
1090
spin_unlock(&port->lock);
1095
/* ======================================================================== */
1096
/* Console ( if applicable ) */
1097
/* ======================================================================== */
1099
#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1102
mpc52xx_console_get_options(struct uart_port *port,
1103
int *baud, int *parity, int *bits, int *flow)
1105
struct mpc52xx_psc __iomem *psc = PSC(port);
1108
pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1110
/* Read the mode registers */
1111
out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1112
mr1 = in_8(&psc->mode);
1114
/* CT{U,L}R are write-only ! */
1115
*baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1118
switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1119
case MPC52xx_PSC_MODE_5_BITS:
1122
case MPC52xx_PSC_MODE_6_BITS:
1125
case MPC52xx_PSC_MODE_7_BITS:
1128
case MPC52xx_PSC_MODE_8_BITS:
1133
if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1136
*parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1140
mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1142
struct uart_port *port = &mpc52xx_uart_ports[co->index];
1145
/* Disable interrupts */
1146
psc_ops->cw_disable_ints(port);
1148
/* Wait the TX buffer to be empty */
1149
j = 5000000; /* Maximum wait */
1150
while (!mpc52xx_uart_tx_empty(port) && --j)
1153
/* Write all the chars */
1154
for (i = 0; i < count; i++, s++) {
1155
/* Line return handling */
1157
psc_ops->write_char(port, '\r');
1160
psc_ops->write_char(port, *s);
1162
/* Wait the TX buffer to be empty */
1163
j = 20000; /* Maximum wait */
1164
while (!mpc52xx_uart_tx_empty(port) && --j)
1168
/* Restore interrupt state */
1169
psc_ops->cw_restore_ints(port);
1174
mpc52xx_console_setup(struct console *co, char *options)
1176
struct uart_port *port = &mpc52xx_uart_ports[co->index];
1177
struct device_node *np = mpc52xx_uart_nodes[co->index];
1178
unsigned int uartclk;
1179
struct resource res;
1182
int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1187
pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1188
co, co->index, options);
1190
if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1191
pr_debug("PSC%x out of range\n", co->index);
1196
pr_debug("PSC%x not found in device tree\n", co->index);
1200
pr_debug("Console on ttyPSC%x is %s\n",
1201
co->index, mpc52xx_uart_nodes[co->index]->full_name);
1203
/* Fetch register locations */
1204
ret = of_address_to_resource(np, 0, &res);
1206
pr_debug("Could not get resources for PSC%x\n", co->index);
1210
uartclk = mpc5xxx_get_bus_frequency(np);
1212
pr_debug("Could not find uart clock frequency!\n");
1216
/* Basic port init. Needed since we use some uart_??? func before
1217
* real init for early access */
1218
spin_lock_init(&port->lock);
1219
port->uartclk = uartclk;
1220
port->ops = &mpc52xx_uart_ops;
1221
port->mapbase = res.start;
1222
port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1223
port->irq = irq_of_parse_and_map(np, 0);
1225
if (port->membase == NULL)
1228
pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1229
(void *)port->mapbase, port->membase,
1230
port->irq, port->uartclk);
1232
/* Setup the port parameters accoding to options */
1234
uart_parse_options(options, &baud, &parity, &bits, &flow);
1236
mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1238
pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1239
baud, bits, parity, flow);
1241
return uart_set_options(port, co, baud, parity, bits, flow);
1245
static struct uart_driver mpc52xx_uart_driver;
1247
static struct console mpc52xx_console = {
1249
.write = mpc52xx_console_write,
1250
.device = uart_console_device,
1251
.setup = mpc52xx_console_setup,
1252
.flags = CON_PRINTBUFFER,
1253
.index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1254
.data = &mpc52xx_uart_driver,
1259
mpc52xx_console_init(void)
1261
mpc52xx_uart_of_enumerate();
1262
register_console(&mpc52xx_console);
1266
console_initcall(mpc52xx_console_init);
1268
#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1270
#define MPC52xx_PSC_CONSOLE NULL
1274
/* ======================================================================== */
1276
/* ======================================================================== */
1278
static struct uart_driver mpc52xx_uart_driver = {
1279
.driver_name = "mpc52xx_psc_uart",
1280
.dev_name = "ttyPSC",
1281
.major = SERIAL_PSC_MAJOR,
1282
.minor = SERIAL_PSC_MINOR,
1283
.nr = MPC52xx_PSC_MAXNUM,
1284
.cons = MPC52xx_PSC_CONSOLE,
1287
/* ======================================================================== */
1288
/* OF Platform Driver */
1289
/* ======================================================================== */
1291
static struct of_device_id mpc52xx_uart_of_match[] = {
1292
#ifdef CONFIG_PPC_MPC52xx
1293
{ .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1294
{ .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1295
/* binding used by old lite5200 device trees: */
1296
{ .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1297
/* binding used by efika: */
1298
{ .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1300
#ifdef CONFIG_PPC_MPC512x
1301
{ .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1306
static int __devinit mpc52xx_uart_of_probe(struct platform_device *op)
1309
unsigned int uartclk;
1310
struct uart_port *port = NULL;
1311
struct resource res;
1314
/* Check validity & presence */
1315
for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1316
if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1318
if (idx >= MPC52xx_PSC_MAXNUM)
1320
pr_debug("Found %s assigned to ttyPSC%x\n",
1321
mpc52xx_uart_nodes[idx]->full_name, idx);
1323
/* set the uart clock to the input clock of the psc, the different
1324
* prescalers are taken into account in the set_baudrate() methods
1325
* of the respective chip */
1326
uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1328
dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1332
/* Init the port structure */
1333
port = &mpc52xx_uart_ports[idx];
1335
spin_lock_init(&port->lock);
1336
port->uartclk = uartclk;
1337
port->fifosize = 512;
1338
port->iotype = UPIO_MEM;
1339
port->flags = UPF_BOOT_AUTOCONF |
1340
(uart_console(port) ? 0 : UPF_IOREMAP);
1342
port->ops = &mpc52xx_uart_ops;
1343
port->dev = &op->dev;
1345
/* Search for IRQ and mapbase */
1346
ret = of_address_to_resource(op->dev.of_node, 0, &res);
1350
port->mapbase = res.start;
1351
if (!port->mapbase) {
1352
dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1356
psc_ops->get_irq(port, op->dev.of_node);
1357
if (port->irq == NO_IRQ) {
1358
dev_dbg(&op->dev, "Could not get irq\n");
1362
dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1363
(void *)port->mapbase, port->irq, port->uartclk);
1365
/* Add the port to the uart sub-system */
1366
ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1370
dev_set_drvdata(&op->dev, (void *)port);
1375
mpc52xx_uart_of_remove(struct platform_device *op)
1377
struct uart_port *port = dev_get_drvdata(&op->dev);
1378
dev_set_drvdata(&op->dev, NULL);
1381
uart_remove_one_port(&mpc52xx_uart_driver, port);
1388
mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1390
struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1393
uart_suspend_port(&mpc52xx_uart_driver, port);
1399
mpc52xx_uart_of_resume(struct platform_device *op)
1401
struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1404
uart_resume_port(&mpc52xx_uart_driver, port);
1411
mpc52xx_uart_of_assign(struct device_node *np)
1415
/* Find the first free PSC number */
1416
for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1417
if (mpc52xx_uart_nodes[i] == NULL) {
1419
mpc52xx_uart_nodes[i] = np;
1426
mpc52xx_uart_of_enumerate(void)
1428
static int enum_done;
1429
struct device_node *np;
1430
const struct of_device_id *match;
1436
/* Assign index to each PSC in device tree */
1437
for_each_matching_node(np, mpc52xx_uart_of_match) {
1438
match = of_match_node(mpc52xx_uart_of_match, np);
1439
psc_ops = match->data;
1440
mpc52xx_uart_of_assign(np);
1445
for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1446
if (mpc52xx_uart_nodes[i])
1447
pr_debug("%s assigned to ttyPSC%x\n",
1448
mpc52xx_uart_nodes[i]->full_name, i);
1452
MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1454
static struct platform_driver mpc52xx_uart_of_driver = {
1455
.probe = mpc52xx_uart_of_probe,
1456
.remove = mpc52xx_uart_of_remove,
1458
.suspend = mpc52xx_uart_of_suspend,
1459
.resume = mpc52xx_uart_of_resume,
1462
.name = "mpc52xx-psc-uart",
1463
.owner = THIS_MODULE,
1464
.of_match_table = mpc52xx_uart_of_match,
1469
/* ======================================================================== */
1471
/* ======================================================================== */
1474
mpc52xx_uart_init(void)
1478
printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1480
ret = uart_register_driver(&mpc52xx_uart_driver);
1482
printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1487
mpc52xx_uart_of_enumerate();
1490
* Map the PSC FIFO Controller and init if on MPC512x.
1492
if (psc_ops && psc_ops->fifoc_init) {
1493
ret = psc_ops->fifoc_init();
1498
ret = platform_driver_register(&mpc52xx_uart_of_driver);
1500
printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1502
uart_unregister_driver(&mpc52xx_uart_driver);
1510
mpc52xx_uart_exit(void)
1512
if (psc_ops->fifoc_uninit)
1513
psc_ops->fifoc_uninit();
1515
platform_driver_unregister(&mpc52xx_uart_of_driver);
1516
uart_unregister_driver(&mpc52xx_uart_driver);
1520
module_init(mpc52xx_uart_init);
1521
module_exit(mpc52xx_uart_exit);
1523
MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1524
MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1525
MODULE_LICENSE("GPL");