2
* linux/arch/arm/mm/alignment.c
4
* Copyright (C) 1995 Linus Torvalds
5
* Modifications for ARM processor (c) 1995-2001 Russell King
6
* Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7
* - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8
* Copyright (C) 1996, Cygnus Software Technologies Ltd.
10
* This program is free software; you can redistribute it and/or modify
11
* it under the terms of the GNU General Public License version 2 as
12
* published by the Free Software Foundation.
14
#include <linux/moduleparam.h>
15
#include <linux/compiler.h>
16
#include <linux/kernel.h>
17
#include <linux/errno.h>
18
#include <linux/string.h>
19
#include <linux/proc_fs.h>
20
#include <linux/seq_file.h>
21
#include <linux/init.h>
22
#include <linux/sched.h>
23
#include <linux/uaccess.h>
25
#include <asm/system.h>
26
#include <asm/unaligned.h>
31
* 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
32
* /proc/sys/debug/alignment, modified and integrated into
33
* Linux 2.1 by Russell King
35
* Speed optimisations and better fault handling by Russell King.
38
* This code is not portable to processors with late data abort handling.
40
#define CODING_BITS(i) (i & 0x0e000000)
42
#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
43
#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
44
#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
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#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
46
#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
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#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
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#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
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#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
53
#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
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#define RD_BITS(i) ((i >> 12) & 15) /* Rd */
55
#define RM_BITS(i) (i & 15) /* Rm */
57
#define REGMASK_BITS(i) (i & 0xffff)
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#define OFFSET_BITS(i) (i & 0x0fff)
60
#define IS_SHIFT(i) (i & 0x0ff0)
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#define SHIFT_BITS(i) ((i >> 7) & 0x1f)
62
#define SHIFT_TYPE(i) (i & 0x60)
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#define SHIFT_LSL 0x00
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#define SHIFT_LSR 0x20
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#define SHIFT_ASR 0x40
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#define SHIFT_RORRRX 0x60
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#define BAD_INSTR 0xdeadc0de
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/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
71
#define IS_T32(hi16) \
72
(((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
74
static unsigned long ai_user;
75
static unsigned long ai_sys;
76
static unsigned long ai_skipped;
77
static unsigned long ai_half;
78
static unsigned long ai_word;
79
static unsigned long ai_dword;
80
static unsigned long ai_multi;
81
static int ai_usermode;
83
core_param(alignment, ai_usermode, int, 0600);
85
#define UM_WARN (1 << 0)
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#define UM_FIXUP (1 << 1)
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#define UM_SIGNAL (1 << 2)
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/* Return true if and only if the ARMv6 unaligned access model is in use. */
90
static bool cpu_is_v6_unaligned(void)
92
return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
95
static int safe_usermode(int new_usermode, bool warn)
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* ARMv6 and later CPUs can perform unaligned accesses for
99
* most single load and store instructions up to word size.
100
* LDM, STM, LDRD and STRD still need to be handled.
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* Ignoring the alignment fault is not an option on these
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* CPUs since we spin re-faulting the instruction without
104
* making any progress.
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if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
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new_usermode |= UM_FIXUP;
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printk(KERN_WARNING "alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n");
116
#ifdef CONFIG_PROC_FS
117
static const char *usermode_action[] = {
126
static int alignment_proc_show(struct seq_file *m, void *v)
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seq_printf(m, "User:\t\t%lu\n", ai_user);
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seq_printf(m, "System:\t\t%lu\n", ai_sys);
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seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
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seq_printf(m, "Half:\t\t%lu\n", ai_half);
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seq_printf(m, "Word:\t\t%lu\n", ai_word);
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if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
134
seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
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seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
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seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
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usermode_action[ai_usermode]);
142
static int alignment_proc_open(struct inode *inode, struct file *file)
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return single_open(file, alignment_proc_show, NULL);
147
static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *pos)
153
if (get_user(mode, buffer))
155
if (mode >= '0' && mode <= '5')
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ai_usermode = safe_usermode(mode - '0', true);
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static const struct file_operations alignment_proc_fops = {
162
.open = alignment_proc_open,
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.release = single_release,
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.write = alignment_proc_write,
168
#endif /* CONFIG_PROC_FS */
182
#define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
183
#define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
184
#define NEXT_BYTE "ror #24"
187
#define FIRST_BYTE_16
188
#define FIRST_BYTE_32
189
#define NEXT_BYTE "lsr #8"
192
#define __get8_unaligned_check(ins,val,addr,err) \
194
ARM( "1: "ins" %1, [%2], #1\n" ) \
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THUMB( "1: "ins" %1, [%2]\n" ) \
196
THUMB( " add %2, %2, #1\n" ) \
198
" .pushsection .fixup,\"ax\"\n" \
203
" .pushsection __ex_table,\"a\"\n" \
207
: "=r" (err), "=&r" (val), "=r" (addr) \
208
: "0" (err), "2" (addr))
210
#define __get16_unaligned_check(ins,val,addr) \
212
unsigned int err = 0, v, a = addr; \
213
__get8_unaligned_check(ins,v,a,err); \
214
val = v << ((BE) ? 8 : 0); \
215
__get8_unaligned_check(ins,v,a,err); \
216
val |= v << ((BE) ? 0 : 8); \
221
#define get16_unaligned_check(val,addr) \
222
__get16_unaligned_check("ldrb",val,addr)
224
#define get16t_unaligned_check(val,addr) \
225
__get16_unaligned_check("ldrbt",val,addr)
227
#define __get32_unaligned_check(ins,val,addr) \
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unsigned int err = 0, v, a = addr; \
230
__get8_unaligned_check(ins,v,a,err); \
231
val = v << ((BE) ? 24 : 0); \
232
__get8_unaligned_check(ins,v,a,err); \
233
val |= v << ((BE) ? 16 : 8); \
234
__get8_unaligned_check(ins,v,a,err); \
235
val |= v << ((BE) ? 8 : 16); \
236
__get8_unaligned_check(ins,v,a,err); \
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val |= v << ((BE) ? 0 : 24); \
242
#define get32_unaligned_check(val,addr) \
243
__get32_unaligned_check("ldrb",val,addr)
245
#define get32t_unaligned_check(val,addr) \
246
__get32_unaligned_check("ldrbt",val,addr)
248
#define __put16_unaligned_check(ins,val,addr) \
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unsigned int err = 0, v = val, a = addr; \
251
__asm__( FIRST_BYTE_16 \
252
ARM( "1: "ins" %1, [%2], #1\n" ) \
253
THUMB( "1: "ins" %1, [%2]\n" ) \
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THUMB( " add %2, %2, #1\n" ) \
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" mov %1, %1, "NEXT_BYTE"\n" \
256
"2: "ins" %1, [%2]\n" \
258
" .pushsection .fixup,\"ax\"\n" \
263
" .pushsection __ex_table,\"a\"\n" \
268
: "=r" (err), "=&r" (v), "=&r" (a) \
269
: "0" (err), "1" (v), "2" (a)); \
274
#define put16_unaligned_check(val,addr) \
275
__put16_unaligned_check("strb",val,addr)
277
#define put16t_unaligned_check(val,addr) \
278
__put16_unaligned_check("strbt",val,addr)
280
#define __put32_unaligned_check(ins,val,addr) \
282
unsigned int err = 0, v = val, a = addr; \
283
__asm__( FIRST_BYTE_32 \
284
ARM( "1: "ins" %1, [%2], #1\n" ) \
285
THUMB( "1: "ins" %1, [%2]\n" ) \
286
THUMB( " add %2, %2, #1\n" ) \
287
" mov %1, %1, "NEXT_BYTE"\n" \
288
ARM( "2: "ins" %1, [%2], #1\n" ) \
289
THUMB( "2: "ins" %1, [%2]\n" ) \
290
THUMB( " add %2, %2, #1\n" ) \
291
" mov %1, %1, "NEXT_BYTE"\n" \
292
ARM( "3: "ins" %1, [%2], #1\n" ) \
293
THUMB( "3: "ins" %1, [%2]\n" ) \
294
THUMB( " add %2, %2, #1\n" ) \
295
" mov %1, %1, "NEXT_BYTE"\n" \
296
"4: "ins" %1, [%2]\n" \
298
" .pushsection .fixup,\"ax\"\n" \
303
" .pushsection __ex_table,\"a\"\n" \
310
: "=r" (err), "=&r" (v), "=&r" (a) \
311
: "0" (err), "1" (v), "2" (a)); \
316
#define put32_unaligned_check(val,addr) \
317
__put32_unaligned_check("strb", val, addr)
319
#define put32t_unaligned_check(val,addr) \
320
__put32_unaligned_check("strbt", val, addr)
323
do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
325
if (!LDST_U_BIT(instr))
326
offset.un = -offset.un;
328
if (!LDST_P_BIT(instr))
331
if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
332
regs->uregs[RN_BITS(instr)] = addr;
336
do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
338
unsigned int rd = RD_BITS(instr);
345
if (LDST_L_BIT(instr)) {
347
get16_unaligned_check(val, addr);
349
/* signed half-word? */
351
val = (signed long)((signed short) val);
353
regs->uregs[rd] = val;
355
put16_unaligned_check(regs->uregs[rd], addr);
360
if (LDST_L_BIT(instr)) {
362
get16t_unaligned_check(val, addr);
364
/* signed half-word? */
366
val = (signed long)((signed short) val);
368
regs->uregs[rd] = val;
370
put16t_unaligned_check(regs->uregs[rd], addr);
379
do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
380
struct pt_regs *regs)
382
unsigned int rd = RD_BITS(instr);
386
if ((instr & 0xfe000000) == 0xe8000000) {
387
/* ARMv7 Thumb-2 32-bit LDRD/STRD */
388
rd2 = (instr >> 8) & 0xf;
389
load = !!(LDST_L_BIT(instr));
390
} else if (((rd & 1) == 1) || (rd == 14))
393
load = ((instr & 0xf0) == 0xd0);
404
get32_unaligned_check(val, addr);
405
regs->uregs[rd] = val;
406
get32_unaligned_check(val, addr + 4);
407
regs->uregs[rd2] = val;
409
put32_unaligned_check(regs->uregs[rd], addr);
410
put32_unaligned_check(regs->uregs[rd2], addr + 4);
418
get32t_unaligned_check(val, addr);
419
regs->uregs[rd] = val;
420
get32t_unaligned_check(val, addr + 4);
421
regs->uregs[rd2] = val;
423
put32t_unaligned_check(regs->uregs[rd], addr);
424
put32t_unaligned_check(regs->uregs[rd2], addr + 4);
435
do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
437
unsigned int rd = RD_BITS(instr);
441
if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
444
if (LDST_L_BIT(instr)) {
446
get32_unaligned_check(val, addr);
447
regs->uregs[rd] = val;
449
put32_unaligned_check(regs->uregs[rd], addr);
453
if (LDST_L_BIT(instr)) {
455
get32t_unaligned_check(val, addr);
456
regs->uregs[rd] = val;
458
put32t_unaligned_check(regs->uregs[rd], addr);
466
* LDM/STM alignment handler.
468
* There are 4 variants of this instruction:
470
* B = rn pointer before instruction, A = rn pointer after instruction
471
* ------ increasing address ----->
472
* | | r0 | r1 | ... | rx | |
479
do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
481
unsigned int rd, rn, correction, nr_regs, regbits;
482
unsigned long eaddr, newaddr;
484
if (LDM_S_BIT(instr))
487
correction = 4; /* processor implementation defined */
488
regs->ARM_pc += correction;
492
/* count the number of registers in the mask to be transferred */
493
nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
496
newaddr = eaddr = regs->uregs[rn];
498
if (!LDST_U_BIT(instr))
501
if (!LDST_U_BIT(instr))
504
if (LDST_P_EQ_U(instr)) /* U = P */
508
* For alignment faults on the ARM922T/ARM920T the MMU makes
509
* the FSR (and hence addr) equal to the updated base address
510
* of the multiple access rather than the restored value.
511
* Switch this message off if we've got a ARM92[02], otherwise
512
* [ls]dm alignment faults are noisy!
514
#if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
516
* This is a "hint" - we already have eaddr worked out by the
520
printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
521
"addr = %08lx, eaddr = %08lx\n",
522
instruction_pointer(regs), instr, addr, eaddr);
527
if (user_mode(regs)) {
528
for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
529
regbits >>= 1, rd += 1)
531
if (LDST_L_BIT(instr)) {
533
get32t_unaligned_check(val, eaddr);
534
regs->uregs[rd] = val;
536
put32t_unaligned_check(regs->uregs[rd], eaddr);
540
for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
541
regbits >>= 1, rd += 1)
543
if (LDST_L_BIT(instr)) {
545
get32_unaligned_check(val, eaddr);
546
regs->uregs[rd] = val;
548
put32_unaligned_check(regs->uregs[rd], eaddr);
553
if (LDST_W_BIT(instr))
554
regs->uregs[rn] = newaddr;
555
if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
556
regs->ARM_pc -= correction;
560
regs->ARM_pc -= correction;
564
printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
569
* Convert Thumb ld/st instruction forms to equivalent ARM instructions so
570
* we can reuse ARM userland alignment fault fixups for Thumb.
572
* This implementation was initially based on the algorithm found in
573
* gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
574
* to convert only Thumb ld/st instruction forms to equivalent ARM forms.
577
* 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
578
* 2. If for some reason we're passed an non-ld/st Thumb instruction to
579
* decode, we return 0xdeadc0de. This should never happen under normal
580
* circumstances but if it does, we've got other problems to deal with
581
* elsewhere and we obviously can't fix those problems here.
585
thumb2arm(u16 tinstr)
587
u32 L = (tinstr & (1<<11)) >> 11;
589
switch ((tinstr & 0xf800) >> 11) {
590
/* 6.5.1 Format 1: */
591
case 0x6000 >> 11: /* 7.1.52 STR(1) */
592
case 0x6800 >> 11: /* 7.1.26 LDR(1) */
593
case 0x7000 >> 11: /* 7.1.55 STRB(1) */
594
case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
596
((tinstr & (1<<12)) << (22-12)) | /* fixup */
597
(L<<20) | /* L==1? */
598
((tinstr & (7<<0)) << (12-0)) | /* Rd */
599
((tinstr & (7<<3)) << (16-3)) | /* Rn */
600
((tinstr & (31<<6)) >> /* immed_5 */
601
(6 - ((tinstr & (1<<12)) ? 0 : 2)));
602
case 0x8000 >> 11: /* 7.1.57 STRH(1) */
603
case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
605
(L<<20) | /* L==1? */
606
((tinstr & (7<<0)) << (12-0)) | /* Rd */
607
((tinstr & (7<<3)) << (16-3)) | /* Rn */
608
((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
609
((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
611
/* 6.5.1 Format 2: */
615
static const u32 subset[8] = {
616
0xe7800000, /* 7.1.53 STR(2) */
617
0xe18000b0, /* 7.1.58 STRH(2) */
618
0xe7c00000, /* 7.1.56 STRB(2) */
619
0xe19000d0, /* 7.1.34 LDRSB */
620
0xe7900000, /* 7.1.27 LDR(2) */
621
0xe19000b0, /* 7.1.33 LDRH(2) */
622
0xe7d00000, /* 7.1.31 LDRB(2) */
623
0xe19000f0 /* 7.1.35 LDRSH */
625
return subset[(tinstr & (7<<9)) >> 9] |
626
((tinstr & (7<<0)) << (12-0)) | /* Rd */
627
((tinstr & (7<<3)) << (16-3)) | /* Rn */
628
((tinstr & (7<<6)) >> (6-0)); /* Rm */
631
/* 6.5.1 Format 3: */
632
case 0x4800 >> 11: /* 7.1.28 LDR(3) */
633
/* NOTE: This case is not technically possible. We're
634
* loading 32-bit memory data via PC relative
635
* addressing mode. So we can and should eliminate
636
* this case. But I'll leave it here for now.
639
((tinstr & (7<<8)) << (12-8)) | /* Rd */
640
((tinstr & 255) << (2-0)); /* immed_8 */
642
/* 6.5.1 Format 4: */
643
case 0x9000 >> 11: /* 7.1.54 STR(3) */
644
case 0x9800 >> 11: /* 7.1.29 LDR(4) */
646
(L<<20) | /* L==1? */
647
((tinstr & (7<<8)) << (12-8)) | /* Rd */
648
((tinstr & 255) << 2); /* immed_8 */
650
/* 6.6.1 Format 1: */
651
case 0xc000 >> 11: /* 7.1.51 STMIA */
652
case 0xc800 >> 11: /* 7.1.25 LDMIA */
654
u32 Rn = (tinstr & (7<<8)) >> 8;
655
u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
657
return 0xe8800000 | W | (L<<20) | (Rn<<16) |
661
/* 6.6.1 Format 2: */
662
case 0xb000 >> 11: /* 7.1.48 PUSH */
663
case 0xb800 >> 11: /* 7.1.47 POP */
664
if ((tinstr & (3 << 9)) == 0x0400) {
665
static const u32 subset[4] = {
666
0xe92d0000, /* STMDB sp!,{registers} */
667
0xe92d4000, /* STMDB sp!,{registers,lr} */
668
0xe8bd0000, /* LDMIA sp!,{registers} */
669
0xe8bd8000 /* LDMIA sp!,{registers,pc} */
671
return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
672
(tinstr & 255); /* register_list */
674
/* Else fall through for illegal instruction case */
682
* Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
683
* handlable by ARM alignment handler, also find the corresponding handler,
684
* so that we can reuse ARM userland alignment fault fixups for Thumb.
686
* @pinstr: original Thumb-2 instruction; returns new handlable instruction
687
* @regs: register context.
688
* @poffset: return offset from faulted addr for later writeback
691
* 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
692
* 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
695
do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
696
union offset_union *poffset)
698
unsigned long instr = *pinstr;
699
u16 tinst1 = (instr >> 16) & 0xffff;
700
u16 tinst2 = instr & 0xffff;
703
switch (tinst1 & 0xffe0) {
704
/* A6.3.5 Load/Store multiple */
705
case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
706
case 0xe8a0: /* ...above writeback version */
707
case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
708
case 0xe920: /* ...above writeback version */
709
/* no need offset decision since handler calculates it */
710
return do_alignment_ldmstm;
712
case 0xf840: /* POP/PUSH T3 (single register) */
713
if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
714
u32 L = !!(LDST_L_BIT(instr));
715
const u32 subset[2] = {
716
0xe92d0000, /* STMDB sp!,{registers} */
717
0xe8bd0000, /* LDMIA sp!,{registers} */
719
*pinstr = subset[L] | (1<<RD_BITS(instr));
720
return do_alignment_ldmstm;
722
/* Else fall through for illegal instruction case */
725
/* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
730
poffset->un = (tinst2 & 0xff) << 2;
733
return do_alignment_ldrdstrd;
736
* No need to handle load/store instructions up to word size
737
* since ARMv6 and later CPUs can perform unaligned accesses.
746
do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
748
union offset_union offset;
749
unsigned long instr = 0, instrptr;
750
int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
758
if (interrupts_enabled(regs))
761
instrptr = instruction_pointer(regs);
765
if (thumb_mode(regs)) {
766
fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
768
if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
772
fault = __get_user(tinst2, (u16 *)(instrptr+2));
773
instr = (tinstr << 16) | tinst2;
777
instr = thumb2arm(tinstr);
781
fault = __get_user(instr, (u32 *)instrptr);
796
regs->ARM_pc += isize;
798
switch (CODING_BITS(instr)) {
799
case 0x00000000: /* 3.13.4 load/store instruction extensions */
800
if (LDSTHD_I_BIT(instr))
801
offset.un = (instr & 0xf00) >> 4 | (instr & 15);
803
offset.un = regs->uregs[RM_BITS(instr)];
805
if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
806
(instr & 0x001000f0) == 0x001000f0) /* LDRSH */
807
handler = do_alignment_ldrhstrh;
808
else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
809
(instr & 0x001000f0) == 0x000000f0) /* STRD */
810
handler = do_alignment_ldrdstrd;
811
else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
817
case 0x04000000: /* ldr or str immediate */
818
offset.un = OFFSET_BITS(instr);
819
handler = do_alignment_ldrstr;
822
case 0x06000000: /* ldr or str register */
823
offset.un = regs->uregs[RM_BITS(instr)];
825
if (IS_SHIFT(instr)) {
826
unsigned int shiftval = SHIFT_BITS(instr);
828
switch(SHIFT_TYPE(instr)) {
830
offset.un <<= shiftval;
834
offset.un >>= shiftval;
838
offset.sn >>= shiftval;
844
if (regs->ARM_cpsr & PSR_C_BIT)
845
offset.un |= 1 << 31;
847
offset.un = offset.un >> shiftval |
848
offset.un << (32 - shiftval);
852
handler = do_alignment_ldrstr;
855
case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
857
handler = do_alignment_t32_to_handler(&instr, regs, &offset);
859
handler = do_alignment_ldmstm;
868
type = handler(addr, instr, regs);
870
if (type == TYPE_ERROR || type == TYPE_FAULT) {
871
regs->ARM_pc -= isize;
875
if (type == TYPE_LDST)
876
do_alignment_finish_ldst(addr, instr, regs, offset);
881
if (type == TYPE_ERROR)
884
* We got a fault - fix it up, or die.
886
do_bad_area(addr, fsr, regs);
890
printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
894
* Oops, we didn't handle the instruction.
896
printk(KERN_ERR "Alignment trap: not handling instruction "
897
"%0*lx at [<%08lx>]\n",
899
isize == 2 ? tinstr : instr, instrptr);
906
if (ai_usermode & UM_WARN)
907
printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
908
"Address=0x%08lx FSR 0x%03x\n", current->comm,
909
task_pid_nr(current), instrptr,
911
isize == 2 ? tinstr : instr,
914
if (ai_usermode & UM_FIXUP)
917
if (ai_usermode & UM_SIGNAL) {
920
si.si_signo = SIGBUS;
922
si.si_code = BUS_ADRALN;
923
si.si_addr = (void __user *)addr;
925
force_sig_info(si.si_signo, &si, current);
928
* We're about to disable the alignment trap and return to
929
* user space. But if an interrupt occurs before actually
930
* reaching user space, then the IRQ vector entry code will
931
* notice that we were still in kernel space and therefore
932
* the alignment trap won't be re-enabled in that case as it
933
* is presumed to be always on from kernel space.
934
* Let's prevent that race by disabling interrupts here (they
935
* are disabled on the way back to user space anyway in
936
* entry-common.S) and disable the alignment trap only if
937
* there is no work pending for this thread.
939
raw_local_irq_disable();
940
if (!(current_thread_info()->flags & _TIF_WORK_MASK))
941
set_cr(cr_no_alignment);
948
* This needs to be done after sysctl_init, otherwise sys/ will be
949
* overwritten. Actually, this shouldn't be in sys/ at all since
950
* it isn't a sysctl, and it doesn't contain sysctl information.
951
* We now locate it in /proc/cpu/alignment instead.
953
static int __init alignment_init(void)
955
#ifdef CONFIG_PROC_FS
956
struct proc_dir_entry *res;
958
res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
959
&alignment_proc_fops);
964
if (cpu_is_v6_unaligned()) {
965
cr_alignment &= ~CR_A;
966
cr_no_alignment &= ~CR_A;
967
set_cr(cr_alignment);
968
ai_usermode = safe_usermode(ai_usermode, false);
971
hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
972
"alignment exception");
975
* ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
976
* fault, not as alignment error.
978
* TODO: handle ARMv6K properly. Runtime check for 'K' extension is
981
if (cpu_architecture() <= CPU_ARCH_ARMv6) {
982
hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
983
"alignment exception");
989
fs_initcall(alignment_init);