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* Copyright (c) 2004 Topspin Communications. All rights reserved.
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* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include <linux/mlx4/cmd.h>
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* Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
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struct mlx4_mpt_entry {
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__be32 first_byte_offset;
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#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
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#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
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#define MLX4_MPT_FLAG_MIO (1 << 17)
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#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
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#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
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#define MLX4_MPT_FLAG_REGION (1 << 8)
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#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
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#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
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#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
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#define MLX4_MPT_STATUS_SW 0xF0
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#define MLX4_MPT_STATUS_HW 0x00
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static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
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spin_lock(&buddy->lock);
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for (o = order; o <= buddy->max_order; ++o)
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if (buddy->num_free[o]) {
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m = 1 << (buddy->max_order - o);
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seg = find_first_bit(buddy->bits[o], m);
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spin_unlock(&buddy->lock);
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clear_bit(seg, buddy->bits[o]);
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set_bit(seg ^ 1, buddy->bits[o]);
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++buddy->num_free[o];
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spin_unlock(&buddy->lock);
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static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
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spin_lock(&buddy->lock);
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while (test_bit(seg ^ 1, buddy->bits[order])) {
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clear_bit(seg ^ 1, buddy->bits[order]);
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--buddy->num_free[order];
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set_bit(seg, buddy->bits[order]);
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++buddy->num_free[order];
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spin_unlock(&buddy->lock);
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static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
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buddy->max_order = max_order;
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spin_lock_init(&buddy->lock);
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buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
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buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
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if (!buddy->bits || !buddy->num_free)
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for (i = 0; i <= buddy->max_order; ++i) {
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s = BITS_TO_LONGS(1 << (buddy->max_order - i));
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buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
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bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
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set_bit(0, buddy->bits[buddy->max_order]);
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buddy->num_free[buddy->max_order] = 1;
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for (i = 0; i <= buddy->max_order; ++i)
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kfree(buddy->bits[i]);
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kfree(buddy->num_free);
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static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
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for (i = 0; i <= buddy->max_order; ++i)
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kfree(buddy->bits[i]);
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kfree(buddy->num_free);
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static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
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struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
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seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
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if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
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seg + (1 << order) - 1)) {
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mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
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int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
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struct mlx4_mtt *mtt)
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mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
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mtt->page_shift = page_shift;
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for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1)
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mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
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if (mtt->first_seg == -1)
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EXPORT_SYMBOL_GPL(mlx4_mtt_init);
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void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
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struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
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mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
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mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
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mtt->first_seg + (1 << mtt->order) - 1);
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EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
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u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
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return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
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EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
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static u32 hw_index_to_key(u32 ind)
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return (ind >> 24) | (ind << 8);
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static u32 key_to_hw_index(u32 key)
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return (key << 24) | (key >> 8);
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static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
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MLX4_CMD_TIME_CLASS_B);
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static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
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!mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B);
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int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
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int npages, int page_shift, struct mlx4_mr *mr)
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struct mlx4_priv *priv = mlx4_priv(dev);
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index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
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mr->key = hw_index_to_key(index);
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err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
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mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
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EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
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void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
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struct mlx4_priv *priv = mlx4_priv(dev);
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err = mlx4_HW2SW_MPT(dev, NULL,
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key_to_hw_index(mr->key) &
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(dev->caps.num_mpts - 1));
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mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
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mlx4_mtt_cleanup(dev, &mr->mtt);
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mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
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EXPORT_SYMBOL_GPL(mlx4_mr_free);
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int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
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struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_mpt_entry *mpt_entry;
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err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox)) {
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err = PTR_ERR(mailbox);
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mpt_entry = mailbox->buf;
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memset(mpt_entry, 0, sizeof *mpt_entry);
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mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
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MLX4_MPT_FLAG_REGION |
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mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
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mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
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mpt_entry->start = cpu_to_be64(mr->iova);
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mpt_entry->length = cpu_to_be64(mr->size);
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mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
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if (mr->mtt.order < 0) {
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mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
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mpt_entry->mtt_seg = 0;
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mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
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if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
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/* fast register MR in free state */
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mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
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mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
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MLX4_MPT_PD_FLAG_RAE);
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mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) *
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dev->caps.mtts_per_seg);
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mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
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err = mlx4_SW2HW_MPT(dev, mailbox,
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key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
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mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
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mlx4_free_cmd_mailbox(dev, mailbox);
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mlx4_free_cmd_mailbox(dev, mailbox);
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mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
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EXPORT_SYMBOL_GPL(mlx4_mr_enable);
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static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
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int start_index, int npages, u64 *page_list)
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struct mlx4_priv *priv = mlx4_priv(dev);
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dma_addr_t dma_handle;
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int s = start_index * sizeof (u64);
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/* All MTTs must fit in the same page */
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if (start_index / (PAGE_SIZE / sizeof (u64)) !=
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(start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
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if (start_index & (dev->caps.mtts_per_seg - 1))
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mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
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s / dev->caps.mtt_entry_sz, &dma_handle);
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dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
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npages * sizeof (u64), DMA_TO_DEVICE);
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for (i = 0; i < npages; ++i)
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mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
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dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
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npages * sizeof (u64), DMA_TO_DEVICE);
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int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
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int start_index, int npages, u64 *page_list)
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chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
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err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
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start_index += chunk;
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EXPORT_SYMBOL_GPL(mlx4_write_mtt);
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int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
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struct mlx4_buf *buf)
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page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
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for (i = 0; i < buf->npages; ++i)
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page_list[i] = buf->direct.map + (i << buf->page_shift);
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page_list[i] = buf->page_list[i].map;
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err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
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EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
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int mlx4_init_mr_table(struct mlx4_dev *dev)
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struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
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err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
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~0, dev->caps.reserved_mrws, 0);
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err = mlx4_buddy_init(&mr_table->mtt_buddy,
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ilog2(dev->caps.num_mtt_segs));
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if (dev->caps.reserved_mtts) {
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if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
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mlx4_warn(dev, "MTT table of order %d is too small.\n",
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mr_table->mtt_buddy.max_order);
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goto err_reserve_mtts;
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mlx4_buddy_cleanup(&mr_table->mtt_buddy);
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mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
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void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
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struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
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mlx4_buddy_cleanup(&mr_table->mtt_buddy);
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mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
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static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
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int npages, u64 iova)
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if (npages > fmr->max_pages)
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page_mask = (1 << fmr->page_shift) - 1;
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/* We are getting page lists, so va must be page aligned. */
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if (iova & page_mask)
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/* Trust the user not to pass misaligned data in page_list */
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for (i = 0; i < npages; ++i) {
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if (page_list[i] & ~page_mask)
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if (fmr->maps >= fmr->max_maps)
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int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
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int npages, u64 iova, u32 *lkey, u32 *rkey)
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err = mlx4_check_fmr(fmr, page_list, npages, iova);
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key = key_to_hw_index(fmr->mr.key);
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key += dev->caps.num_mpts;
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*lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
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*(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
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/* Make sure MPT status is visible before writing MTT entries */
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dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
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npages * sizeof(u64), DMA_TO_DEVICE);
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for (i = 0; i < npages; ++i)
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fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
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dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
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npages * sizeof(u64), DMA_TO_DEVICE);
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fmr->mpt->key = cpu_to_be32(key);
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fmr->mpt->lkey = cpu_to_be32(key);
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fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
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fmr->mpt->start = cpu_to_be64(iova);
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/* Make MTT entries are visible before setting MPT status */
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*(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
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/* Make sure MPT status is visible before consumer can use FMR */
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EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
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int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
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int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
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struct mlx4_priv *priv = mlx4_priv(dev);
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if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
590
/* All MTTs must fit in the same page */
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if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
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fmr->page_shift = page_shift;
595
fmr->max_pages = max_pages;
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fmr->max_maps = max_maps;
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err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
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page_shift, &fmr->mr);
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mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
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fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
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fmr->mr.mtt.first_seg,
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mlx4_mr_free(dev, &fmr->mr);
620
EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
622
int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
624
struct mlx4_priv *priv = mlx4_priv(dev);
627
err = mlx4_mr_enable(dev, &fmr->mr);
631
fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
632
key_to_hw_index(fmr->mr.key), NULL);
638
EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
640
void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
641
u32 *lkey, u32 *rkey)
648
*(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
650
EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
652
int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
658
mlx4_mr_free(dev, &fmr->mr);
662
EXPORT_SYMBOL_GPL(mlx4_fmr_free);
664
int mlx4_SYNC_TPT(struct mlx4_dev *dev)
666
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000);
668
EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);