9
select PPC_INDIRECT_PIO
10
select PPC_INDIRECT_MMIO
13
select IRQ_EDGE_EOI_HANDLER
15
config PPC_CELL_NATIVE
17
select PPC_CELL_COMMON
19
select PPC_IO_WORKAROUNDS
22
select IBM_EMAC_ZMII #test only
23
select IBM_EMAC_TAH #test only
26
config PPC_IBM_CELL_BLADE
28
depends on PPC64 && PPC_BOOK3S
29
select PPC_CELL_NATIVE
30
select PPC_OF_PLATFORM_PCI
34
select UDBG_RTAS_CONSOLE
37
bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
38
depends on PPC64 && PPC_BOOK3S
39
select PPC_CELL_NATIVE
40
select PPC_OF_PLATFORM_PCI
42
select HAS_TXX9_SERIAL
44
select USB_OHCI_BIG_ENDIAN_MMIO
45
select USB_EHCI_BIG_ENDIAN_MMIO
48
bool "IBM Cell - QPACE"
49
depends on PPC64 && PPC_BOOK3S
50
select PPC_CELL_COMMON
54
depends on PPC_IBM_CELL_BLADE && PCI_MSI
57
menu "Cell Broadband Engine options"
61
tristate "SPU file system"
67
The SPU file system is used to access Synergistic Processing
68
Units on machines implementing the Broadband Processor
72
bool "Use 64K pages to map SPE local store"
73
# we depend on PPC_MM_SLICES for now rather than selecting
74
# it because we depend on hugetlbfs hooks being present. We
75
# will fix that when the generic code has been improved to
76
# not require hijacking hugetlbfs hooks.
77
depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
79
select PPC_HAS_HASH_64K
81
This option causes SPE local stores to be mapped in process
82
address spaces using 64K pages while the rest of the kernel
83
uses 4K pages. This can improve performances of applications
84
using multiple SPEs by lowering the TLB pressure on them.
91
bool "RAS features for bare metal Cell BE"
92
depends on PPC_CELL_NATIVE
95
config PPC_IBM_CELL_RESETBUTTON
96
bool "IBM Cell Blade Pinhole reset button"
97
depends on CBE_RAS && PPC_IBM_CELL_BLADE
100
Support Pinhole Resetbutton on IBM Cell blades.
101
This adds a method to trigger system reset via front panel pinhole button.
103
config PPC_IBM_CELL_POWERBUTTON
104
tristate "IBM Cell Blade power button"
105
depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
108
Support Powerbutton on IBM Cell blades.
109
This will enable the powerbutton as an input device.
112
tristate "CBE thermal support"
114
depends on CBE_RAS && SPU_BASE
117
tristate "CBE frequency scaling"
118
depends on CBE_RAS && CPU_FREQ
121
This adds the cpufreq driver for Cell BE processors.
122
For details, take a look at <file:Documentation/cpu-freq/>.
123
If you don't have such processor, say N
125
config CBE_CPUFREQ_PMI_ENABLE
126
bool "CBE frequency scaling using PMI interface"
127
depends on CBE_CPUFREQ && EXPERIMENTAL
130
Select this, if you want to use the PMI interface
131
to switch frequencies. Using PMI, the
132
processor will not only be able to run at lower speed,
133
but also at lower core voltage.
135
config CBE_CPUFREQ_PMI
137
depends on CBE_CPUFREQ_PMI_ENABLE
143
depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
145
PMI (Platform Management Interrupt) is a way to
146
communicate with the BMC (Baseboard Management Controller).
147
It is used in some IBM Cell blades.
149
config CBE_CPUFREQ_SPU_GOVERNOR
150
tristate "CBE frequency scaling based on SPU usage"
151
depends on SPU_FS && CPU_FREQ
154
This governor checks for spu usage to adjust the cpu frequency.
155
If no spu is running on a given cpu, that cpu will be throttled to
156
the minimal possible frequency.
162
depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE