2
* linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
4
* Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
6
* Created 15 Jan 2000 by Ghozlane Toumi
8
* Contributions (and many thanks) :
10
* 03/2001 James Simmons <jsimmons@infradead.org>
11
* 04/2001 Paul Mundt <lethal@chaoticdreams.org>
12
* 05/2001 Urs Ganse <ursg@uni.de>
13
* (initial work on voodoo2 port, interlace)
14
* 09/2002 Helge Deller <deller@gmx.de>
15
* (enable driver on big-endian machines (hppa), ioctl fixes)
16
* 12/2002 Helge Deller <deller@gmx.de>
17
* (port driver to new frambuffer infrastructure)
18
* 01/2003 Helge Deller <deller@gmx.de>
19
* (initial work on fb hardware acceleration for voodoo2)
20
* 08/2006 Alan Cox <alan@redhat.com>
21
* Remove never finished and bogus 24/32bit support
22
* Clean up macro abuse
23
* Minor tidying for format.
24
* 12/2006 Helge Deller <deller@gmx.de>
25
* add /sys/class/graphics/fbX/vgapass sysfs-interface
26
* add module option "mode_option" to set initial screen mode
27
* use fbdev default videomode database
28
* remove debug functions from ioctl
32
* The voodoo1 has the following memory mapped address space:
33
* 0x000000 - 0x3fffff : registers (4MB)
34
* 0x400000 - 0x7fffff : linear frame buffer (4MB)
35
* 0x800000 - 0xffffff : texture memory (8MB)
39
* misc notes, TODOs, toASKs, and deep thoughts
41
-TODO: at one time or another test that the mode is acceptable by the monitor
42
-ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
43
which one should i use ? is there any preferred one ? It seems ARGB is
45
-TODO: in set_var check the validity of timings (hsync vsync)...
46
-TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
47
a nop command. so it's ok as long as the commands we pass don't go
48
through the fifo. warning: issuing a nop command seems to need pci_fifo
49
-FIXME: in case of failure in the init sequence, be sure we return to a safe
51
- FIXME: Use accelerator for 2D scroll
52
-FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
57
* SST_DEBUG : enable debugging
58
* SST_DEBUG_REG : debug registers
60
* 1 : dac calls, [un]set_bits, FbiInit
61
* 2 : insane debug level (log every register read/write)
62
* SST_DEBUG_FUNC : functions
64
* 1 : function call / debug ioctl
66
* 3 : flood . you don't want to do that. trust me.
67
* SST_DEBUG_VAR : debug display/var structs
69
* 1 : dumps display, fb_var
71
* sstfb specific ioctls:
72
* toggle vga (0x46db) : toggle vga_pass_through
82
#include <linux/string.h>
83
#include <linux/kernel.h>
84
#include <linux/module.h>
86
#include <linux/pci.h>
87
#include <linux/delay.h>
88
#include <linux/init.h>
90
#include <linux/uaccess.h>
91
#include <video/sstfb.h>
94
/* initialized by setup */
96
static int vgapass; /* enable VGA passthrough cable */
97
static int mem; /* mem size in MB, 0 = autodetect */
98
static int clipping = 1; /* use clipping (slower, safer) */
99
static int gfxclk; /* force FBI freq in Mhz . Dangerous */
100
static int slowpci; /* slow PCI settings */
103
Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60
105
#define DEFAULT_VIDEO_MODE "640x480@60"
107
static char *mode_option __devinitdata = DEFAULT_VIDEO_MODE;
114
#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
116
static struct sst_spec voodoo_spec[] __devinitdata = {
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{ .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
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{ .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
126
#if (SST_DEBUG_REG > 0)
127
static void sst_dbg_print_read_reg(u32 reg, u32 val) {
130
case FBIINIT0: regname = "FbiInit0"; break;
131
case FBIINIT1: regname = "FbiInit1"; break;
132
case FBIINIT2: regname = "FbiInit2"; break;
133
case FBIINIT3: regname = "FbiInit3"; break;
134
case FBIINIT4: regname = "FbiInit4"; break;
135
case FBIINIT5: regname = "FbiInit5"; break;
136
case FBIINIT6: regname = "FbiInit6"; break;
137
default: regname = NULL; break;
140
r_ddprintk("sst_read(%#x): %#x\n", reg, val);
142
r_dprintk(" sst_read(%s): %#x\n", regname, val);
145
static void sst_dbg_print_write_reg(u32 reg, u32 val) {
148
case FBIINIT0: regname = "FbiInit0"; break;
149
case FBIINIT1: regname = "FbiInit1"; break;
150
case FBIINIT2: regname = "FbiInit2"; break;
151
case FBIINIT3: regname = "FbiInit3"; break;
152
case FBIINIT4: regname = "FbiInit4"; break;
153
case FBIINIT5: regname = "FbiInit5"; break;
154
case FBIINIT6: regname = "FbiInit6"; break;
155
default: regname = NULL; break;
158
r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
160
r_dprintk(" sst_write(%s, %#x)\n", regname, val);
162
#else /* (SST_DEBUG_REG > 0) */
163
# define sst_dbg_print_read_reg(reg, val) do {} while(0)
164
# define sst_dbg_print_write_reg(reg, val) do {} while(0)
165
#endif /* (SST_DEBUG_REG > 0) */
168
* hardware access functions
171
/* register access */
172
#define sst_read(reg) __sst_read(par->mmio_vbase, reg)
173
#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
174
#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
175
#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
176
#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
177
#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
178
#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
179
#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
181
static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
183
u32 ret = readl(vbase + reg);
184
sst_dbg_print_read_reg(reg, ret);
188
static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
190
sst_dbg_print_write_reg(reg, val);
191
writel(val, vbase + reg);
194
static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
196
r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
197
__sst_write(vbase, reg, __sst_read(vbase, reg) | val);
200
static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
202
r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
203
__sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
207
* wait for the fbi chip. ASK: what happens if the fbi is stuck ?
209
* the FBI is supposed to be ready if we receive 5 time
210
* in a row a "idle" answer to our requests
213
#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
215
static int __sst_wait_idle(u8 __iomem *vbase)
219
/* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
222
if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
223
f_dddprintk("status: busy\n");
224
/* FIXME basically, this is a busy wait. maybe not that good. oh well;
225
* this is a small loop after all.
226
* Or maybe we should use mdelay() or udelay() here instead ? */
230
f_dddprintk("status: idle(%d)\n", count);
232
if (count >= 5) return 1;
233
/* XXX do something to avoid hanging the machine if the voodoo is out */
239
/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
240
static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
245
__sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
246
__sst_wait_idle(vbase);
248
ret = __sst_read(vbase, DAC_READ) & 0xff;
249
r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
254
static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
256
r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
258
__sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
259
__sst_wait_idle(vbase);
262
/* indexed access to ti/att dacs */
263
static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
267
__sst_dac_write(vbase, DACREG_ADDR_I, reg);
268
ret = __sst_dac_read(vbase, DACREG_DATA_I);
269
r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
272
static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
274
r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
275
__sst_dac_write(vbase, DACREG_ADDR_I, reg);
276
__sst_dac_write(vbase, DACREG_DATA_I, val);
279
/* compute the m,n,p , returns the real freq
280
* (ics datasheet : N <-> N1 , P <-> N2)
282
* Fout= Fref * (M+2)/( 2^P * (N+2))
283
* we try to get close to the asked freq
284
* with P as high, and M as low as possible
286
* ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
287
* ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
288
* we'll use the lowest limitation, should be precise enouth
290
static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
292
int m, m2, n, p, best_err, fout;
298
/* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
299
while (((1 << p) * freq > VCO_MAX) && (p >= 0))
303
for (n = 1; n < 32; n++) {
304
/* calc 2 * m so we can round it later*/
305
m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
307
m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
310
fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
311
if ((abs(fout - freq) < best_err) && (m > 0)) {
314
best_err = abs(fout - freq);
315
/* we get the lowest m , allowing 0.5% error in freq*/
316
if (200*best_err < freq) break;
319
if (best_n == -1) /* unlikely, but who knows ? */
324
*freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
325
f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
326
t->m, t->n, t->p, *freq_out);
333
static void sstfb_clear_screen(struct fb_info *info)
336
fb_memset(info->screen_base, 0, info->fix.smem_len);
341
* sstfb_check_var - Optional function. Validates a var passed in.
342
* @var: frame buffer variable screen structure
343
* @info: frame buffer structure that represents a single frame buffer
345
* Limit to the abilities of a single chip as SLI is not supported
349
static int sstfb_check_var(struct fb_var_screeninfo *var,
350
struct fb_info *info)
352
struct sstfb_par *par = info->par;
353
int hSyncOff = var->xres + var->right_margin + var->left_margin;
354
int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
355
int vBackPorch = var->left_margin, yDim = var->yres;
356
int vSyncOn = var->vsync_len;
357
int tiles_in_X, real_length;
360
if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
361
printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n",
362
PICOS2KHZ(var->pixclock));
365
var->pixclock = KHZ2PICOS(freq);
367
if (var->vmode & FB_VMODE_INTERLACED)
368
vBackPorch += (vBackPorch % 2);
369
if (var->vmode & FB_VMODE_DOUBLE) {
376
switch (var->bits_per_pixel) {
378
var->bits_per_pixel = 16;
381
printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel);
386
if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 ||
387
hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 ||
388
vSyncOff <= 0 || vBackPorch <= 0) {
392
if (IS_VOODOO2(par)) {
393
/* Voodoo 2 limits */
394
tiles_in_X = (var->xres + 63 ) / 64 * 2;
396
if (var->xres > POW2(11) || yDim >= POW2(11)) {
397
printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
398
var->xres, var->yres);
402
if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) ||
403
var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) ||
404
vSyncOff >= POW2(13) || vBackPorch >= POW2(9) ||
405
tiles_in_X >= POW2(6) || tiles_in_X <= 0) {
406
printk(KERN_ERR "sstfb: Unsupported timings\n");
411
tiles_in_X = (var->xres + 63 ) / 64;
414
printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n",
418
if (var->xres > POW2(10) || var->yres >= POW2(10)) {
419
printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
420
var->xres, var->yres);
423
if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) ||
424
var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) ||
425
vSyncOff >= POW2(12) || vBackPorch >= POW2(8) ||
426
tiles_in_X >= POW2(4) || tiles_in_X <= 0) {
427
printk(KERN_ERR "sstfb: Unsupported timings\n");
432
/* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
433
/* FIXME: i don't like this... looks wrong */
434
real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
435
* ((var->bits_per_pixel == 16) ? 2 : 4);
437
if (real_length * yDim > info->fix.smem_len) {
438
printk(KERN_ERR "sstfb: Not enough video memory\n");
442
var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
443
var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
450
* correct the color bit fields
452
/* var->{red|green|blue}.msb_right = 0; */
454
switch (var->bits_per_pixel) {
455
case 16: /* RGB 565 LfbMode 0 */
457
var->green.length = 6;
458
var->blue.length = 5;
459
var->transp.length = 0;
461
var->red.offset = 11;
462
var->green.offset = 5;
463
var->blue.offset = 0;
464
var->transp.offset = 0;
473
* sstfb_set_par - Optional function. Alters the hardware state.
474
* @info: frame buffer structure that represents a single frame buffer
476
static int sstfb_set_par(struct fb_info *info)
478
struct sstfb_par *par = info->par;
479
u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
480
struct pci_dev *sst_dev = par->dev;
484
par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
486
par->yDim = info->var.yres;
487
par->vSyncOn = info->var.vsync_len;
488
par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
489
par->vBackPorch = info->var.upper_margin;
491
/* We need par->pll */
492
sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
494
if (info->var.vmode & FB_VMODE_INTERLACED)
495
par->vBackPorch += (par->vBackPorch % 2);
496
if (info->var.vmode & FB_VMODE_DOUBLE) {
497
par->vBackPorch <<= 1;
503
if (IS_VOODOO2(par)) {
504
/* voodoo2 has 32 pixel wide tiles , BUT strange things
505
happen with odd number of tiles */
506
par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
508
/* voodoo1 has 64 pixels wide tiles. */
509
par->tiles_in_X = (info->var.xres + 63 ) / 64;
512
f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
513
f_ddprintk("%-7d %-8d %-7d %-8d\n",
514
info->var.hsync_len, par->hSyncOff,
515
par->vSyncOn, par->vSyncOff);
516
f_ddprintk("left_margin upper_margin xres yres Freq\n");
517
f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
518
info->var.left_margin, info->var.upper_margin,
519
info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
521
sst_write(NOPCMD, 0);
523
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
524
sst_set_bits(FBIINIT1, VIDEO_RESET);
525
sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
526
sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
529
/*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
531
sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
532
sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
533
sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
534
sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
536
fbiinit2 = sst_read(FBIINIT2);
537
fbiinit3 = sst_read(FBIINIT3);
539
/* everything is reset. we enable fbiinit2/3 remap : dac access ok */
540
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
541
PCI_EN_INIT_WR | PCI_REMAP_DAC );
543
par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
545
/* set video clock */
546
par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
548
/* disable fbiinit2/3 remap */
549
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
552
/* restore fbiinit2/3 */
553
sst_write(FBIINIT2,fbiinit2);
554
sst_write(FBIINIT3,fbiinit3);
556
fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
561
/* | (15 << TILES_IN_X_SHIFT) */
563
/* | (2 << VCLK_2X_SEL_DEL_SHIFT)
564
| (2 << VCLK_DEL_SHIFT) */;
565
/* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
566
in (near) future set them accordingly to revision + resolution (cf glide)
567
first understand what it stands for :)
568
FIXME: there are some artefacts... check for the vclk_in_delay
569
lets try with 6ns delay in both vclk_out & in...
570
doh... they're still there :\
573
ntiles = par->tiles_in_X;
574
if (IS_VOODOO2(par)) {
575
fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
576
| ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
577
/* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
578
and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
579
write our value. BTW due to the dac unable to read odd number of tiles, this
580
field is always null ... */
581
fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
584
fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
586
switch (info->var.bits_per_pixel) {
588
fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
593
sst_write(FBIINIT1, fbiinit1);
594
if (IS_VOODOO2(par)) {
595
sst_write(FBIINIT6, fbiinit6);
596
fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
597
if (info->var.vmode & FB_VMODE_INTERLACED)
598
fbiinit5 |= INTERLACE;
599
if (info->var.vmode & FB_VMODE_DOUBLE)
600
fbiinit5 |= VDOUBLESCAN;
601
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
602
fbiinit5 |= HSYNC_HIGH;
603
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
604
fbiinit5 |= VSYNC_HIGH;
605
sst_write(FBIINIT5, fbiinit5);
608
sst_unset_bits(FBIINIT1, VIDEO_RESET);
609
sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
610
sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
611
/* disables fbiinit writes */
612
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
614
/* set lfbmode : set mode + front buffer for reads/writes
615
+ disable pipeline */
616
switch (info->var.bits_per_pixel) {
624
#if defined(__BIG_ENDIAN)
625
/* Enable byte-swizzle functionality in hardware.
626
* With this enabled, all our read- and write-accesses to
627
* the voodoo framebuffer can be done in native format, and
628
* the hardware will automatically convert it to little-endian.
629
* - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
630
lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
631
LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
635
sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
637
* Set "clipping" dimensions. If clipping is disabled and
638
* writes to offscreen areas of the framebuffer are performed,
639
* the "behaviour is undefined" (_very_ undefined) - Urs
641
/* btw, it requires enabling pixel pipeline in LFBMODE .
642
off screen read/writes will just wrap and read/print pixels
643
on screen. Ugly but not that dangerous */
644
f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
645
info->var.xres - 1, par->yDim - 1);
647
sst_write(CLIP_LEFT_RIGHT, info->var.xres);
648
sst_write(CLIP_LOWY_HIGHY, par->yDim);
649
sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
651
/* no clipping : direct access, no pipeline */
652
sst_write(LFBMODE, lfbmode);
658
* sstfb_setcolreg - Optional function. Sets a color register.
659
* @regno: hardware colormap register
660
* @red: frame buffer colormap structure
661
* @green: The green value which can be up to 16 bits wide
662
* @blue: The blue value which can be up to 16 bits wide.
663
* @transp: If supported the alpha value which can be up to 16 bits wide.
664
* @info: frame buffer info structure
666
static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
667
u_int transp, struct fb_info *info)
669
struct sstfb_par *par = info->par;
672
f_dddprintk("sstfb_setcolreg\n");
673
f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
674
regno, red, green, blue, transp);
678
red >>= (16 - info->var.red.length);
679
green >>= (16 - info->var.green.length);
680
blue >>= (16 - info->var.blue.length);
681
transp >>= (16 - info->var.transp.length);
682
col = (red << info->var.red.offset)
683
| (green << info->var.green.offset)
684
| (blue << info->var.blue.offset)
685
| (transp << info->var.transp.offset);
687
par->palette[regno] = col;
692
static void sstfb_setvgapass( struct fb_info *info, int enable )
694
struct sstfb_par *par = info->par;
695
struct pci_dev *sst_dev = par->dev;
698
enable = enable ? 1:0;
699
if (par->vgapass == enable)
701
par->vgapass = enable;
703
pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
704
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
705
tmp | PCI_EN_INIT_WR );
706
fbiinit0 = sst_read (FBIINIT0);
708
sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH);
709
printk(KERN_INFO "fb%d: Enabling VGA pass-through\n", info->node );
711
sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH);
712
printk(KERN_INFO "fb%d: Disabling VGA pass-through\n", info->node );
714
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
717
static ssize_t store_vgapass(struct device *device, struct device_attribute *attr,
718
const char *buf, size_t count)
720
struct fb_info *info = dev_get_drvdata(device);
724
val = simple_strtoul(buf, last, 0);
725
sstfb_setvgapass(info, val);
730
static ssize_t show_vgapass(struct device *device, struct device_attribute *attr,
733
struct fb_info *info = dev_get_drvdata(device);
734
struct sstfb_par *par = info->par;
735
return snprintf(buf, PAGE_SIZE, "%d\n", par->vgapass);
738
static struct device_attribute device_attrs[] = {
739
__ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass)
742
static int sstfb_ioctl(struct fb_info *info, unsigned int cmd,
745
struct sstfb_par *par;
749
/* set/get VGA pass_through mode */
750
case SSTFB_SET_VGAPASS:
751
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
753
sstfb_setvgapass(info, val);
755
case SSTFB_GET_VGAPASS:
758
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
768
* Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
771
static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
773
struct sstfb_par *par = info->par;
774
u32 stride = info->fix.line_length;
776
if (!IS_VOODOO2(par))
779
sst_write(BLTSRCBASEADDR, 0);
780
sst_write(BLTDSTBASEADDR, 0);
781
sst_write(BLTROP, BLTROP_COPY);
782
sst_write(BLTXYSTRIDES, stride | (stride << 16));
783
sst_write(BLTSRCXY, area->sx | (area->sy << 16));
784
sst_write(BLTDSTXY, area->dx | (area->dy << 16));
785
sst_write(BLTSIZE, area->width | (area->height << 16));
786
sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
787
(BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
794
* FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
797
static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
799
struct sstfb_par *par = info->par;
800
u32 stride = info->fix.line_length;
802
if (!IS_VOODOO2(par))
805
sst_write(BLTCLIPX, info->var.xres);
806
sst_write(BLTCLIPY, info->var.yres);
808
sst_write(BLTDSTBASEADDR, 0);
809
sst_write(BLTCOLOR, rect->color);
810
sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
811
sst_write(BLTXYSTRIDES, stride | (stride << 16));
812
sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
813
sst_write(BLTSIZE, rect->width | (rect->height << 16));
814
sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
815
| (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
825
static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
827
u8 __iomem *fbbase_virt = info->screen_base;
830
if (mem >= 1 && mem <= 4) {
831
*memsize = (mem * 0x100000);
832
printk(KERN_INFO "supplied memsize: %#x\n", *memsize);
836
writel(0xdeadbeef, fbbase_virt);
837
writel(0xdeadbeef, fbbase_virt+0x100000);
838
writel(0xdeadbeef, fbbase_virt+0x200000);
839
f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
840
readl(fbbase_virt), readl(fbbase_virt + 0x100000),
841
readl(fbbase_virt + 0x200000));
843
writel(0xabcdef01, fbbase_virt);
845
f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
846
readl(fbbase_virt), readl(fbbase_virt + 0x100000),
847
readl(fbbase_virt + 0x200000));
849
/* checks for 4mb lfb, then 2, then defaults to 1 */
850
if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
852
else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
856
f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
862
* DAC detection routines
865
/* fbi should be idle, and fifo emty and mem disabled */
866
/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
868
static int __devinit sst_detect_att(struct fb_info *info)
870
struct sstfb_par *par = info->par;
873
for (i = 0; i < 3; i++) {
874
sst_dac_write(DACREG_WMA, 0); /* backdoor */
875
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
876
sst_dac_read(DACREG_RMR);
877
sst_dac_read(DACREG_RMR);
878
sst_dac_read(DACREG_RMR);
879
/* the fifth time, CR0 is read */
880
sst_dac_read(DACREG_RMR);
881
/* the 6th, manufacturer id register */
882
mir = sst_dac_read(DACREG_RMR);
883
/*the 7th, device ID register */
884
dir = sst_dac_read(DACREG_RMR);
885
f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
886
if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) {
893
static int __devinit sst_detect_ti(struct fb_info *info)
895
struct sstfb_par *par = info->par;
898
for (i = 0; i<3; i++) {
899
sst_dac_write(DACREG_WMA, 0); /* backdoor */
900
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
901
sst_dac_read(DACREG_RMR);
902
sst_dac_read(DACREG_RMR);
903
sst_dac_read(DACREG_RMR);
904
/* the fifth time, CR0 is read */
905
sst_dac_read(DACREG_RMR);
906
/* the 6th, manufacturer id register */
907
mir = sst_dac_read(DACREG_RMR);
908
/*the 7th, device ID register */
909
dir = sst_dac_read(DACREG_RMR);
910
f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
911
if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
919
* try to detect ICS5342 ramdac
920
* we get the 1st byte (M value) of preset f1,f7 and fB
921
* why those 3 ? mmmh... for now, i'll do it the glide way...
922
* and ask questions later. anyway, it seems that all the freq registers are
923
* really at their default state (cf specs) so i ask again, why those 3 regs ?
924
* mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
925
* pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
927
* is it really safe ? how can i reset this ramdac ? geee...
929
static int __devinit sst_detect_ics(struct fb_info *info)
931
struct sstfb_par *par = info->par;
932
int m_clk0_1, m_clk0_7, m_clk1_b;
933
int n_clk0_1, n_clk0_7, n_clk1_b;
936
for (i = 0; i<5; i++ ) {
937
sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
938
m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
939
n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
940
sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
941
m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
942
n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
943
sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
944
m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
945
n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
946
f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
947
m_clk0_1, m_clk0_7, m_clk1_b);
948
f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
949
n_clk0_1, n_clk0_7, n_clk1_b);
950
if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
951
&& (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
952
&& (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
961
* gfx, video, pci fifo should be reset, dram refresh disabled
965
static int sst_set_pll_att_ti(struct fb_info *info,
966
const struct pll_timing *t, const int clock)
968
struct sstfb_par *par = info->par;
971
/* enable indexed mode */
972
sst_dac_write(DACREG_WMA, 0); /* backdoor */
973
sst_dac_read(DACREG_RMR); /* 1 time: RMR */
974
sst_dac_read(DACREG_RMR); /* 2 RMR */
975
sst_dac_read(DACREG_RMR); /* 3 // */
976
sst_dac_read(DACREG_RMR); /* 4 // */
977
cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
979
sst_dac_write(DACREG_WMA, 0);
980
sst_dac_read(DACREG_RMR);
981
sst_dac_read(DACREG_RMR);
982
sst_dac_read(DACREG_RMR);
983
sst_dac_read(DACREG_RMR);
984
sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
985
| DACREG_CR0_EN_INDEXED
987
| DACREG_CR0_PWDOWN );
988
/* so, now we are in indexed mode . dunno if its common, but
989
i find this way of doing things a little bit weird :p */
992
cc = dac_i_read(DACREG_CC_I);
995
dac_i_write(DACREG_AC0_I, t->m);
996
dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
997
dac_i_write(DACREG_CC_I,
998
(cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
1001
dac_i_write(DACREG_BD0_I, t->m);
1002
dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
1003
dac_i_write(DACREG_CC_I,
1004
(cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
1007
dprintk("%s: wrong clock code '%d'\n",
1013
/* power up the dac & return to "normal" non-indexed mode */
1014
dac_i_write(DACREG_CR0_I,
1015
cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1019
static int sst_set_pll_ics(struct fb_info *info,
1020
const struct pll_timing *t, const int clock)
1022
struct sstfb_par *par = info->par;
1025
sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
1026
pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
1029
sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
1030
sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1031
sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1032
/* selects freq f0 for clock 0 */
1033
sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1034
sst_dac_write(DACREG_ICS_PLLDATA,
1037
| DACREG_ICS_CLK0_0);
1040
sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
1041
sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1042
sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1043
/* selects freq fA for clock 1 */
1044
sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1045
sst_dac_write(DACREG_ICS_PLLDATA,
1046
(pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
1049
dprintk("%s: wrong clock code '%d'\n",
1057
static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
1059
struct sstfb_par *par = info->par;
1062
sst_dac_write(DACREG_WMA, 0); /* backdoor */
1063
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1064
sst_dac_read(DACREG_RMR);
1065
sst_dac_read(DACREG_RMR);
1066
sst_dac_read(DACREG_RMR);
1067
/* the fifth time, CR0 is read */
1068
cr0 = sst_dac_read(DACREG_RMR);
1070
sst_dac_write(DACREG_WMA, 0); /* backdoor */
1071
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1072
sst_dac_read(DACREG_RMR);
1073
sst_dac_read(DACREG_RMR);
1074
sst_dac_read(DACREG_RMR);
1078
sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
1081
dprintk("%s: bad depth '%u'\n", __func__, bpp);
1086
static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
1088
struct sstfb_par *par = info->par;
1092
sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
1095
dprintk("%s: bad depth '%u'\n", __func__, bpp);
1102
* prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
1103
* dram refresh disabled, FbiInit remaped.
1104
* TODO: mmh.. maybe i should put the "prerequisite" in the func ...
1108
static struct dac_switch dacs[] __devinitdata = {
1109
{ .name = "TI TVP3409",
1110
.detect = sst_detect_ti,
1111
.set_pll = sst_set_pll_att_ti,
1112
.set_vidmod = sst_set_vidmod_att_ti },
1114
{ .name = "AT&T ATT20C409",
1115
.detect = sst_detect_att,
1116
.set_pll = sst_set_pll_att_ti,
1117
.set_vidmod = sst_set_vidmod_att_ti },
1118
{ .name = "ICS ICS5342",
1119
.detect = sst_detect_ics,
1120
.set_pll = sst_set_pll_ics,
1121
.set_vidmod = sst_set_vidmod_ics },
1124
static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1128
for (i = 0; i < ARRAY_SIZE(dacs); i++) {
1129
ret = dacs[i].detect(info);
1135
f_dprintk("%s found %s\n", __func__, dacs[i].name);
1136
par->dac_sw = dacs[i];
1143
static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par)
1145
u32 fbiinit0, fbiinit1, fbiinit4;
1146
struct pci_dev *dev = par->dev;
1147
struct pll_timing gfx_timings;
1148
struct sst_spec *spec;
1152
spec = &voodoo_spec[par->type];
1153
f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
1155
f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
1156
sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
1157
sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
1158
/* disable video clock */
1159
pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
1161
/* enable writing to init registers, disable pci fifo */
1162
pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1164
sst_set_bits(FBIINIT1, VIDEO_RESET);
1166
/* reset gfx + pci fifo */
1167
sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1171
/*sst_unset_bits(FBIINIT0, FIFO_RESET);
1174
/*sst_unset_bits(FBIINIT0, FBI_RESET);
1177
/* disable dram refresh */
1178
sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1180
/* remap fbinit2/3 to dac */
1181
pci_write_config_dword(dev, PCI_INIT_ENABLE,
1182
PCI_EN_INIT_WR | PCI_REMAP_DAC );
1183
/* detect dac type */
1184
if (!sst_detect_dactype(info, par)) {
1185
printk(KERN_ERR "sstfb: unknown dac type.\n");
1186
//FIXME watch it: we are not in a safe state, bad bad bad.
1190
/* set graphic clock */
1191
gfx_clock = spec->default_gfx_clock;
1192
if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
1193
printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk);
1194
gfx_clock = gfxclk *1000;
1195
} else if (gfxclk) {
1196
printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk);
1199
sst_calc_pll(gfx_clock, &Fout, &gfx_timings);
1200
par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1202
/* disable fbiinit remap */
1203
pci_write_config_dword(dev, PCI_INIT_ENABLE,
1204
PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
1205
/* defaults init registers */
1206
/* FbiInit0: unreset gfx, unreset fifo */
1207
fbiinit0 = FBIINIT0_DEFAULT;
1208
fbiinit1 = FBIINIT1_DEFAULT;
1209
fbiinit4 = FBIINIT4_DEFAULT;
1210
par->vgapass = vgapass;
1212
fbiinit0 &= ~DIS_VGA_PASSTHROUGH;
1214
fbiinit0 |= DIS_VGA_PASSTHROUGH;
1216
fbiinit1 |= SLOW_PCI_WRITES;
1217
fbiinit4 |= SLOW_PCI_READS;
1219
fbiinit1 &= ~SLOW_PCI_WRITES;
1220
fbiinit4 &= ~SLOW_PCI_READS;
1222
sst_write(FBIINIT0, fbiinit0);
1224
sst_write(FBIINIT1, fbiinit1);
1226
sst_write(FBIINIT2, FBIINIT2_DEFAULT);
1228
sst_write(FBIINIT3, FBIINIT3_DEFAULT);
1230
sst_write(FBIINIT4, fbiinit4);
1232
if (IS_VOODOO2(par)) {
1233
sst_write(FBIINIT6, FBIINIT6_DEFAULT);
1237
pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
1238
pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
1242
static void __devexit sst_shutdown(struct fb_info *info)
1244
struct sstfb_par *par = info->par;
1245
struct pci_dev *dev = par->dev;
1246
struct pll_timing gfx_timings;
1249
/* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
1250
pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1251
sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
1252
sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1253
sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1255
pci_write_config_dword(dev, PCI_INIT_ENABLE,
1256
PCI_EN_INIT_WR | PCI_REMAP_DAC);
1257
/* set 20Mhz gfx clock */
1258
sst_calc_pll(20000, &Fout, &gfx_timings);
1259
par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1260
/* TODO maybe shutdown the dac, vrefresh and so on... */
1261
pci_write_config_dword(dev, PCI_INIT_ENABLE,
1263
sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH);
1264
pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
1265
/* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
1267
pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
1272
* Interface to the world
1274
static int __devinit sstfb_setup(char *options)
1278
if (!options || !*options)
1281
while ((this_opt = strsep(&options, ",")) != NULL) {
1282
if (!*this_opt) continue;
1284
f_ddprintk("option %s\n", this_opt);
1286
if (!strcmp(this_opt, "vganopass"))
1288
else if (!strcmp(this_opt, "vgapass"))
1290
else if (!strcmp(this_opt, "clipping"))
1292
else if (!strcmp(this_opt, "noclipping"))
1294
else if (!strcmp(this_opt, "fastpci"))
1296
else if (!strcmp(this_opt, "slowpci"))
1298
else if (!strncmp(this_opt, "mem:",4))
1299
mem = simple_strtoul (this_opt+4, NULL, 0);
1300
else if (!strncmp(this_opt, "gfxclk:",7))
1301
gfxclk = simple_strtoul (this_opt+7, NULL, 0);
1303
mode_option = this_opt;
1309
static struct fb_ops sstfb_ops = {
1310
.owner = THIS_MODULE,
1311
.fb_check_var = sstfb_check_var,
1312
.fb_set_par = sstfb_set_par,
1313
.fb_setcolreg = sstfb_setcolreg,
1314
.fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
1315
.fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
1316
.fb_imageblit = cfb_imageblit,
1317
.fb_ioctl = sstfb_ioctl,
1320
static int __devinit sstfb_probe(struct pci_dev *pdev,
1321
const struct pci_device_id *id)
1323
struct fb_info *info;
1324
struct fb_fix_screeninfo *fix;
1325
struct sstfb_par *par;
1326
struct sst_spec *spec;
1329
/* Enable device in PCI config. */
1330
if ((err=pci_enable_device(pdev))) {
1331
printk(KERN_ERR "cannot enable device\n");
1335
/* Allocate the fb and par structures. */
1336
info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
1340
pci_set_drvdata(pdev, info);
1345
par->type = id->driver_data;
1346
spec = &voodoo_spec[par->type];
1347
f_ddprintk("found device : %s\n", spec->name);
1350
par->revision = pdev->revision;
1352
fix->mmio_start = pci_resource_start(pdev,0);
1353
fix->mmio_len = 0x400000;
1354
fix->smem_start = fix->mmio_start + 0x400000;
1356
if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
1357
printk(KERN_ERR "sstfb: cannot reserve mmio memory\n");
1361
if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
1362
printk(KERN_ERR "sstfb: cannot reserve fb memory\n");
1366
par->mmio_vbase = ioremap_nocache(fix->mmio_start,
1368
if (!par->mmio_vbase) {
1369
printk(KERN_ERR "sstfb: cannot remap register area %#lx\n",
1371
goto fail_mmio_remap;
1373
info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
1374
if (!info->screen_base) {
1375
printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n",
1380
if (!sst_init(info, par)) {
1381
printk(KERN_ERR "sstfb: Init failed\n");
1384
sst_get_memsize(info, &fix->smem_len);
1385
strlcpy(fix->id, spec->name, sizeof(fix->id));
1387
printk(KERN_INFO "%s (revision %d) with %s dac\n",
1388
fix->id, par->revision, par->dac_sw.name);
1389
printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
1390
fix->smem_start, info->screen_base,
1391
fix->smem_len >> 20);
1393
f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
1394
f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
1395
f_ddprintk("fbbase_virt: %p\n", info->screen_base);
1397
info->flags = FBINFO_DEFAULT;
1398
info->fbops = &sstfb_ops;
1399
info->pseudo_palette = par->palette;
1401
fix->type = FB_TYPE_PACKED_PIXELS;
1402
fix->visual = FB_VISUAL_TRUECOLOR;
1403
fix->accel = FB_ACCEL_NONE; /* FIXME */
1405
* According to the specs, the linelength must be of 1024 *pixels*
1406
* and the 24bpp mode is in fact a 32 bpp mode (and both are in
1407
* fact dithered to 16bit).
1409
fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
1411
fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16);
1413
if (sstfb_check_var(&info->var, info)) {
1414
printk(KERN_ERR "sstfb: invalid video mode.\n");
1418
if (sstfb_set_par(info)) {
1419
printk(KERN_ERR "sstfb: can't set default video mode.\n");
1423
if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1424
printk(KERN_ERR "sstfb: can't alloc cmap memory.\n");
1429
info->device = &pdev->dev;
1430
if (register_framebuffer(info) < 0) {
1431
printk(KERN_ERR "sstfb: can't register framebuffer.\n");
1435
sstfb_clear_screen(info);
1437
if (device_create_file(info->dev, &device_attrs[0]))
1438
printk(KERN_WARNING "sstfb: can't create sysfs entry.\n");
1441
printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n",
1442
info->node, fix->id, info->screen_base);
1447
fb_dealloc_cmap(&info->cmap);
1449
iounmap(info->screen_base);
1451
iounmap(par->mmio_vbase);
1453
release_mem_region(fix->smem_start, 0x400000);
1455
release_mem_region(fix->mmio_start, info->fix.mmio_len);
1457
framebuffer_release(info);
1458
return -ENXIO; /* no voodoo detected */
1461
static void __devexit sstfb_remove(struct pci_dev *pdev)
1463
struct sstfb_par *par;
1464
struct fb_info *info;
1466
info = pci_get_drvdata(pdev);
1469
device_remove_file(info->dev, &device_attrs[0]);
1471
iounmap(info->screen_base);
1472
iounmap(par->mmio_vbase);
1473
release_mem_region(info->fix.smem_start, 0x400000);
1474
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1475
fb_dealloc_cmap(&info->cmap);
1476
unregister_framebuffer(info);
1477
framebuffer_release(info);
1481
static const struct pci_device_id sstfb_id_tbl[] = {
1482
{ PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ),
1483
.driver_data = ID_VOODOO1, },
1484
{ PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2),
1485
.driver_data = ID_VOODOO2, },
1489
static struct pci_driver sstfb_driver = {
1491
.id_table = sstfb_id_tbl,
1492
.probe = sstfb_probe,
1493
.remove = __devexit_p(sstfb_remove),
1497
static int __devinit sstfb_init(void)
1499
char *option = NULL;
1501
if (fb_get_options("sstfb", &option))
1503
sstfb_setup(option);
1505
return pci_register_driver(&sstfb_driver);
1508
static void __devexit sstfb_exit(void)
1510
pci_unregister_driver(&sstfb_driver);
1514
module_init(sstfb_init);
1515
module_exit(sstfb_exit);
1517
MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
1518
MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
1519
MODULE_LICENSE("GPL");
1521
module_param(mem, int, 0);
1522
MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
1523
module_param(vgapass, bool, 0);
1524
MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
1525
module_param(clipping, bool, 0);
1526
MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
1527
module_param(gfxclk, int, 0);
1528
MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
1529
module_param(slowpci, bool, 0);
1530
MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
1531
module_param(mode_option, charp, 0);
1532
MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")");