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* Atmel MultiMedia Card Interface driver
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* Copyright (C) 2004-2008 Atmel Corporation
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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#include <linux/blkdev.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/stat.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sdio.h>
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#include <mach/atmel-mci.h>
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#include <linux/atmel-mci.h>
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#include <linux/atmel_pdc.h>
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#include <asm/unaligned.h>
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#include <mach/board.h>
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#include "atmel-mci-regs.h"
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#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
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#define ATMCI_DMA_THRESHOLD 16
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EVENT_CMD_COMPLETE = 0,
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enum atmel_mci_state {
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struct atmel_mci_caps {
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struct atmel_mci_dma {
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struct dma_chan *chan;
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struct dma_async_tx_descriptor *data_desc;
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* struct atmel_mci - MMC controller state shared between all slots
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* @lock: Spinlock protecting the queue and associated data.
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* @regs: Pointer to MMIO registers.
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* @sg: Scatterlist entry currently being processed by PIO or PDC code.
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* @pio_offset: Offset into the current scatterlist entry.
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* @cur_slot: The slot which is currently using the controller.
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* @mrq: The request currently being processed on @cur_slot,
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* or NULL if the controller is idle.
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* @cmd: The command currently being sent to the card, or NULL.
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* @data: The data currently being transferred, or NULL if no data
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* transfer is in progress.
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* @data_size: just data->blocks * data->blksz.
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* @dma: DMA client state.
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* @data_chan: DMA channel being used for the current data transfer.
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* @cmd_status: Snapshot of SR taken upon completion of the current
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* command. Only valid when EVENT_CMD_COMPLETE is pending.
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* @data_status: Snapshot of SR taken upon completion of the current
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* data transfer. Only valid when EVENT_DATA_COMPLETE or
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* EVENT_DATA_ERROR is pending.
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* @stop_cmdr: Value to be loaded into CMDR when the stop command is
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* @tasklet: Tasklet running the request state machine.
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* @pending_events: Bitmask of events flagged by the interrupt handler
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* to be processed by the tasklet.
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* @completed_events: Bitmask of events which the state machine has
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* @state: Tasklet state.
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* @queue: List of slots waiting for access to the controller.
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* @need_clock_update: Update the clock rate before the next request.
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* @need_reset: Reset controller before next request.
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* @mode_reg: Value of the MR register.
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* @cfg_reg: Value of the CFG register.
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* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
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* rate and timeout calculations.
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* @mapbase: Physical address of the MMIO registers.
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* @mck: The peripheral bus clock hooked up to the MMC controller.
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* @pdev: Platform device associated with the MMC controller.
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* @slot: Slots sharing this MMC controller.
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* @caps: MCI capabilities depending on MCI version.
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* @prepare_data: function to setup MCI before data transfer which
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* depends on MCI capabilities.
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* @submit_data: function to start data transfer which depends on MCI
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* @stop_transfer: function to stop data transfer which depends on MCI
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* @lock is a softirq-safe spinlock protecting @queue as well as
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* @cur_slot, @mrq and @state. These must always be updated
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* at the same time while holding @lock.
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* @lock also protects mode_reg and need_clock_update since these are
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* used to synchronize mode register updates with the queue
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* The @mrq field of struct atmel_mci_slot is also protected by @lock,
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* and must always be written at the same time as the slot is added to
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* @pending_events and @completed_events are accessed using atomic bit
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* operations, so they don't need any locking.
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* None of the fields touched by the interrupt handler need any
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* locking. However, ordering is important: Before EVENT_DATA_ERROR or
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* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
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* interrupts must be disabled and @data_status updated with a
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* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
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* CMDRDY interrupt must be disabled and @cmd_status updated with a
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* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
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* bytes_xfered field of @data must be written. This is ensured by
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struct scatterlist *sg;
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unsigned int pio_offset;
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struct atmel_mci_slot *cur_slot;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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unsigned int data_size;
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struct atmel_mci_dma dma;
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struct dma_chan *data_chan;
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struct tasklet_struct tasklet;
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unsigned long pending_events;
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unsigned long completed_events;
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enum atmel_mci_state state;
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struct list_head queue;
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bool need_clock_update;
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unsigned long bus_hz;
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unsigned long mapbase;
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struct platform_device *pdev;
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struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
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struct atmel_mci_caps caps;
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u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
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void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
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void (*stop_transfer)(struct atmel_mci *host);
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* struct atmel_mci_slot - MMC slot state
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* @mmc: The mmc_host representing this slot.
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* @host: The MMC controller this slot is using.
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* @sdc_reg: Value of SDCR to be written before using this slot.
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* @sdio_irq: SDIO irq mask for this slot.
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* @mrq: mmc_request currently being processed or waiting to be
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* processed, or NULL when the slot is idle.
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* @queue_node: List node for placing this node in the @queue list of
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* @clock: Clock rate configured by set_ios(). Protected by host->lock.
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* @flags: Random state bits associated with the slot.
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* @detect_pin: GPIO pin used for card detection, or negative if not
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* @wp_pin: GPIO pin used for card write protect sending, or negative
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* @detect_is_active_high: The state of the detect pin when it is active.
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* @detect_timer: Timer used for debouncing @detect_pin interrupts.
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struct atmel_mci_slot {
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struct mmc_host *mmc;
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struct atmel_mci *host;
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struct mmc_request *mrq;
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struct list_head queue_node;
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#define ATMCI_CARD_PRESENT 0
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#define ATMCI_CARD_NEED_INIT 1
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#define ATMCI_SHUTDOWN 2
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#define ATMCI_SUSPENDED 3
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bool detect_is_active_high;
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struct timer_list detect_timer;
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#define atmci_test_and_clear_pending(host, event) \
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test_and_clear_bit(event, &host->pending_events)
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#define atmci_set_completed(host, event) \
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set_bit(event, &host->completed_events)
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#define atmci_set_pending(host, event) \
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set_bit(event, &host->pending_events)
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* The debugfs stuff below is mostly optimized away when
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* CONFIG_DEBUG_FS is not set.
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static int atmci_req_show(struct seq_file *s, void *v)
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struct atmel_mci_slot *slot = s->private;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_command *stop;
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struct mmc_data *data;
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/* Make sure we get a consistent snapshot */
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spin_lock_bh(&slot->host->lock);
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"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
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cmd->opcode, cmd->arg, cmd->flags,
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cmd->resp[0], cmd->resp[1], cmd->resp[2],
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cmd->resp[3], cmd->error);
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seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
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data->bytes_xfered, data->blocks,
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data->blksz, data->flags, data->error);
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"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
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stop->opcode, stop->arg, stop->flags,
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stop->resp[0], stop->resp[1], stop->resp[2],
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stop->resp[3], stop->error);
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spin_unlock_bh(&slot->host->lock);
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static int atmci_req_open(struct inode *inode, struct file *file)
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return single_open(file, atmci_req_show, inode->i_private);
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static const struct file_operations atmci_req_fops = {
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.owner = THIS_MODULE,
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.open = atmci_req_open,
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.release = single_release,
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static void atmci_show_status_reg(struct seq_file *s,
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const char *regname, u32 value)
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static const char *sr_bit[] = {
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seq_printf(s, "%s:\t0x%08x", regname, value);
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for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
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if (value & (1 << i)) {
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seq_printf(s, " %s", sr_bit[i]);
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seq_puts(s, " UNKNOWN");
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static int atmci_regs_show(struct seq_file *s, void *v)
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struct atmel_mci *host = s->private;
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buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
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* Grab a more or less consistent snapshot. Note that we're
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* not disabling interrupts, so IMR and SR may not be
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spin_lock_bh(&host->lock);
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clk_enable(host->mck);
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memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
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clk_disable(host->mck);
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spin_unlock_bh(&host->lock);
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seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
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buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
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buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
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buf[ATMCI_MR / 4] & 0xff);
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seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
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seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
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seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
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seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
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buf[ATMCI_BLKR / 4] & 0xffff,
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(buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
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if (host->caps.has_cstor_reg)
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seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
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/* Don't read RSPR and RDR; it will consume the data there */
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atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
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atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
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if (host->caps.has_dma) {
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val = buf[ATMCI_DMA / 4];
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seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
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1 << (((val >> 4) & 3) + 1) : 1,
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val & ATMCI_DMAEN ? " DMAEN" : "");
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if (host->caps.has_cfg_reg) {
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val = buf[ATMCI_CFG / 4];
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seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
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val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
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val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
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val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
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val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
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static int atmci_regs_open(struct inode *inode, struct file *file)
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return single_open(file, atmci_regs_show, inode->i_private);
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static const struct file_operations atmci_regs_fops = {
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.owner = THIS_MODULE,
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.open = atmci_regs_open,
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.release = single_release,
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static void atmci_init_debugfs(struct atmel_mci_slot *slot)
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struct mmc_host *mmc = slot->mmc;
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struct atmel_mci *host = slot->host;
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root = mmc->debugfs_root;
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node = debugfs_create_file("regs", S_IRUSR, root, host,
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node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
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node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
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node = debugfs_create_x32("pending_events", S_IRUSR, root,
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(u32 *)&host->pending_events);
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node = debugfs_create_x32("completed_events", S_IRUSR, root,
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(u32 *)&host->completed_events);
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dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
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static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
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return (ns * (host->bus_hz / 1000000) + 999) / 1000;
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static void atmci_set_timeout(struct atmel_mci *host,
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struct atmel_mci_slot *slot, struct mmc_data *data)
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static unsigned dtomul_to_shift[] = {
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0, 4, 7, 8, 10, 12, 16, 20
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timeout = atmci_ns_to_clocks(host, data->timeout_ns)
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+ data->timeout_clks;
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for (dtomul = 0; dtomul < 8; dtomul++) {
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unsigned shift = dtomul_to_shift[dtomul];
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dtocyc = (timeout + (1 << shift) - 1) >> shift;
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dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
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dtocyc << dtomul_to_shift[dtomul]);
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atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
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* Return mask with command flags to be enabled for this command.
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static u32 atmci_prepare_command(struct mmc_host *mmc,
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struct mmc_command *cmd)
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struct mmc_data *data;
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cmd->error = -EINPROGRESS;
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cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136)
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cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
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cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
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* This should really be MAXLAT_5 for CMD2 and ACMD41, but
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* it's too difficult to determine whether this is an ACMD or
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* not. Better make it 64.
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cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
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if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
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cmdr |= ATMCI_CMDR_OPDCMD;
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cmdr |= ATMCI_CMDR_START_XFER;
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if (cmd->opcode == SD_IO_RW_EXTENDED) {
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cmdr |= ATMCI_CMDR_SDIO_BLOCK;
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if (data->flags & MMC_DATA_STREAM)
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cmdr |= ATMCI_CMDR_STREAM;
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else if (data->blocks > 1)
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cmdr |= ATMCI_CMDR_MULTI_BLOCK;
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cmdr |= ATMCI_CMDR_BLOCK;
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if (data->flags & MMC_DATA_READ)
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cmdr |= ATMCI_CMDR_TRDIR_READ;
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static void atmci_send_command(struct atmel_mci *host,
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struct mmc_command *cmd, u32 cmd_flags)
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dev_vdbg(&host->pdev->dev,
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"start command: ARGR=0x%08x CMDR=0x%08x\n",
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cmd->arg, cmd_flags);
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atmci_writel(host, ATMCI_ARGR, cmd->arg);
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atmci_writel(host, ATMCI_CMDR, cmd_flags);
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static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
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atmci_send_command(host, data->stop, host->stop_cmdr);
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atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
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* Configure given PDC buffer taking care of alignement issues.
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* Update host->data_size and host->sg.
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static void atmci_pdc_set_single_buf(struct atmel_mci *host,
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enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
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u32 pointer_reg, counter_reg;
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if (dir == XFER_RECEIVE) {
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pointer_reg = ATMEL_PDC_RPR;
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counter_reg = ATMEL_PDC_RCR;
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pointer_reg = ATMEL_PDC_TPR;
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counter_reg = ATMEL_PDC_TCR;
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if (buf_nb == PDC_SECOND_BUF) {
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pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
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counter_reg += ATMEL_PDC_SCND_BUF_OFF;
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atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
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if (host->data_size <= sg_dma_len(host->sg)) {
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if (host->data_size & 0x3) {
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/* If size is different from modulo 4, transfer bytes */
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atmci_writel(host, counter_reg, host->data_size);
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atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
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/* Else transfer 32-bits words */
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atmci_writel(host, counter_reg, host->data_size / 4);
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/* We assume the size of a page is 32-bits aligned */
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atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
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host->data_size -= sg_dma_len(host->sg);
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host->sg = sg_next(host->sg);
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* Configure PDC buffer according to the data size ie configuring one or two
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* buffers. Don't use this function if you want to configure only the second
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* buffer. In this case, use atmci_pdc_set_single_buf.
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static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
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atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
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atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
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* Unmap sg lists, called when transfer is finished.
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static void atmci_pdc_cleanup(struct atmel_mci *host)
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struct mmc_data *data = host->data;
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dma_unmap_sg(&host->pdev->dev,
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data->sg, data->sg_len,
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((data->flags & MMC_DATA_WRITE)
653
? DMA_TO_DEVICE : DMA_FROM_DEVICE));
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* Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
658
* having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
659
* interrupt needed for both transfer directions.
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static void atmci_pdc_complete(struct atmel_mci *host)
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atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
664
atmci_pdc_cleanup(host);
667
* If the card was removed, data will be NULL. No point trying
668
* to send the stop command or waiting for NBUSY in this case.
671
atmci_set_pending(host, EVENT_XFER_COMPLETE);
672
tasklet_schedule(&host->tasklet);
673
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
677
static void atmci_dma_cleanup(struct atmel_mci *host)
679
struct mmc_data *data = host->data;
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dma_unmap_sg(host->dma.chan->device->dev,
683
data->sg, data->sg_len,
684
((data->flags & MMC_DATA_WRITE)
685
? DMA_TO_DEVICE : DMA_FROM_DEVICE));
689
* This function is called by the DMA driver from tasklet context.
691
static void atmci_dma_complete(void *arg)
693
struct atmel_mci *host = arg;
694
struct mmc_data *data = host->data;
696
dev_vdbg(&host->pdev->dev, "DMA complete\n");
698
if (host->caps.has_dma)
699
/* Disable DMA hardware handshaking on MCI */
700
atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
702
atmci_dma_cleanup(host);
705
* If the card was removed, data will be NULL. No point trying
706
* to send the stop command or waiting for NBUSY in this case.
709
atmci_set_pending(host, EVENT_XFER_COMPLETE);
710
tasklet_schedule(&host->tasklet);
713
* Regardless of what the documentation says, we have
714
* to wait for NOTBUSY even after block read
717
* When the DMA transfer is complete, the controller
718
* may still be reading the CRC from the card, i.e.
719
* the data transfer is still in progress and we
720
* haven't seen all the potential error bits yet.
722
* The interrupt handler will schedule a different
723
* tasklet to finish things up when the data transfer
724
* is completely done.
726
* We may not complete the mmc request here anyway
727
* because the mmc layer may call back and cause us to
728
* violate the "don't submit new operations from the
729
* completion callback" rule of the dma engine
732
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
737
* Returns a mask of interrupt flags to be enabled after the whole
738
* request has been prepared.
740
static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
744
data->error = -EINPROGRESS;
748
host->data_chan = NULL;
750
iflags = ATMCI_DATA_ERROR_FLAGS;
753
* Errata: MMC data write operation with less than 12
754
* bytes is impossible.
756
* Errata: MCI Transmit Data Register (TDR) FIFO
757
* corruption when length is not multiple of 4.
759
if (data->blocks * data->blksz < 12
760
|| (data->blocks * data->blksz) & 3)
761
host->need_reset = true;
763
host->pio_offset = 0;
764
if (data->flags & MMC_DATA_READ)
765
iflags |= ATMCI_RXRDY;
767
iflags |= ATMCI_TXRDY;
773
* Set interrupt flags and set block length into the MCI mode register even
774
* if this value is also accessible in the MCI block register. It seems to be
775
* necessary before the High Speed MCI version. It also map sg and configure
779
atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
783
enum dma_data_direction dir;
785
data->error = -EINPROGRESS;
789
iflags = ATMCI_DATA_ERROR_FLAGS;
791
/* Enable pdc mode */
792
atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
794
if (data->flags & MMC_DATA_READ) {
795
dir = DMA_FROM_DEVICE;
796
iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
799
iflags |= ATMCI_ENDTX | ATMCI_TXBUFE;
803
tmp = atmci_readl(host, ATMCI_MR);
805
tmp |= ATMCI_BLKLEN(data->blksz);
806
atmci_writel(host, ATMCI_MR, tmp);
809
host->data_size = data->blocks * data->blksz;
810
sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
812
atmci_pdc_set_both_buf(host,
813
((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
819
atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
821
struct dma_chan *chan;
822
struct dma_async_tx_descriptor *desc;
823
struct scatterlist *sg;
825
enum dma_data_direction direction;
829
data->error = -EINPROGRESS;
835
iflags = ATMCI_DATA_ERROR_FLAGS;
838
* We don't do DMA on "complex" transfers, i.e. with
839
* non-word-aligned buffers or lengths. Also, we don't bother
840
* with all the DMA setup overhead for short transfers.
842
if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
843
return atmci_prepare_data(host, data);
845
return atmci_prepare_data(host, data);
847
for_each_sg(data->sg, sg, data->sg_len, i) {
848
if (sg->offset & 3 || sg->length & 3)
849
return atmci_prepare_data(host, data);
852
/* If we don't have a channel, we can't do DMA */
853
chan = host->dma.chan;
855
host->data_chan = chan;
860
if (host->caps.has_dma)
861
atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
863
if (data->flags & MMC_DATA_READ)
864
direction = DMA_FROM_DEVICE;
866
direction = DMA_TO_DEVICE;
868
sglen = dma_map_sg(chan->device->dev, data->sg,
869
data->sg_len, direction);
871
desc = chan->device->device_prep_slave_sg(chan,
872
data->sg, sglen, direction,
873
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
877
host->dma.data_desc = desc;
878
desc->callback = atmci_dma_complete;
879
desc->callback_param = host;
883
dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
888
atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
894
* Start PDC according to transfer direction.
897
atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
899
if (data->flags & MMC_DATA_READ)
900
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
902
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
906
atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
908
struct dma_chan *chan = host->data_chan;
909
struct dma_async_tx_descriptor *desc = host->dma.data_desc;
912
dmaengine_submit(desc);
913
dma_async_issue_pending(chan);
917
static void atmci_stop_transfer(struct atmel_mci *host)
919
atmci_set_pending(host, EVENT_XFER_COMPLETE);
920
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
924
* Stop data transfer because error(s) occured.
926
static void atmci_stop_transfer_pdc(struct atmel_mci *host)
928
atmci_set_pending(host, EVENT_XFER_COMPLETE);
929
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
932
static void atmci_stop_transfer_dma(struct atmel_mci *host)
934
struct dma_chan *chan = host->data_chan;
937
dmaengine_terminate_all(chan);
938
atmci_dma_cleanup(host);
940
/* Data transfer was stopped by the interrupt handler */
941
atmci_set_pending(host, EVENT_XFER_COMPLETE);
942
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
947
* Start a request: prepare data if needed, prepare the command and activate
950
static void atmci_start_request(struct atmel_mci *host,
951
struct atmel_mci_slot *slot)
953
struct mmc_request *mrq;
954
struct mmc_command *cmd;
955
struct mmc_data *data;
960
host->cur_slot = slot;
963
host->pending_events = 0;
964
host->completed_events = 0;
965
host->data_status = 0;
967
if (host->need_reset) {
968
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
969
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
970
atmci_writel(host, ATMCI_MR, host->mode_reg);
971
if (host->caps.has_cfg_reg)
972
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
973
host->need_reset = false;
975
atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
977
iflags = atmci_readl(host, ATMCI_IMR);
978
if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
979
dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
982
if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
983
/* Send init sequence (74 clock cycles) */
984
atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
985
while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
991
atmci_set_timeout(host, slot, data);
993
/* Must set block count/size before sending command */
994
atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
995
| ATMCI_BLKLEN(data->blksz));
996
dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
997
ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
999
iflags |= host->prepare_data(host, data);
1002
iflags |= ATMCI_CMDRDY;
1004
cmdflags = atmci_prepare_command(slot->mmc, cmd);
1005
atmci_send_command(host, cmd, cmdflags);
1008
host->submit_data(host, data);
1011
host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1012
host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1013
if (!(data->flags & MMC_DATA_WRITE))
1014
host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1015
if (data->flags & MMC_DATA_STREAM)
1016
host->stop_cmdr |= ATMCI_CMDR_STREAM;
1018
host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1022
* We could have enabled interrupts earlier, but I suspect
1023
* that would open up a nice can of interesting race
1024
* conditions (e.g. command and data complete, but stop not
1027
atmci_writel(host, ATMCI_IER, iflags);
1030
static void atmci_queue_request(struct atmel_mci *host,
1031
struct atmel_mci_slot *slot, struct mmc_request *mrq)
1033
dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1036
spin_lock_bh(&host->lock);
1038
if (host->state == STATE_IDLE) {
1039
host->state = STATE_SENDING_CMD;
1040
atmci_start_request(host, slot);
1042
list_add_tail(&slot->queue_node, &host->queue);
1044
spin_unlock_bh(&host->lock);
1047
static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1049
struct atmel_mci_slot *slot = mmc_priv(mmc);
1050
struct atmel_mci *host = slot->host;
1051
struct mmc_data *data;
1056
* We may "know" the card is gone even though there's still an
1057
* electrical connection. If so, we really need to communicate
1058
* this to the MMC core since there won't be any more
1059
* interrupts as the card is completely removed. Otherwise,
1060
* the MMC core might believe the card is still there even
1061
* though the card was just removed very slowly.
1063
if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1064
mrq->cmd->error = -ENOMEDIUM;
1065
mmc_request_done(mmc, mrq);
1069
/* We don't support multiple blocks of weird lengths. */
1071
if (data && data->blocks > 1 && data->blksz & 3) {
1072
mrq->cmd->error = -EINVAL;
1073
mmc_request_done(mmc, mrq);
1076
atmci_queue_request(host, slot, mrq);
1079
static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1081
struct atmel_mci_slot *slot = mmc_priv(mmc);
1082
struct atmel_mci *host = slot->host;
1085
slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1086
switch (ios->bus_width) {
1087
case MMC_BUS_WIDTH_1:
1088
slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1090
case MMC_BUS_WIDTH_4:
1091
slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1096
unsigned int clock_min = ~0U;
1099
spin_lock_bh(&host->lock);
1100
if (!host->mode_reg) {
1101
clk_enable(host->mck);
1102
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1103
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1104
if (host->caps.has_cfg_reg)
1105
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1109
* Use mirror of ios->clock to prevent race with mmc
1110
* core ios update when finding the minimum.
1112
slot->clock = ios->clock;
1113
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1114
if (host->slot[i] && host->slot[i]->clock
1115
&& host->slot[i]->clock < clock_min)
1116
clock_min = host->slot[i]->clock;
1119
/* Calculate clock divider */
1120
clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1122
dev_warn(&mmc->class_dev,
1123
"clock %u too slow; using %lu\n",
1124
clock_min, host->bus_hz / (2 * 256));
1128
host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1131
* WRPROOF and RDPROOF prevent overruns/underruns by
1132
* stopping the clock when the FIFO is full/empty.
1133
* This state is not expected to last for long.
1135
if (host->caps.has_rwproof)
1136
host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1138
if (host->caps.has_cfg_reg) {
1139
/* setup High Speed mode in relation with card capacity */
1140
if (ios->timing == MMC_TIMING_SD_HS)
1141
host->cfg_reg |= ATMCI_CFG_HSMODE;
1143
host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1146
if (list_empty(&host->queue)) {
1147
atmci_writel(host, ATMCI_MR, host->mode_reg);
1148
if (host->caps.has_cfg_reg)
1149
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1151
host->need_clock_update = true;
1154
spin_unlock_bh(&host->lock);
1156
bool any_slot_active = false;
1158
spin_lock_bh(&host->lock);
1160
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1161
if (host->slot[i] && host->slot[i]->clock) {
1162
any_slot_active = true;
1166
if (!any_slot_active) {
1167
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1168
if (host->mode_reg) {
1169
atmci_readl(host, ATMCI_MR);
1170
clk_disable(host->mck);
1174
spin_unlock_bh(&host->lock);
1177
switch (ios->power_mode) {
1179
set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1183
* TODO: None of the currently available AVR32-based
1184
* boards allow MMC power to be turned off. Implement
1185
* power control when this can be tested properly.
1187
* We also need to hook this into the clock management
1188
* somehow so that newly inserted cards aren't
1189
* subjected to a fast clock before we have a chance
1190
* to figure out what the maximum rate is. Currently,
1191
* there's no way to avoid this, and there never will
1192
* be for boards that don't support power control.
1198
static int atmci_get_ro(struct mmc_host *mmc)
1200
int read_only = -ENOSYS;
1201
struct atmel_mci_slot *slot = mmc_priv(mmc);
1203
if (gpio_is_valid(slot->wp_pin)) {
1204
read_only = gpio_get_value(slot->wp_pin);
1205
dev_dbg(&mmc->class_dev, "card is %s\n",
1206
read_only ? "read-only" : "read-write");
1212
static int atmci_get_cd(struct mmc_host *mmc)
1214
int present = -ENOSYS;
1215
struct atmel_mci_slot *slot = mmc_priv(mmc);
1217
if (gpio_is_valid(slot->detect_pin)) {
1218
present = !(gpio_get_value(slot->detect_pin) ^
1219
slot->detect_is_active_high);
1220
dev_dbg(&mmc->class_dev, "card is %spresent\n",
1221
present ? "" : "not ");
1227
static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1229
struct atmel_mci_slot *slot = mmc_priv(mmc);
1230
struct atmel_mci *host = slot->host;
1233
atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1235
atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1238
static const struct mmc_host_ops atmci_ops = {
1239
.request = atmci_request,
1240
.set_ios = atmci_set_ios,
1241
.get_ro = atmci_get_ro,
1242
.get_cd = atmci_get_cd,
1243
.enable_sdio_irq = atmci_enable_sdio_irq,
1246
/* Called with host->lock held */
1247
static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1248
__releases(&host->lock)
1249
__acquires(&host->lock)
1251
struct atmel_mci_slot *slot = NULL;
1252
struct mmc_host *prev_mmc = host->cur_slot->mmc;
1254
WARN_ON(host->cmd || host->data);
1257
* Update the MMC clock rate if necessary. This may be
1258
* necessary if set_ios() is called when a different slot is
1259
* busy transferring data.
1261
if (host->need_clock_update) {
1262
atmci_writel(host, ATMCI_MR, host->mode_reg);
1263
if (host->caps.has_cfg_reg)
1264
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1267
host->cur_slot->mrq = NULL;
1269
if (!list_empty(&host->queue)) {
1270
slot = list_entry(host->queue.next,
1271
struct atmel_mci_slot, queue_node);
1272
list_del(&slot->queue_node);
1273
dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1274
mmc_hostname(slot->mmc));
1275
host->state = STATE_SENDING_CMD;
1276
atmci_start_request(host, slot);
1278
dev_vdbg(&host->pdev->dev, "list empty\n");
1279
host->state = STATE_IDLE;
1282
spin_unlock(&host->lock);
1283
mmc_request_done(prev_mmc, mrq);
1284
spin_lock(&host->lock);
1287
static void atmci_command_complete(struct atmel_mci *host,
1288
struct mmc_command *cmd)
1290
u32 status = host->cmd_status;
1292
/* Read the response from the card (up to 16 bytes) */
1293
cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1294
cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1295
cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1296
cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1298
if (status & ATMCI_RTOE)
1299
cmd->error = -ETIMEDOUT;
1300
else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1301
cmd->error = -EILSEQ;
1302
else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1308
dev_dbg(&host->pdev->dev,
1309
"command error: status=0x%08x\n", status);
1312
host->stop_transfer(host);
1314
atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY
1315
| ATMCI_TXRDY | ATMCI_RXRDY
1316
| ATMCI_DATA_ERROR_FLAGS);
1321
static void atmci_detect_change(unsigned long data)
1323
struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1328
* atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1329
* freeing the interrupt. We must not re-enable the interrupt
1330
* if it has been freed, and if we're shutting down, it
1331
* doesn't really matter whether the card is present or not.
1334
if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1337
enable_irq(gpio_to_irq(slot->detect_pin));
1338
present = !(gpio_get_value(slot->detect_pin) ^
1339
slot->detect_is_active_high);
1340
present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1342
dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1343
present, present_old);
1345
if (present != present_old) {
1346
struct atmel_mci *host = slot->host;
1347
struct mmc_request *mrq;
1349
dev_dbg(&slot->mmc->class_dev, "card %s\n",
1350
present ? "inserted" : "removed");
1352
spin_lock(&host->lock);
1355
clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1357
set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1359
/* Clean up queue if present */
1362
if (mrq == host->mrq) {
1364
* Reset controller to terminate any ongoing
1365
* commands or data transfers.
1367
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1368
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1369
atmci_writel(host, ATMCI_MR, host->mode_reg);
1370
if (host->caps.has_cfg_reg)
1371
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1376
switch (host->state) {
1379
case STATE_SENDING_CMD:
1380
mrq->cmd->error = -ENOMEDIUM;
1384
case STATE_SENDING_DATA:
1385
mrq->data->error = -ENOMEDIUM;
1386
host->stop_transfer(host);
1388
case STATE_DATA_BUSY:
1389
case STATE_DATA_ERROR:
1390
if (mrq->data->error == -EINPROGRESS)
1391
mrq->data->error = -ENOMEDIUM;
1395
case STATE_SENDING_STOP:
1396
mrq->stop->error = -ENOMEDIUM;
1400
atmci_request_end(host, mrq);
1402
list_del(&slot->queue_node);
1403
mrq->cmd->error = -ENOMEDIUM;
1405
mrq->data->error = -ENOMEDIUM;
1407
mrq->stop->error = -ENOMEDIUM;
1409
spin_unlock(&host->lock);
1410
mmc_request_done(slot->mmc, mrq);
1411
spin_lock(&host->lock);
1414
spin_unlock(&host->lock);
1416
mmc_detect_change(slot->mmc, 0);
1420
static void atmci_tasklet_func(unsigned long priv)
1422
struct atmel_mci *host = (struct atmel_mci *)priv;
1423
struct mmc_request *mrq = host->mrq;
1424
struct mmc_data *data = host->data;
1425
struct mmc_command *cmd = host->cmd;
1426
enum atmel_mci_state state = host->state;
1427
enum atmel_mci_state prev_state;
1430
spin_lock(&host->lock);
1432
state = host->state;
1434
dev_vdbg(&host->pdev->dev,
1435
"tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1436
state, host->pending_events, host->completed_events,
1437
atmci_readl(host, ATMCI_IMR));
1446
case STATE_SENDING_CMD:
1447
if (!atmci_test_and_clear_pending(host,
1448
EVENT_CMD_COMPLETE))
1452
atmci_set_completed(host, EVENT_CMD_COMPLETE);
1453
atmci_command_complete(host, mrq->cmd);
1454
if (!mrq->data || cmd->error) {
1455
atmci_request_end(host, host->mrq);
1459
prev_state = state = STATE_SENDING_DATA;
1462
case STATE_SENDING_DATA:
1463
if (atmci_test_and_clear_pending(host,
1464
EVENT_DATA_ERROR)) {
1465
host->stop_transfer(host);
1467
atmci_send_stop_cmd(host, data);
1468
state = STATE_DATA_ERROR;
1472
if (!atmci_test_and_clear_pending(host,
1473
EVENT_XFER_COMPLETE))
1476
atmci_set_completed(host, EVENT_XFER_COMPLETE);
1477
prev_state = state = STATE_DATA_BUSY;
1480
case STATE_DATA_BUSY:
1481
if (!atmci_test_and_clear_pending(host,
1482
EVENT_DATA_COMPLETE))
1486
atmci_set_completed(host, EVENT_DATA_COMPLETE);
1487
status = host->data_status;
1488
if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1489
if (status & ATMCI_DTOE) {
1490
dev_dbg(&host->pdev->dev,
1491
"data timeout error\n");
1492
data->error = -ETIMEDOUT;
1493
} else if (status & ATMCI_DCRCE) {
1494
dev_dbg(&host->pdev->dev,
1495
"data CRC error\n");
1496
data->error = -EILSEQ;
1498
dev_dbg(&host->pdev->dev,
1499
"data FIFO error (status=%08x)\n",
1504
data->bytes_xfered = data->blocks * data->blksz;
1506
atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS);
1510
atmci_request_end(host, host->mrq);
1514
prev_state = state = STATE_SENDING_STOP;
1516
atmci_send_stop_cmd(host, data);
1519
case STATE_SENDING_STOP:
1520
if (!atmci_test_and_clear_pending(host,
1521
EVENT_CMD_COMPLETE))
1525
atmci_command_complete(host, mrq->stop);
1526
atmci_request_end(host, host->mrq);
1529
case STATE_DATA_ERROR:
1530
if (!atmci_test_and_clear_pending(host,
1531
EVENT_XFER_COMPLETE))
1534
state = STATE_DATA_BUSY;
1537
} while (state != prev_state);
1539
host->state = state;
1542
spin_unlock(&host->lock);
1545
static void atmci_read_data_pio(struct atmel_mci *host)
1547
struct scatterlist *sg = host->sg;
1548
void *buf = sg_virt(sg);
1549
unsigned int offset = host->pio_offset;
1550
struct mmc_data *data = host->data;
1553
unsigned int nbytes = 0;
1556
value = atmci_readl(host, ATMCI_RDR);
1557
if (likely(offset + 4 <= sg->length)) {
1558
put_unaligned(value, (u32 *)(buf + offset));
1563
if (offset == sg->length) {
1564
flush_dcache_page(sg_page(sg));
1565
host->sg = sg = sg_next(sg);
1573
unsigned int remaining = sg->length - offset;
1574
memcpy(buf + offset, &value, remaining);
1575
nbytes += remaining;
1577
flush_dcache_page(sg_page(sg));
1578
host->sg = sg = sg_next(sg);
1582
offset = 4 - remaining;
1584
memcpy(buf, (u8 *)&value + remaining, offset);
1588
status = atmci_readl(host, ATMCI_SR);
1589
if (status & ATMCI_DATA_ERROR_FLAGS) {
1590
atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1591
| ATMCI_DATA_ERROR_FLAGS));
1592
host->data_status = status;
1593
data->bytes_xfered += nbytes;
1595
atmci_set_pending(host, EVENT_DATA_ERROR);
1596
tasklet_schedule(&host->tasklet);
1599
} while (status & ATMCI_RXRDY);
1601
host->pio_offset = offset;
1602
data->bytes_xfered += nbytes;
1607
atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1608
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1609
data->bytes_xfered += nbytes;
1611
atmci_set_pending(host, EVENT_XFER_COMPLETE);
1614
static void atmci_write_data_pio(struct atmel_mci *host)
1616
struct scatterlist *sg = host->sg;
1617
void *buf = sg_virt(sg);
1618
unsigned int offset = host->pio_offset;
1619
struct mmc_data *data = host->data;
1622
unsigned int nbytes = 0;
1625
if (likely(offset + 4 <= sg->length)) {
1626
value = get_unaligned((u32 *)(buf + offset));
1627
atmci_writel(host, ATMCI_TDR, value);
1631
if (offset == sg->length) {
1632
host->sg = sg = sg_next(sg);
1640
unsigned int remaining = sg->length - offset;
1643
memcpy(&value, buf + offset, remaining);
1644
nbytes += remaining;
1646
host->sg = sg = sg_next(sg);
1648
atmci_writel(host, ATMCI_TDR, value);
1652
offset = 4 - remaining;
1654
memcpy((u8 *)&value + remaining, buf, offset);
1655
atmci_writel(host, ATMCI_TDR, value);
1659
status = atmci_readl(host, ATMCI_SR);
1660
if (status & ATMCI_DATA_ERROR_FLAGS) {
1661
atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1662
| ATMCI_DATA_ERROR_FLAGS));
1663
host->data_status = status;
1664
data->bytes_xfered += nbytes;
1666
atmci_set_pending(host, EVENT_DATA_ERROR);
1667
tasklet_schedule(&host->tasklet);
1670
} while (status & ATMCI_TXRDY);
1672
host->pio_offset = offset;
1673
data->bytes_xfered += nbytes;
1678
atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1679
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1680
data->bytes_xfered += nbytes;
1682
atmci_set_pending(host, EVENT_XFER_COMPLETE);
1685
static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1687
atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
1689
host->cmd_status = status;
1691
atmci_set_pending(host, EVENT_CMD_COMPLETE);
1692
tasklet_schedule(&host->tasklet);
1695
static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1699
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1700
struct atmel_mci_slot *slot = host->slot[i];
1701
if (slot && (status & slot->sdio_irq)) {
1702
mmc_signal_sdio_irq(slot->mmc);
1708
static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1710
struct atmel_mci *host = dev_id;
1711
u32 status, mask, pending;
1712
unsigned int pass_count = 0;
1715
status = atmci_readl(host, ATMCI_SR);
1716
mask = atmci_readl(host, ATMCI_IMR);
1717
pending = status & mask;
1721
if (pending & ATMCI_DATA_ERROR_FLAGS) {
1722
atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1723
| ATMCI_RXRDY | ATMCI_TXRDY);
1724
pending &= atmci_readl(host, ATMCI_IMR);
1726
host->data_status = status;
1728
atmci_set_pending(host, EVENT_DATA_ERROR);
1729
tasklet_schedule(&host->tasklet);
1732
if (pending & ATMCI_TXBUFE) {
1733
atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1734
atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1736
* We can receive this interruption before having configured
1737
* the second pdc buffer, so we need to reconfigure first and
1738
* second buffers again
1740
if (host->data_size) {
1741
atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1742
atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1743
atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1745
atmci_pdc_complete(host);
1747
} else if (pending & ATMCI_ENDTX) {
1748
atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1750
if (host->data_size) {
1751
atmci_pdc_set_single_buf(host,
1752
XFER_TRANSMIT, PDC_SECOND_BUF);
1753
atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1757
if (pending & ATMCI_RXBUFF) {
1758
atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
1759
atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1761
* We can receive this interruption before having configured
1762
* the second pdc buffer, so we need to reconfigure first and
1763
* second buffers again
1765
if (host->data_size) {
1766
atmci_pdc_set_both_buf(host, XFER_RECEIVE);
1767
atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1768
atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1770
atmci_pdc_complete(host);
1772
} else if (pending & ATMCI_ENDRX) {
1773
atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1775
if (host->data_size) {
1776
atmci_pdc_set_single_buf(host,
1777
XFER_RECEIVE, PDC_SECOND_BUF);
1778
atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1783
if (pending & ATMCI_NOTBUSY) {
1784
atmci_writel(host, ATMCI_IDR,
1785
ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
1786
if (!host->data_status)
1787
host->data_status = status;
1789
atmci_set_pending(host, EVENT_DATA_COMPLETE);
1790
tasklet_schedule(&host->tasklet);
1792
if (pending & ATMCI_RXRDY)
1793
atmci_read_data_pio(host);
1794
if (pending & ATMCI_TXRDY)
1795
atmci_write_data_pio(host);
1797
if (pending & ATMCI_CMDRDY)
1798
atmci_cmd_interrupt(host, status);
1800
if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1801
atmci_sdio_interrupt(host, status);
1803
} while (pass_count++ < 5);
1805
return pass_count ? IRQ_HANDLED : IRQ_NONE;
1808
static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1810
struct atmel_mci_slot *slot = dev_id;
1813
* Disable interrupts until the pin has stabilized and check
1814
* the state then. Use mod_timer() since we may be in the
1815
* middle of the timer routine when this interrupt triggers.
1817
disable_irq_nosync(irq);
1818
mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1823
static int __init atmci_init_slot(struct atmel_mci *host,
1824
struct mci_slot_pdata *slot_data, unsigned int id,
1825
u32 sdc_reg, u32 sdio_irq)
1827
struct mmc_host *mmc;
1828
struct atmel_mci_slot *slot;
1830
mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1834
slot = mmc_priv(mmc);
1837
slot->detect_pin = slot_data->detect_pin;
1838
slot->wp_pin = slot_data->wp_pin;
1839
slot->detect_is_active_high = slot_data->detect_is_active_high;
1840
slot->sdc_reg = sdc_reg;
1841
slot->sdio_irq = sdio_irq;
1843
mmc->ops = &atmci_ops;
1844
mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1845
mmc->f_max = host->bus_hz / 2;
1846
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1848
mmc->caps |= MMC_CAP_SDIO_IRQ;
1849
if (host->caps.has_highspeed)
1850
mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1851
if (slot_data->bus_width >= 4)
1852
mmc->caps |= MMC_CAP_4_BIT_DATA;
1855
mmc->max_req_size = 32768 * 512;
1856
mmc->max_blk_size = 32768;
1857
mmc->max_blk_count = 512;
1859
/* Assume card is present initially */
1860
set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1861
if (gpio_is_valid(slot->detect_pin)) {
1862
if (gpio_request(slot->detect_pin, "mmc_detect")) {
1863
dev_dbg(&mmc->class_dev, "no detect pin available\n");
1864
slot->detect_pin = -EBUSY;
1865
} else if (gpio_get_value(slot->detect_pin) ^
1866
slot->detect_is_active_high) {
1867
clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1871
if (!gpio_is_valid(slot->detect_pin))
1872
mmc->caps |= MMC_CAP_NEEDS_POLL;
1874
if (gpio_is_valid(slot->wp_pin)) {
1875
if (gpio_request(slot->wp_pin, "mmc_wp")) {
1876
dev_dbg(&mmc->class_dev, "no WP pin available\n");
1877
slot->wp_pin = -EBUSY;
1881
host->slot[id] = slot;
1884
if (gpio_is_valid(slot->detect_pin)) {
1887
setup_timer(&slot->detect_timer, atmci_detect_change,
1888
(unsigned long)slot);
1890
ret = request_irq(gpio_to_irq(slot->detect_pin),
1891
atmci_detect_interrupt,
1892
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1893
"mmc-detect", slot);
1895
dev_dbg(&mmc->class_dev,
1896
"could not request IRQ %d for detect pin\n",
1897
gpio_to_irq(slot->detect_pin));
1898
gpio_free(slot->detect_pin);
1899
slot->detect_pin = -EBUSY;
1903
atmci_init_debugfs(slot);
1908
static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1911
/* Debugfs stuff is cleaned up by mmc core */
1913
set_bit(ATMCI_SHUTDOWN, &slot->flags);
1916
mmc_remove_host(slot->mmc);
1918
if (gpio_is_valid(slot->detect_pin)) {
1919
int pin = slot->detect_pin;
1921
free_irq(gpio_to_irq(pin), slot);
1922
del_timer_sync(&slot->detect_timer);
1925
if (gpio_is_valid(slot->wp_pin))
1926
gpio_free(slot->wp_pin);
1928
slot->host->slot[id] = NULL;
1929
mmc_free_host(slot->mmc);
1932
static bool atmci_filter(struct dma_chan *chan, void *slave)
1934
struct mci_dma_data *sl = slave;
1936
if (sl && find_slave_dev(sl) == chan->device->dev) {
1937
chan->private = slave_data_ptr(sl);
1944
static void atmci_configure_dma(struct atmel_mci *host)
1946
struct mci_platform_data *pdata;
1951
pdata = host->pdev->dev.platform_data;
1953
if (pdata && find_slave_dev(pdata->dma_slave)) {
1954
dma_cap_mask_t mask;
1956
setup_dma_addr(pdata->dma_slave,
1957
host->mapbase + ATMCI_TDR,
1958
host->mapbase + ATMCI_RDR);
1960
/* Try to grab a DMA channel */
1962
dma_cap_set(DMA_SLAVE, mask);
1964
dma_request_channel(mask, atmci_filter, pdata->dma_slave);
1966
if (!host->dma.chan)
1967
dev_notice(&host->pdev->dev, "DMA not available, using PIO\n");
1969
dev_info(&host->pdev->dev,
1970
"Using %s for DMA transfers\n",
1971
dma_chan_name(host->dma.chan));
1974
static inline unsigned int atmci_get_version(struct atmel_mci *host)
1976
return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
1980
* HSMCI (High Speed MCI) module is not fully compatible with MCI module.
1981
* HSMCI provides DMA support and a new config register but no more supports
1984
static void __init atmci_get_cap(struct atmel_mci *host)
1986
unsigned int version;
1988
version = atmci_get_version(host);
1989
dev_info(&host->pdev->dev,
1990
"version: 0x%x\n", version);
1992
host->caps.has_dma = 0;
1993
host->caps.has_pdc = 0;
1994
host->caps.has_cfg_reg = 0;
1995
host->caps.has_cstor_reg = 0;
1996
host->caps.has_highspeed = 0;
1997
host->caps.has_rwproof = 0;
1999
/* keep only major version number */
2000
switch (version & 0xf00) {
2003
host->caps.has_pdc = 1;
2004
host->caps.has_rwproof = 1;
2009
#ifdef CONFIG_AT_HDMAC
2010
host->caps.has_dma = 1;
2012
host->caps.has_dma = 0;
2013
dev_info(&host->pdev->dev,
2014
"has dma capability but dma engine is not selected, then use pio\n");
2016
host->caps.has_cfg_reg = 1;
2017
host->caps.has_cstor_reg = 1;
2018
host->caps.has_highspeed = 1;
2019
host->caps.has_rwproof = 1;
2022
dev_warn(&host->pdev->dev,
2023
"Unmanaged mci version, set minimum capabilities\n");
2028
static int __init atmci_probe(struct platform_device *pdev)
2030
struct mci_platform_data *pdata;
2031
struct atmel_mci *host;
2032
struct resource *regs;
2033
unsigned int nr_slots;
2037
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2040
pdata = pdev->dev.platform_data;
2043
irq = platform_get_irq(pdev, 0);
2047
host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2052
spin_lock_init(&host->lock);
2053
INIT_LIST_HEAD(&host->queue);
2055
host->mck = clk_get(&pdev->dev, "mci_clk");
2056
if (IS_ERR(host->mck)) {
2057
ret = PTR_ERR(host->mck);
2062
host->regs = ioremap(regs->start, resource_size(regs));
2066
clk_enable(host->mck);
2067
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2068
host->bus_hz = clk_get_rate(host->mck);
2069
clk_disable(host->mck);
2071
host->mapbase = regs->start;
2073
tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2075
ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2077
goto err_request_irq;
2079
/* Get MCI capabilities and set operations according to it */
2080
atmci_get_cap(host);
2081
if (host->caps.has_dma) {
2082
dev_info(&pdev->dev, "using DMA\n");
2083
host->prepare_data = &atmci_prepare_data_dma;
2084
host->submit_data = &atmci_submit_data_dma;
2085
host->stop_transfer = &atmci_stop_transfer_dma;
2086
} else if (host->caps.has_pdc) {
2087
dev_info(&pdev->dev, "using PDC\n");
2088
host->prepare_data = &atmci_prepare_data_pdc;
2089
host->submit_data = &atmci_submit_data_pdc;
2090
host->stop_transfer = &atmci_stop_transfer_pdc;
2092
dev_info(&pdev->dev, "no DMA, no PDC\n");
2093
host->prepare_data = &atmci_prepare_data;
2094
host->submit_data = &atmci_submit_data;
2095
host->stop_transfer = &atmci_stop_transfer;
2098
if (host->caps.has_dma)
2099
atmci_configure_dma(host);
2101
platform_set_drvdata(pdev, host);
2103
/* We need at least one slot to succeed */
2106
if (pdata->slot[0].bus_width) {
2107
ret = atmci_init_slot(host, &pdata->slot[0],
2108
0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2112
if (pdata->slot[1].bus_width) {
2113
ret = atmci_init_slot(host, &pdata->slot[1],
2114
1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2120
dev_err(&pdev->dev, "init failed: no slot defined\n");
2124
dev_info(&pdev->dev,
2125
"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2126
host->mapbase, irq, nr_slots);
2132
dma_release_channel(host->dma.chan);
2133
free_irq(irq, host);
2135
iounmap(host->regs);
2143
static int __exit atmci_remove(struct platform_device *pdev)
2145
struct atmel_mci *host = platform_get_drvdata(pdev);
2148
platform_set_drvdata(pdev, NULL);
2150
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2152
atmci_cleanup_slot(host->slot[i], i);
2155
clk_enable(host->mck);
2156
atmci_writel(host, ATMCI_IDR, ~0UL);
2157
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2158
atmci_readl(host, ATMCI_SR);
2159
clk_disable(host->mck);
2161
#ifdef CONFIG_MMC_ATMELMCI_DMA
2163
dma_release_channel(host->dma.chan);
2166
free_irq(platform_get_irq(pdev, 0), host);
2167
iounmap(host->regs);
2176
static int atmci_suspend(struct device *dev)
2178
struct atmel_mci *host = dev_get_drvdata(dev);
2181
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2182
struct atmel_mci_slot *slot = host->slot[i];
2187
ret = mmc_suspend_host(slot->mmc);
2190
slot = host->slot[i];
2192
&& test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2193
mmc_resume_host(host->slot[i]->mmc);
2194
clear_bit(ATMCI_SUSPENDED, &slot->flags);
2199
set_bit(ATMCI_SUSPENDED, &slot->flags);
2206
static int atmci_resume(struct device *dev)
2208
struct atmel_mci *host = dev_get_drvdata(dev);
2212
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2213
struct atmel_mci_slot *slot = host->slot[i];
2216
slot = host->slot[i];
2219
if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2221
err = mmc_resume_host(slot->mmc);
2225
clear_bit(ATMCI_SUSPENDED, &slot->flags);
2230
static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2231
#define ATMCI_PM_OPS (&atmci_pm)
2233
#define ATMCI_PM_OPS NULL
2236
static struct platform_driver atmci_driver = {
2237
.remove = __exit_p(atmci_remove),
2239
.name = "atmel_mci",
2244
static int __init atmci_init(void)
2246
return platform_driver_probe(&atmci_driver, atmci_probe);
2249
static void __exit atmci_exit(void)
2251
platform_driver_unregister(&atmci_driver);
2254
late_initcall(atmci_init); /* try to load after dma driver when built-in */
2255
module_exit(atmci_exit);
2257
MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2258
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2259
MODULE_LICENSE("GPL v2");