2
* wm8955.c -- WM8955 ALSA SoC Audio driver
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* Copyright 2009 Wolfson Microelectronics plc
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/wm8955.h>
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#define WM8955_NUM_SUPPLIES 4
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static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
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/* codec private data */
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enum snd_soc_control_type control_type;
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unsigned int mclk_rate;
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struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
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static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
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0x0079, /* R2 - LOUT1 volume */
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0x0079, /* R3 - ROUT1 volume */
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0x0008, /* R5 - DAC Control */
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0x000A, /* R7 - Audio Interface */
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0x0000, /* R8 - Sample Rate */
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0x00FF, /* R10 - Left DAC volume */
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0x00FF, /* R11 - Right DAC volume */
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0x000F, /* R12 - Bass control */
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0x000F, /* R13 - Treble control */
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0x0000, /* R15 - Reset */
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0x00C1, /* R23 - Additional control (1) */
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0x0000, /* R24 - Additional control (2) */
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0x0000, /* R25 - Power Management (1) */
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0x0000, /* R26 - Power Management (2) */
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0x0000, /* R27 - Additional Control (3) */
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0x0050, /* R34 - Left out Mix (1) */
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0x0050, /* R35 - Left out Mix (2) */
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0x0050, /* R36 - Right out Mix (1) */
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0x0050, /* R37 - Right Out Mix (2) */
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0x0050, /* R38 - Mono out Mix (1) */
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0x0050, /* R39 - Mono out Mix (2) */
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0x0079, /* R40 - LOUT2 volume */
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0x0079, /* R41 - ROUT2 volume */
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0x0079, /* R42 - MONOOUT volume */
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0x0000, /* R43 - Clocking / PLL */
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0x0103, /* R44 - PLL Control 1 */
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0x0024, /* R45 - PLL Control 2 */
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0x01BA, /* R46 - PLL Control 3 */
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0x0000, /* R59 - PLL Control 4 */
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static int wm8955_reset(struct snd_soc_codec *codec)
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return snd_soc_write(codec, WM8955_RESET, 0);
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/* The size in bits of the FLL divide multiplied by 10
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* to allow rounding later */
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#define FIXED_FLL_SIZE ((1 << 22) * 10)
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static int wm8995_pll_factors(struct device *dev,
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int Fref, int Fout, struct pll_factors *pll)
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unsigned int K, Ndiv, Nmod, target;
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dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
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/* The oscilator should run at should be 90-100MHz, and
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* there's a divide by 4 plus an optional divide by 2 in the
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* output path to generate the system clock. The clock table
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* is sortd so we should always generate a suitable target. */
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if (target < 90000000) {
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WARN_ON(target < 90000000 || target > 100000000);
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dev_dbg(dev, "Fvco=%dHz\n", target);
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/* Now, calculate N.K */
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Ndiv = target / Fref;
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Nmod = target % Fref;
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dev_dbg(dev, "Nmod=%d\n", Nmod);
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/* Calculate fractional part - scale up so we can round. */
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Kpart = FIXED_FLL_SIZE * (long long)Nmod;
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K = Kpart & 0xFFFFFFFF;
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/* Move down to proper range now rounding is done */
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dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
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/* Lookup table specifying SRATE (table 25 in datasheet); some of the
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* output frequencies have been rounded to the standard frequencies
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* they are intended to match where the error is slight. */
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{ 18432000, 8000, 0, 3, },
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{ 18432000, 12000, 0, 9, },
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{ 18432000, 16000, 0, 11, },
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{ 18432000, 24000, 0, 29, },
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{ 18432000, 32000, 0, 13, },
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{ 18432000, 48000, 0, 1, },
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{ 18432000, 96000, 0, 15, },
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{ 16934400, 8018, 0, 19, },
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{ 16934400, 11025, 0, 25, },
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{ 16934400, 22050, 0, 27, },
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{ 16934400, 44100, 0, 17, },
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{ 16934400, 88200, 0, 31, },
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{ 12000000, 8000, 1, 2, },
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{ 12000000, 11025, 1, 25, },
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{ 12000000, 12000, 1, 8, },
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{ 12000000, 16000, 1, 10, },
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{ 12000000, 22050, 1, 27, },
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{ 12000000, 24000, 1, 28, },
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{ 12000000, 32000, 1, 12, },
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{ 12000000, 44100, 1, 17, },
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{ 12000000, 48000, 1, 0, },
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{ 12000000, 88200, 1, 31, },
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{ 12000000, 96000, 1, 14, },
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{ 12288000, 8000, 0, 2, },
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{ 12288000, 12000, 0, 8, },
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{ 12288000, 16000, 0, 10, },
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{ 12288000, 24000, 0, 28, },
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{ 12288000, 32000, 0, 12, },
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{ 12288000, 48000, 0, 0, },
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{ 12288000, 96000, 0, 14, },
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{ 12289600, 8018, 0, 18, },
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{ 12289600, 11025, 0, 24, },
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{ 12289600, 22050, 0, 26, },
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{ 11289600, 44100, 0, 16, },
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{ 11289600, 88200, 0, 31, },
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static int wm8955_configure_clocking(struct snd_soc_codec *codec)
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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struct pll_factors pll;
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/* If we're not running a sample rate currently just pick one */
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/* Can we generate an exact output? */
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for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
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if (wm8955->fs != clock_cfgs[i].fs)
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if (wm8955->mclk_rate == clock_cfgs[i].mclk)
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/* We should never get here with an unsupported sample rate */
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dev_err(codec->dev, "Sample rate %dHz unsupported\n",
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if (i == ARRAY_SIZE(clock_cfgs)) {
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/* If we can't generate the right clock from MCLK then
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* we should configure the PLL to supply us with an
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clocking |= WM8955_MCLKSEL;
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/* Use the last divider configuration we saw for the
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ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
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clock_cfgs[sr].mclk, &pll);
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"Unable to generate %dHz from %dHz MCLK\n",
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wm8955->fs, wm8955->mclk_rate);
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
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WM8955_N_MASK | WM8955_K_21_18_MASK,
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(pll.n << WM8955_N_SHIFT) |
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
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(pll.k >> 9) & WM8955_K_17_9_MASK);
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
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pll.k & WM8955_K_8_0_MASK);
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
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WM8955_KEN, WM8955_KEN);
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snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
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val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
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/* Now start the PLL running */
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snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
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WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
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snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
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WM8955_PLLEN, WM8955_PLLEN);
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srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
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snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
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WM8955_USB | WM8955_SR_MASK, srate);
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snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
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WM8955_MCLKSEL, clocking);
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static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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struct snd_soc_codec *codec = w->codec;
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/* Always disable the clocks - if we're doing reconfiguration this
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* avoids misclocking.
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snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
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snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
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WM8955_PLL_RB | WM8955_PLLEN, 0);
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_PRE_PMU:
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ret = wm8955_configure_clocking(codec);
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static int deemph_settings[] = { 0, 32000, 44100, 48000 };
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static int wm8955_set_deemph(struct snd_soc_codec *codec)
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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/* If we're using deemphasis select the nearest available sample
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if (wm8955->deemph) {
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for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
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if (abs(deemph_settings[i] - wm8955->fs) <
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abs(deemph_settings[best] - wm8955->fs))
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val = best << WM8955_DEEMPH_SHIFT;
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dev_dbg(codec->dev, "Set deemphasis %d\n", val);
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return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
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WM8955_DEEMPH_MASK, val);
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static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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ucontrol->value.enumerated.item[0] = wm8955->deemph;
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static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
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int deemph = ucontrol->value.enumerated.item[0];
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wm8955->deemph = deemph;
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return wm8955_set_deemph(codec);
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static const char *bass_mode_text[] = {
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"Linear", "Adaptive",
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static const struct soc_enum bass_mode =
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SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
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static const char *bass_cutoff_text[] = {
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static const struct soc_enum bass_cutoff =
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SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
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static const char *treble_cutoff_text[] = {
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static const struct soc_enum treble_cutoff =
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SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
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static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
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static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
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static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
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static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
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static const struct snd_kcontrol_new wm8955_snd_controls[] = {
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SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
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WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
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SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
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SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
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wm8955_get_deemph, wm8955_put_deemph),
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SOC_ENUM("Bass Mode", bass_mode),
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SOC_ENUM("Bass Cutoff", bass_cutoff),
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SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
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SOC_ENUM("Treble Cutoff", treble_cutoff),
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SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
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SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
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SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
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SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
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SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
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/* Not a stereo pair so they line up with the DAPM switches */
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SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
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SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
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SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
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WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
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SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
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WM8955_ROUT1_VOLUME, 7, 1, 0),
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SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
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WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
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SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
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WM8955_ROUT2_VOLUME, 7, 1, 0),
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SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
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SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
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static const struct snd_kcontrol_new lmixer[] = {
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SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
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SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
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SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
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static const struct snd_kcontrol_new rmixer[] = {
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SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
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SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
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SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
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SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
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static const struct snd_kcontrol_new mmixer[] = {
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SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
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SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
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SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
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SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
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static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
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SND_SOC_DAPM_INPUT("MONOIN-"),
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SND_SOC_DAPM_INPUT("MONOIN+"),
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SND_SOC_DAPM_INPUT("LINEINR"),
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SND_SOC_DAPM_INPUT("LINEINL"),
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SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
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SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
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SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
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SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
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SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
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SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
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SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
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SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
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SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
512
SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
513
SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
515
/* The names are chosen to make the control names nice */
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SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
517
lmixer, ARRAY_SIZE(lmixer)),
518
SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
519
rmixer, ARRAY_SIZE(rmixer)),
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SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
521
mmixer, ARRAY_SIZE(mmixer)),
523
SND_SOC_DAPM_OUTPUT("LOUT1"),
524
SND_SOC_DAPM_OUTPUT("ROUT1"),
525
SND_SOC_DAPM_OUTPUT("LOUT2"),
526
SND_SOC_DAPM_OUTPUT("ROUT2"),
527
SND_SOC_DAPM_OUTPUT("MONOOUT"),
528
SND_SOC_DAPM_OUTPUT("OUT3"),
531
static const struct snd_soc_dapm_route wm8955_intercon[] = {
532
{ "DACL", NULL, "SYSCLK" },
533
{ "DACR", NULL, "SYSCLK" },
535
{ "Mono Input", NULL, "MONOIN-" },
536
{ "Mono Input", NULL, "MONOIN+" },
538
{ "Left", "Playback Switch", "DACL" },
539
{ "Left", "Right Playback Switch", "DACR" },
540
{ "Left", "Bypass Switch", "LINEINL" },
541
{ "Left", "Mono Switch", "Mono Input" },
543
{ "Right", "Playback Switch", "DACR" },
544
{ "Right", "Left Playback Switch", "DACL" },
545
{ "Right", "Bypass Switch", "LINEINR" },
546
{ "Right", "Mono Switch", "Mono Input" },
548
{ "Mono", "Left Playback Switch", "DACL" },
549
{ "Mono", "Right Playback Switch", "DACR" },
550
{ "Mono", "Left Bypass Switch", "LINEINL" },
551
{ "Mono", "Right Bypass Switch", "LINEINR" },
553
{ "LOUT1 PGA", NULL, "Left" },
554
{ "LOUT1", NULL, "TSDEN" },
555
{ "LOUT1", NULL, "LOUT1 PGA" },
557
{ "ROUT1 PGA", NULL, "Right" },
558
{ "ROUT1", NULL, "TSDEN" },
559
{ "ROUT1", NULL, "ROUT1 PGA" },
561
{ "LOUT2 PGA", NULL, "Left" },
562
{ "LOUT2", NULL, "TSDEN" },
563
{ "LOUT2", NULL, "LOUT2 PGA" },
565
{ "ROUT2 PGA", NULL, "Right" },
566
{ "ROUT2", NULL, "TSDEN" },
567
{ "ROUT2", NULL, "ROUT2 PGA" },
569
{ "MOUT PGA", NULL, "Mono" },
570
{ "MONOOUT", NULL, "MOUT PGA" },
572
/* OUT3 not currently implemented */
573
{ "OUT3", NULL, "OUT3 PGA" },
576
static int wm8955_add_widgets(struct snd_soc_codec *codec)
578
struct snd_soc_dapm_context *dapm = &codec->dapm;
580
snd_soc_add_controls(codec, wm8955_snd_controls,
581
ARRAY_SIZE(wm8955_snd_controls));
583
snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets,
584
ARRAY_SIZE(wm8955_dapm_widgets));
585
snd_soc_dapm_add_routes(dapm, wm8955_intercon,
586
ARRAY_SIZE(wm8955_intercon));
591
static int wm8955_hw_params(struct snd_pcm_substream *substream,
592
struct snd_pcm_hw_params *params,
593
struct snd_soc_dai *dai)
595
struct snd_soc_codec *codec = dai->codec;
596
struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
600
switch (params_format(params)) {
601
case SNDRV_PCM_FORMAT_S16_LE:
604
case SNDRV_PCM_FORMAT_S20_3LE:
607
case SNDRV_PCM_FORMAT_S24_LE:
610
case SNDRV_PCM_FORMAT_S32_LE:
616
snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
619
wm8955->fs = params_rate(params);
620
wm8955_set_deemph(codec);
622
/* If the chip is clocked then disable the clocks and force a
623
* reconfiguration, otherwise DAPM will power up the
624
* clocks for us later. */
625
ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
628
if (ret & WM8955_DIGENB) {
629
snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
631
snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
632
WM8955_PLL_RB | WM8955_PLLEN, 0);
634
wm8955_configure_clocking(codec);
641
static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
642
unsigned int freq, int dir)
644
struct snd_soc_codec *codec = dai->codec;
645
struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
649
case WM8955_CLK_MCLK:
650
if (freq > 15000000) {
651
priv->mclk_rate = freq /= 2;
652
div = WM8955_MCLKDIV2;
654
priv->mclk_rate = freq;
658
snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
659
WM8955_MCLKDIV2, div);
666
dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
671
static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
673
struct snd_soc_codec *codec = dai->codec;
676
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
677
case SND_SOC_DAIFMT_CBS_CFS:
679
case SND_SOC_DAIFMT_CBM_CFM:
686
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
687
case SND_SOC_DAIFMT_DSP_B:
689
case SND_SOC_DAIFMT_DSP_A:
692
case SND_SOC_DAIFMT_I2S:
695
case SND_SOC_DAIFMT_RIGHT_J:
697
case SND_SOC_DAIFMT_LEFT_J:
704
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
705
case SND_SOC_DAIFMT_DSP_A:
706
case SND_SOC_DAIFMT_DSP_B:
707
/* frame inversion not valid for DSP modes */
708
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
709
case SND_SOC_DAIFMT_NB_NF:
711
case SND_SOC_DAIFMT_IB_NF:
712
aif |= WM8955_BCLKINV;
719
case SND_SOC_DAIFMT_I2S:
720
case SND_SOC_DAIFMT_RIGHT_J:
721
case SND_SOC_DAIFMT_LEFT_J:
722
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
723
case SND_SOC_DAIFMT_NB_NF:
725
case SND_SOC_DAIFMT_IB_IF:
726
aif |= WM8955_BCLKINV | WM8955_LRP;
728
case SND_SOC_DAIFMT_IB_NF:
729
aif |= WM8955_BCLKINV;
731
case SND_SOC_DAIFMT_NB_IF:
742
snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
743
WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
750
static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
752
struct snd_soc_codec *codec = codec_dai->codec;
760
snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
765
static int wm8955_set_bias_level(struct snd_soc_codec *codec,
766
enum snd_soc_bias_level level)
768
struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
769
u16 *reg_cache = codec->reg_cache;
773
case SND_SOC_BIAS_ON:
776
case SND_SOC_BIAS_PREPARE:
777
/* VMID resistance 2*50k */
778
snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
780
0x1 << WM8955_VMIDSEL_SHIFT);
782
/* Default bias current */
783
snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
785
0x2 << WM8955_VSEL_SHIFT);
788
case SND_SOC_BIAS_STANDBY:
789
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
790
ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
794
"Failed to enable supplies: %d\n",
799
/* Sync back cached values if they're
800
* different from the hardware default.
802
for (i = 0; i < codec->driver->reg_cache_size; i++) {
803
if (i == WM8955_RESET)
806
if (reg_cache[i] == wm8955_reg[i])
809
snd_soc_write(codec, i, reg_cache[i]);
812
/* Enable VREF and VMID */
813
snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
817
0x3 << WM8955_VREF_SHIFT);
822
/* High resistance VROI to maintain outputs */
823
snd_soc_update_bits(codec,
824
WM8955_ADDITIONAL_CONTROL_3,
825
WM8955_VROI, WM8955_VROI);
828
/* Maintain VMID with 2*250k */
829
snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
831
0x2 << WM8955_VMIDSEL_SHIFT);
833
/* Minimum bias current */
834
snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
835
WM8955_VSEL_MASK, 0);
838
case SND_SOC_BIAS_OFF:
839
/* Low resistance VROI to help discharge */
840
snd_soc_update_bits(codec,
841
WM8955_ADDITIONAL_CONTROL_3,
844
/* Turn off VMID and VREF */
845
snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
847
WM8955_VMIDSEL_MASK, 0);
849
regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
853
codec->dapm.bias_level = level;
857
#define WM8955_RATES SNDRV_PCM_RATE_8000_96000
859
#define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
860
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
862
static struct snd_soc_dai_ops wm8955_dai_ops = {
863
.set_sysclk = wm8955_set_sysclk,
864
.set_fmt = wm8955_set_fmt,
865
.hw_params = wm8955_hw_params,
866
.digital_mute = wm8955_digital_mute,
869
static struct snd_soc_dai_driver wm8955_dai = {
870
.name = "wm8955-hifi",
872
.stream_name = "Playback",
875
.rates = WM8955_RATES,
876
.formats = WM8955_FORMATS,
878
.ops = &wm8955_dai_ops,
882
static int wm8955_suspend(struct snd_soc_codec *codec, pm_message_t state)
884
wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
889
static int wm8955_resume(struct snd_soc_codec *codec)
891
wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
896
#define wm8955_suspend NULL
897
#define wm8955_resume NULL
900
static int wm8955_probe(struct snd_soc_codec *codec)
902
struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
903
struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
904
u16 *reg_cache = codec->reg_cache;
907
ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
909
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
913
for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
914
wm8955->supplies[i].supply = wm8955_supply_names[i];
916
ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
919
dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
923
ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
926
dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
930
ret = wm8955_reset(codec);
932
dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
936
/* Change some default settings - latch VU and enable ZC */
937
snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME,
938
WM8955_LDVU, WM8955_LDVU);
939
snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME,
940
WM8955_RDVU, WM8955_RDVU);
941
snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME,
942
WM8955_LO1VU | WM8955_LO1ZC,
943
WM8955_LO1VU | WM8955_LO1ZC);
944
snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME,
945
WM8955_RO1VU | WM8955_RO1ZC,
946
WM8955_RO1VU | WM8955_RO1ZC);
947
snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME,
948
WM8955_LO2VU | WM8955_LO2ZC,
949
WM8955_LO2VU | WM8955_LO2ZC);
950
snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME,
951
WM8955_RO2VU | WM8955_RO2ZC,
952
WM8955_RO2VU | WM8955_RO2ZC);
953
snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME,
954
WM8955_MOZC, WM8955_MOZC);
956
/* Also enable adaptive bass boost by default */
957
snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
959
/* Set platform data values */
961
if (pdata->out2_speaker)
962
reg_cache[WM8955_ADDITIONAL_CONTROL_2]
965
if (pdata->monoin_diff)
966
reg_cache[WM8955_MONO_OUT_MIX_1]
970
wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
972
/* Bias level configuration will have done an extra enable */
973
regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
975
wm8955_add_widgets(codec);
979
regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
981
regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
985
static int wm8955_remove(struct snd_soc_codec *codec)
987
struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
989
wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
990
regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
994
static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
995
.probe = wm8955_probe,
996
.remove = wm8955_remove,
997
.suspend = wm8955_suspend,
998
.resume = wm8955_resume,
999
.set_bias_level = wm8955_set_bias_level,
1000
.reg_cache_size = ARRAY_SIZE(wm8955_reg),
1001
.reg_word_size = sizeof(u16),
1002
.reg_cache_default = wm8955_reg,
1005
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1006
static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
1007
const struct i2c_device_id *id)
1009
struct wm8955_priv *wm8955;
1012
wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1016
i2c_set_clientdata(i2c, wm8955);
1017
wm8955->control_type = SND_SOC_I2C;
1019
ret = snd_soc_register_codec(&i2c->dev,
1020
&soc_codec_dev_wm8955, &wm8955_dai, 1);
1026
static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1028
snd_soc_unregister_codec(&client->dev);
1029
kfree(i2c_get_clientdata(client));
1033
static const struct i2c_device_id wm8955_i2c_id[] = {
1037
MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1039
static struct i2c_driver wm8955_i2c_driver = {
1041
.name = "wm8955-codec",
1042
.owner = THIS_MODULE,
1044
.probe = wm8955_i2c_probe,
1045
.remove = __devexit_p(wm8955_i2c_remove),
1046
.id_table = wm8955_i2c_id,
1050
static int __init wm8955_modinit(void)
1053
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1054
ret = i2c_add_driver(&wm8955_i2c_driver);
1056
printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1062
module_init(wm8955_modinit);
1064
static void __exit wm8955_exit(void)
1066
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1067
i2c_del_driver(&wm8955_i2c_driver);
1070
module_exit(wm8955_exit);
1072
MODULE_DESCRIPTION("ASoC WM8955 driver");
1073
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1074
MODULE_LICENSE("GPL");