2
* Blackfin On-Chip MAC Driver
4
* Copyright 2004-2010 Analog Devices Inc.
6
* Enter bugs at http://blackfin.uclinux.org/
8
* Licensed under the GPL-2 or later.
11
#define DRV_VERSION "1.1"
12
#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
14
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
#include <linux/init.h>
17
#include <linux/module.h>
18
#include <linux/kernel.h>
19
#include <linux/sched.h>
20
#include <linux/slab.h>
21
#include <linux/delay.h>
22
#include <linux/timer.h>
23
#include <linux/errno.h>
24
#include <linux/irq.h>
26
#include <linux/ioport.h>
27
#include <linux/crc32.h>
28
#include <linux/device.h>
29
#include <linux/spinlock.h>
30
#include <linux/mii.h>
31
#include <linux/netdevice.h>
32
#include <linux/etherdevice.h>
33
#include <linux/ethtool.h>
34
#include <linux/skbuff.h>
35
#include <linux/platform_device.h>
38
#include <linux/dma-mapping.h>
40
#include <asm/div64.h>
42
#include <asm/blackfin.h>
43
#include <asm/cacheflush.h>
44
#include <asm/portmux.h>
49
MODULE_AUTHOR("Bryan Wu, Luke Yang");
50
MODULE_LICENSE("GPL");
51
MODULE_DESCRIPTION(DRV_DESC);
52
MODULE_ALIAS("platform:bfin_mac");
54
#if defined(CONFIG_BFIN_MAC_USE_L1)
55
# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56
# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
58
# define bfin_mac_alloc(dma_handle, size, num) \
59
dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60
# define bfin_mac_free(dma_handle, ptr, num) \
61
dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
64
#define PKT_BUF_SZ 1580
66
#define MAX_TIMEOUT_CNT 500
68
/* pointers to maintain transmit list */
69
static struct net_dma_desc_tx *tx_list_head;
70
static struct net_dma_desc_tx *tx_list_tail;
71
static struct net_dma_desc_rx *rx_list_head;
72
static struct net_dma_desc_rx *rx_list_tail;
73
static struct net_dma_desc_rx *current_rx_ptr;
74
static struct net_dma_desc_tx *current_tx_ptr;
75
static struct net_dma_desc_tx *tx_desc;
76
static struct net_dma_desc_rx *rx_desc;
78
static void desc_list_free(void)
80
struct net_dma_desc_rx *r;
81
struct net_dma_desc_tx *t;
83
#if !defined(CONFIG_BFIN_MAC_USE_L1)
84
dma_addr_t dma_handle = 0;
89
for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
92
dev_kfree_skb(t->skb);
98
bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
103
for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
106
dev_kfree_skb(r->skb);
112
bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
116
static int desc_list_init(void)
119
struct sk_buff *new_skb;
120
#if !defined(CONFIG_BFIN_MAC_USE_L1)
122
* This dma_handle is useless in Blackfin dma_alloc_coherent().
123
* The real dma handler is the return value of dma_alloc_coherent().
125
dma_addr_t dma_handle;
128
tx_desc = bfin_mac_alloc(&dma_handle,
129
sizeof(struct net_dma_desc_tx),
130
CONFIG_BFIN_TX_DESC_NUM);
134
rx_desc = bfin_mac_alloc(&dma_handle,
135
sizeof(struct net_dma_desc_rx),
136
CONFIG_BFIN_RX_DESC_NUM);
141
tx_list_head = tx_list_tail = tx_desc;
143
for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144
struct net_dma_desc_tx *t = tx_desc + i;
145
struct dma_descriptor *a = &(t->desc_a);
146
struct dma_descriptor *b = &(t->desc_b);
150
* read from memory WNR = 0
151
* wordsize is 32 bits
152
* 6 half words is desc size
155
a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156
a->start_addr = (unsigned long)t->packet;
158
a->next_dma_desc = b;
162
* write to memory WNR = 1
163
* wordsize is 32 bits
165
* 6 half words is desc size
168
b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169
b->start_addr = (unsigned long)(&(t->status));
173
tx_list_tail->desc_b.next_dma_desc = a;
174
tx_list_tail->next = t;
177
tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178
tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179
current_tx_ptr = tx_list_head;
182
rx_list_head = rx_list_tail = rx_desc;
184
for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185
struct net_dma_desc_rx *r = rx_desc + i;
186
struct dma_descriptor *a = &(r->desc_a);
187
struct dma_descriptor *b = &(r->desc_b);
189
/* allocate a new skb for next time receive */
190
new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
192
pr_notice("init: low on mem - packet dropped\n");
195
skb_reserve(new_skb, NET_IP_ALIGN);
196
/* Invidate the data cache of skb->data range when it is write back
197
* cache. It will prevent overwritting the new data from DMA
199
blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
200
(unsigned long)new_skb->end);
205
* write to memory WNR = 1
206
* wordsize is 32 bits
208
* 6 half words is desc size
211
a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
212
/* since RXDWA is enabled */
213
a->start_addr = (unsigned long)new_skb->data - 2;
215
a->next_dma_desc = b;
219
* write to memory WNR = 1
220
* wordsize is 32 bits
222
* 6 half words is desc size
225
b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
226
NDSIZE_6 | DMAFLOW_LARGE;
227
b->start_addr = (unsigned long)(&(r->status));
230
rx_list_tail->desc_b.next_dma_desc = a;
231
rx_list_tail->next = r;
234
rx_list_tail->next = rx_list_head; /* rx_list is a circle */
235
rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
236
current_rx_ptr = rx_list_head;
242
pr_err("kmalloc failed\n");
247
/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
252
/* Wait until the previous MDC/MDIO transaction has completed */
253
static int bfin_mdio_poll(void)
255
int timeout_cnt = MAX_TIMEOUT_CNT;
257
/* poll the STABUSY bit */
258
while ((bfin_read_EMAC_STAADD()) & STABUSY) {
260
if (timeout_cnt-- < 0) {
261
pr_err("wait MDC/MDIO transaction to complete timeout\n");
269
/* Read an off-chip register in a PHY through the MDC/MDIO port */
270
static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
274
ret = bfin_mdio_poll();
279
bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
280
SET_REGAD((u16) regnum) |
283
ret = bfin_mdio_poll();
287
return (int) bfin_read_EMAC_STADAT();
290
/* Write an off-chip register in a PHY through the MDC/MDIO port */
291
static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
296
ret = bfin_mdio_poll();
300
bfin_write_EMAC_STADAT((u32) value);
303
bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
304
SET_REGAD((u16) regnum) |
308
return bfin_mdio_poll();
311
static int bfin_mdiobus_reset(struct mii_bus *bus)
316
static void bfin_mac_adjust_link(struct net_device *dev)
318
struct bfin_mac_local *lp = netdev_priv(dev);
319
struct phy_device *phydev = lp->phydev;
323
spin_lock_irqsave(&lp->lock, flags);
325
/* Now we make sure that we can be in full duplex mode.
326
* If not, we operate in half-duplex mode. */
327
if (phydev->duplex != lp->old_duplex) {
328
u32 opmode = bfin_read_EMAC_OPMODE();
336
bfin_write_EMAC_OPMODE(opmode);
337
lp->old_duplex = phydev->duplex;
340
if (phydev->speed != lp->old_speed) {
341
if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
342
u32 opmode = bfin_read_EMAC_OPMODE();
343
switch (phydev->speed) {
352
"Ack! Speed (%d) is not 10/100!\n",
356
bfin_write_EMAC_OPMODE(opmode);
360
lp->old_speed = phydev->speed;
367
} else if (lp->old_link) {
375
u32 opmode = bfin_read_EMAC_OPMODE();
376
phy_print_status(phydev);
377
pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
380
spin_unlock_irqrestore(&lp->lock, flags);
384
#define MDC_CLK 2500000
386
static int mii_probe(struct net_device *dev, int phy_mode)
388
struct bfin_mac_local *lp = netdev_priv(dev);
389
struct phy_device *phydev = NULL;
390
unsigned short sysctl;
394
/* Enable PHY output early */
395
if (!(bfin_read_VR_CTL() & CLKBUFOE))
396
bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
399
mdc_div = ((sclk / MDC_CLK) / 2) - 1;
401
sysctl = bfin_read_EMAC_SYSCTL();
402
sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
403
bfin_write_EMAC_SYSCTL(sysctl);
405
/* search for connected PHY device */
406
for (i = 0; i < PHY_MAX_ADDR; ++i) {
407
struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
410
continue; /* no PHY here... */
413
break; /* found it */
416
/* now we are supposed to have a proper phydev, to attach to... */
418
netdev_err(dev, "no phy device found\n");
422
if (phy_mode != PHY_INTERFACE_MODE_RMII &&
423
phy_mode != PHY_INTERFACE_MODE_MII) {
424
netdev_err(dev, "invalid phy interface mode\n");
428
phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
431
if (IS_ERR(phydev)) {
432
netdev_err(dev, "could not attach PHY\n");
433
return PTR_ERR(phydev);
436
/* mask with MAC supported features */
437
phydev->supported &= (SUPPORTED_10baseT_Half
438
| SUPPORTED_10baseT_Full
439
| SUPPORTED_100baseT_Half
440
| SUPPORTED_100baseT_Full
442
| SUPPORTED_Pause | SUPPORTED_Asym_Pause
446
phydev->advertising = phydev->supported;
453
pr_info("attached PHY driver [%s] "
454
"(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
455
phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
456
MDC_CLK, mdc_div, sclk/1000000);
466
* interrupt routine for magic packet wakeup
468
static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
474
bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
476
struct bfin_mac_local *lp = netdev_priv(dev);
479
return phy_ethtool_gset(lp->phydev, cmd);
485
bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
487
struct bfin_mac_local *lp = netdev_priv(dev);
489
if (!capable(CAP_NET_ADMIN))
493
return phy_ethtool_sset(lp->phydev, cmd);
498
static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
499
struct ethtool_drvinfo *info)
501
strcpy(info->driver, KBUILD_MODNAME);
502
strcpy(info->version, DRV_VERSION);
503
strcpy(info->fw_version, "N/A");
504
strcpy(info->bus_info, dev_name(&dev->dev));
507
static void bfin_mac_ethtool_getwol(struct net_device *dev,
508
struct ethtool_wolinfo *wolinfo)
510
struct bfin_mac_local *lp = netdev_priv(dev);
512
wolinfo->supported = WAKE_MAGIC;
513
wolinfo->wolopts = lp->wol;
516
static int bfin_mac_ethtool_setwol(struct net_device *dev,
517
struct ethtool_wolinfo *wolinfo)
519
struct bfin_mac_local *lp = netdev_priv(dev);
522
if (wolinfo->wolopts & (WAKE_MAGICSECURE |
529
lp->wol = wolinfo->wolopts;
531
if (lp->wol && !lp->irq_wake_requested) {
532
/* register wake irq handler */
533
rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
534
IRQF_DISABLED, "EMAC_WAKE", dev);
537
lp->irq_wake_requested = true;
540
if (!lp->wol && lp->irq_wake_requested) {
541
free_irq(IRQ_MAC_WAKEDET, dev);
542
lp->irq_wake_requested = false;
545
/* Make sure the PHY driver doesn't suspend */
546
device_init_wakeup(&dev->dev, lp->wol);
551
static const struct ethtool_ops bfin_mac_ethtool_ops = {
552
.get_settings = bfin_mac_ethtool_getsettings,
553
.set_settings = bfin_mac_ethtool_setsettings,
554
.get_link = ethtool_op_get_link,
555
.get_drvinfo = bfin_mac_ethtool_getdrvinfo,
556
.get_wol = bfin_mac_ethtool_getwol,
557
.set_wol = bfin_mac_ethtool_setwol,
560
/**************************************************************************/
561
static void setup_system_regs(struct net_device *dev)
563
struct bfin_mac_local *lp = netdev_priv(dev);
565
unsigned short sysctl;
568
* Odd word alignment for Receive Frame DMA word
569
* Configure checksum support and rcve frame word alignment
571
sysctl = bfin_read_EMAC_SYSCTL();
573
* check if interrupt is requested for any PHY,
574
* enable PHY interrupt only if needed
576
for (i = 0; i < PHY_MAX_ADDR; ++i)
577
if (lp->mii_bus->irq[i] != PHY_POLL)
579
if (i < PHY_MAX_ADDR)
582
#if defined(BFIN_MAC_CSUM_OFFLOAD)
587
bfin_write_EMAC_SYSCTL(sysctl);
589
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
591
/* Set vlan regs to let 1522 bytes long packets pass through */
592
bfin_write_EMAC_VLAN1(lp->vlan1_mask);
593
bfin_write_EMAC_VLAN2(lp->vlan2_mask);
595
/* Initialize the TX DMA channel registers */
596
bfin_write_DMA2_X_COUNT(0);
597
bfin_write_DMA2_X_MODIFY(4);
598
bfin_write_DMA2_Y_COUNT(0);
599
bfin_write_DMA2_Y_MODIFY(0);
601
/* Initialize the RX DMA channel registers */
602
bfin_write_DMA1_X_COUNT(0);
603
bfin_write_DMA1_X_MODIFY(4);
604
bfin_write_DMA1_Y_COUNT(0);
605
bfin_write_DMA1_Y_MODIFY(0);
608
static void setup_mac_addr(u8 *mac_addr)
610
u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
611
u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
613
/* this depends on a little-endian machine */
614
bfin_write_EMAC_ADDRLO(addr_low);
615
bfin_write_EMAC_ADDRHI(addr_hi);
618
static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
620
struct sockaddr *addr = p;
621
if (netif_running(dev))
623
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
624
setup_mac_addr(dev->dev_addr);
628
#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
629
#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
631
static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
632
struct ifreq *ifr, int cmd)
634
struct hwtstamp_config config;
635
struct bfin_mac_local *lp = netdev_priv(netdev);
637
u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
639
if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
642
pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
643
__func__, config.flags, config.tx_type, config.rx_filter);
645
/* reserved for future extensions */
649
if ((config.tx_type != HWTSTAMP_TX_OFF) &&
650
(config.tx_type != HWTSTAMP_TX_ON))
653
ptpctl = bfin_read_EMAC_PTP_CTL();
655
switch (config.rx_filter) {
656
case HWTSTAMP_FILTER_NONE:
658
* Dont allow any timestamping
661
bfin_write_EMAC_PTP_FV3(ptpfv3);
663
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
664
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
665
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
667
* Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
668
* to enable all the field matches.
671
bfin_write_EMAC_PTP_CTL(ptpctl);
673
* Keep the default values of the EMAC_PTP_FOFF register.
675
ptpfoff = 0x4A24170C;
676
bfin_write_EMAC_PTP_FOFF(ptpfoff);
678
* Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
682
bfin_write_EMAC_PTP_FV1(ptpfv1);
684
bfin_write_EMAC_PTP_FV2(ptpfv2);
686
* The default value (0xFFFC) allows the timestamping of both
687
* received Sync messages and Delay_Req messages.
690
bfin_write_EMAC_PTP_FV3(ptpfv3);
692
config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
694
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
695
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
696
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
697
/* Clear all five comparison mask bits (bits[12:8]) in the
698
* EMAC_PTP_CTL register to enable all the field matches.
701
bfin_write_EMAC_PTP_CTL(ptpctl);
703
* Keep the default values of the EMAC_PTP_FOFF register, except set
704
* the PTPCOF field to 0x2A.
706
ptpfoff = 0x2A24170C;
707
bfin_write_EMAC_PTP_FOFF(ptpfoff);
709
* Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
713
bfin_write_EMAC_PTP_FV1(ptpfv1);
715
bfin_write_EMAC_PTP_FV2(ptpfv2);
717
* To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
718
* the value to 0xFFF0.
721
bfin_write_EMAC_PTP_FV3(ptpfv3);
723
config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
725
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
726
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
727
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
729
* Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
730
* EFTM and PTPCM field comparison.
733
bfin_write_EMAC_PTP_CTL(ptpctl);
735
* Keep the default values of all the fields of the EMAC_PTP_FOFF
736
* register, except set the PTPCOF field to 0x0E.
738
ptpfoff = 0x0E24170C;
739
bfin_write_EMAC_PTP_FOFF(ptpfoff);
741
* Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
742
* corresponds to PTP messages on the MAC layer.
745
bfin_write_EMAC_PTP_FV1(ptpfv1);
747
bfin_write_EMAC_PTP_FV2(ptpfv2);
749
* To allow the timestamping of Pdelay_Req and Pdelay_Resp
750
* messages, set the value to 0xFFF0.
753
bfin_write_EMAC_PTP_FV3(ptpfv3);
755
config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
761
if (config.tx_type == HWTSTAMP_TX_OFF &&
762
bfin_mac_hwtstamp_is_none(config.rx_filter)) {
764
bfin_write_EMAC_PTP_CTL(ptpctl);
769
bfin_write_EMAC_PTP_CTL(ptpctl);
772
* clear any existing timestamp
774
bfin_read_EMAC_PTP_RXSNAPLO();
775
bfin_read_EMAC_PTP_RXSNAPHI();
777
bfin_read_EMAC_PTP_TXSNAPLO();
778
bfin_read_EMAC_PTP_TXSNAPHI();
781
* Set registers so that rollover occurs soon to test this.
783
bfin_write_EMAC_PTP_TIMELO(0x00000000);
784
bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
788
lp->compare.last_update = 0;
789
timecounter_init(&lp->clock,
791
ktime_to_ns(ktime_get_real()));
792
timecompare_update(&lp->compare, 0);
795
lp->stamp_cfg = config;
796
return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
800
static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
802
ktime_t sys = ktime_get_real();
804
pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
805
__func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
806
sys.tv.nsec, cmp->offset, cmp->skew);
809
static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
811
struct bfin_mac_local *lp = netdev_priv(netdev);
813
if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
814
int timeout_cnt = MAX_TIMEOUT_CNT;
816
/* When doing time stamping, keep the connection to the socket
819
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
822
* The timestamping is done at the EMAC module's MII/RMII interface
823
* when the module sees the Start of Frame of an event message packet. This
824
* interface is the closest possible place to the physical Ethernet transmission
825
* medium, providing the best timing accuracy.
827
while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
829
if (timeout_cnt == 0)
830
netdev_err(netdev, "timestamp the TX packet failed\n");
832
struct skb_shared_hwtstamps shhwtstamps;
836
regval = bfin_read_EMAC_PTP_TXSNAPLO();
837
regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
838
memset(&shhwtstamps, 0, sizeof(shhwtstamps));
839
ns = timecounter_cyc2time(&lp->clock,
841
timecompare_update(&lp->compare, ns);
842
shhwtstamps.hwtstamp = ns_to_ktime(ns);
843
shhwtstamps.syststamp =
844
timecompare_transform(&lp->compare, ns);
845
skb_tstamp_tx(skb, &shhwtstamps);
847
bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
852
static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
854
struct bfin_mac_local *lp = netdev_priv(netdev);
857
struct skb_shared_hwtstamps *shhwtstamps;
859
if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
862
valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
866
shhwtstamps = skb_hwtstamps(skb);
868
regval = bfin_read_EMAC_PTP_RXSNAPLO();
869
regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
870
ns = timecounter_cyc2time(&lp->clock, regval);
871
timecompare_update(&lp->compare, ns);
872
memset(shhwtstamps, 0, sizeof(*shhwtstamps));
873
shhwtstamps->hwtstamp = ns_to_ktime(ns);
874
shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
876
bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
880
* bfin_read_clock - read raw cycle counter (to be used by time counter)
882
static cycle_t bfin_read_clock(const struct cyclecounter *tc)
886
stamp = bfin_read_EMAC_PTP_TIMELO();
887
stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
892
#define PTP_CLK 25000000
894
static void bfin_mac_hwtstamp_init(struct net_device *netdev)
896
struct bfin_mac_local *lp = netdev_priv(netdev);
899
/* Initialize hardware timer */
900
append = PTP_CLK * (1ULL << 32);
901
do_div(append, get_sclk());
902
bfin_write_EMAC_PTP_ADDEND((u32)append);
904
memset(&lp->cycles, 0, sizeof(lp->cycles));
905
lp->cycles.read = bfin_read_clock;
906
lp->cycles.mask = CLOCKSOURCE_MASK(64);
907
lp->cycles.mult = 1000000000 / PTP_CLK;
908
lp->cycles.shift = 0;
910
/* Synchronize our NIC clock against system wall clock */
911
memset(&lp->compare, 0, sizeof(lp->compare));
912
lp->compare.source = &lp->clock;
913
lp->compare.target = ktime_get_real;
914
lp->compare.num_samples = 10;
916
/* Initialize hwstamp config */
917
lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
918
lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
922
# define bfin_mac_hwtstamp_is_none(cfg) 0
923
# define bfin_mac_hwtstamp_init(dev)
924
# define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
925
# define bfin_rx_hwtstamp(dev, skb)
926
# define bfin_tx_hwtstamp(dev, skb)
929
static inline void _tx_reclaim_skb(void)
932
tx_list_head->desc_a.config &= ~DMAEN;
933
tx_list_head->status.status_word = 0;
934
if (tx_list_head->skb) {
935
dev_kfree_skb(tx_list_head->skb);
936
tx_list_head->skb = NULL;
938
tx_list_head = tx_list_head->next;
940
} while (tx_list_head->status.status_word != 0);
943
static void tx_reclaim_skb(struct bfin_mac_local *lp)
945
int timeout_cnt = MAX_TIMEOUT_CNT;
947
if (tx_list_head->status.status_word != 0)
950
if (current_tx_ptr->next == tx_list_head) {
951
while (tx_list_head->status.status_word == 0) {
952
/* slow down polling to avoid too many queue stop. */
954
/* reclaim skb if DMA is not running. */
955
if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
957
if (timeout_cnt-- < 0)
961
if (timeout_cnt >= 0)
964
netif_stop_queue(lp->ndev);
967
if (current_tx_ptr->next != tx_list_head &&
968
netif_queue_stopped(lp->ndev))
969
netif_wake_queue(lp->ndev);
971
if (tx_list_head != current_tx_ptr) {
972
/* shorten the timer interval if tx queue is stopped */
973
if (netif_queue_stopped(lp->ndev))
974
lp->tx_reclaim_timer.expires =
975
jiffies + (TX_RECLAIM_JIFFIES >> 4);
977
lp->tx_reclaim_timer.expires =
978
jiffies + TX_RECLAIM_JIFFIES;
980
mod_timer(&lp->tx_reclaim_timer,
981
lp->tx_reclaim_timer.expires);
987
static void tx_reclaim_skb_timeout(unsigned long lp)
989
tx_reclaim_skb((struct bfin_mac_local *)lp);
992
static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
993
struct net_device *dev)
995
struct bfin_mac_local *lp = netdev_priv(dev);
997
u32 data_align = (unsigned long)(skb->data) & 0x3;
999
current_tx_ptr->skb = skb;
1001
if (data_align == 0x2) {
1002
/* move skb->data to current_tx_ptr payload */
1003
data = (u16 *)(skb->data) - 1;
1004
*data = (u16)(skb->len);
1006
* When transmitting an Ethernet packet, the PTP_TSYNC module requires
1007
* a DMA_Length_Word field associated with the packet. The lower 12 bits
1008
* of this field are the length of the packet payload in bytes and the higher
1009
* 4 bits are the timestamping enable field.
1011
if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1014
current_tx_ptr->desc_a.start_addr = (u32)data;
1015
/* this is important! */
1016
blackfin_dcache_flush_range((u32)data,
1017
(u32)((u8 *)data + skb->len + 4));
1019
*((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
1020
/* enable timestamping for the sent packet */
1021
if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1022
*((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1023
memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1025
current_tx_ptr->desc_a.start_addr =
1026
(u32)current_tx_ptr->packet;
1027
blackfin_dcache_flush_range(
1028
(u32)current_tx_ptr->packet,
1029
(u32)(current_tx_ptr->packet + skb->len + 2));
1032
/* make sure the internal data buffers in the core are drained
1033
* so that the DMA descriptors are completely written when the
1034
* DMA engine goes to fetch them below
1038
/* always clear status buffer before start tx dma */
1039
current_tx_ptr->status.status_word = 0;
1041
/* enable this packet's dma */
1042
current_tx_ptr->desc_a.config |= DMAEN;
1044
/* tx dma is running, just return */
1045
if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1048
/* tx dma is not running */
1049
bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1050
/* dma enabled, read from memory, size is 6 */
1051
bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1052
/* Turn on the EMAC tx */
1053
bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1056
bfin_tx_hwtstamp(dev, skb);
1058
current_tx_ptr = current_tx_ptr->next;
1059
dev->stats.tx_packets++;
1060
dev->stats.tx_bytes += (skb->len);
1064
return NETDEV_TX_OK;
1067
#define IP_HEADER_OFF 0
1068
#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1069
RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1071
static void bfin_mac_rx(struct net_device *dev)
1073
struct sk_buff *skb, *new_skb;
1075
struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
1076
#if defined(BFIN_MAC_CSUM_OFFLOAD)
1078
unsigned char fcs[ETH_FCS_LEN + 1];
1081
/* check if frame status word reports an error condition
1082
* we which case we simply drop the packet
1084
if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1085
netdev_notice(dev, "rx: receive error - packet dropped\n");
1086
dev->stats.rx_dropped++;
1090
/* allocate a new skb for next time receive */
1091
skb = current_rx_ptr->skb;
1093
new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
1095
netdev_notice(dev, "rx: low on mem - packet dropped\n");
1096
dev->stats.rx_dropped++;
1099
/* reserve 2 bytes for RXDWA padding */
1100
skb_reserve(new_skb, NET_IP_ALIGN);
1101
/* Invidate the data cache of skb->data range when it is write back
1102
* cache. It will prevent overwritting the new data from DMA
1104
blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1105
(unsigned long)new_skb->end);
1107
current_rx_ptr->skb = new_skb;
1108
current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1110
len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
1111
/* Deduce Ethernet FCS length from Ethernet payload length */
1115
skb->protocol = eth_type_trans(skb, dev);
1117
bfin_rx_hwtstamp(dev, skb);
1119
#if defined(BFIN_MAC_CSUM_OFFLOAD)
1120
/* Checksum offloading only works for IPv4 packets with the standard IP header
1121
* length of 20 bytes, because the blackfin MAC checksum calculation is
1122
* based on that assumption. We must NOT use the calculated checksum if our
1123
* IP version or header break that assumption.
1125
if (skb->data[IP_HEADER_OFF] == 0x45) {
1126
skb->csum = current_rx_ptr->status.ip_payload_csum;
1128
* Deduce Ethernet FCS from hardware generated IP payload checksum.
1129
* IP checksum is based on 16-bit one's complement algorithm.
1130
* To deduce a value from checksum is equal to add its inversion.
1131
* If the IP payload len is odd, the inversed FCS should also
1132
* begin from odd address and leave first byte zero.
1136
for (i = 0; i < ETH_FCS_LEN; i++)
1137
fcs[i + 1] = ~skb->data[skb->len + i];
1138
skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1140
for (i = 0; i < ETH_FCS_LEN; i++)
1141
fcs[i] = ~skb->data[skb->len + i];
1142
skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1144
skb->ip_summed = CHECKSUM_COMPLETE;
1149
dev->stats.rx_packets++;
1150
dev->stats.rx_bytes += len;
1152
current_rx_ptr->status.status_word = 0x00000000;
1153
current_rx_ptr = current_rx_ptr->next;
1156
/* interrupt routine to handle rx and error signal */
1157
static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1159
struct net_device *dev = dev_id;
1163
if (current_rx_ptr->status.status_word == 0) {
1164
/* no more new packet received */
1166
if (current_rx_ptr->next->status.status_word != 0) {
1167
current_rx_ptr = current_rx_ptr->next;
1171
bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1172
DMA_DONE | DMA_ERR);
1179
goto get_one_packet;
1182
#ifdef CONFIG_NET_POLL_CONTROLLER
1183
static void bfin_mac_poll(struct net_device *dev)
1185
struct bfin_mac_local *lp = netdev_priv(dev);
1187
disable_irq(IRQ_MAC_RX);
1188
bfin_mac_interrupt(IRQ_MAC_RX, dev);
1190
enable_irq(IRQ_MAC_RX);
1192
#endif /* CONFIG_NET_POLL_CONTROLLER */
1194
static void bfin_mac_disable(void)
1196
unsigned int opmode;
1198
opmode = bfin_read_EMAC_OPMODE();
1201
/* Turn off the EMAC */
1202
bfin_write_EMAC_OPMODE(opmode);
1206
* Enable Interrupts, Receive, and Transmit
1208
static int bfin_mac_enable(struct phy_device *phydev)
1213
pr_debug("%s\n", __func__);
1216
bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1217
bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1220
ret = bfin_mdio_poll();
1224
/* We enable only RX here */
1225
/* ASTP : Enable Automatic Pad Stripping
1226
PR : Promiscuous Mode for test
1227
PSF : Receive frames with total length less than 64 bytes.
1228
FDMODE : Full Duplex Mode
1229
LB : Internal Loopback for test
1230
RE : Receiver Enable */
1231
opmode = bfin_read_EMAC_OPMODE();
1232
if (opmode & FDMODE)
1235
opmode |= DRO | DC | PSF;
1238
if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1239
opmode |= RMII; /* For Now only 100MBit are supported */
1240
#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1241
if (__SILICON_REVISION__ < 3) {
1243
* This isn't publicly documented (fun times!), but in
1244
* silicon <=0.2, the RX and TX pins are clocked together.
1245
* So in order to recv, we must enable the transmit side
1246
* as well. This will cause a spurious TX interrupt too,
1247
* but we can easily consume that.
1254
/* Turn on the EMAC rx */
1255
bfin_write_EMAC_OPMODE(opmode);
1260
/* Our watchdog timed out. Called by the networking layer */
1261
static void bfin_mac_timeout(struct net_device *dev)
1263
struct bfin_mac_local *lp = netdev_priv(dev);
1265
pr_debug("%s: %s\n", dev->name, __func__);
1269
del_timer(&lp->tx_reclaim_timer);
1271
/* reset tx queue and free skb */
1272
while (tx_list_head != current_tx_ptr) {
1273
tx_list_head->desc_a.config &= ~DMAEN;
1274
tx_list_head->status.status_word = 0;
1275
if (tx_list_head->skb) {
1276
dev_kfree_skb(tx_list_head->skb);
1277
tx_list_head->skb = NULL;
1279
tx_list_head = tx_list_head->next;
1282
if (netif_queue_stopped(lp->ndev))
1283
netif_wake_queue(lp->ndev);
1285
bfin_mac_enable(lp->phydev);
1287
/* We can accept TX packets again */
1288
dev->trans_start = jiffies; /* prevent tx timeout */
1289
netif_wake_queue(dev);
1292
static void bfin_mac_multicast_hash(struct net_device *dev)
1294
u32 emac_hashhi, emac_hashlo;
1295
struct netdev_hw_addr *ha;
1298
emac_hashhi = emac_hashlo = 0;
1300
netdev_for_each_mc_addr(ha, dev) {
1301
crc = ether_crc(ETH_ALEN, ha->addr);
1305
emac_hashhi |= 1 << (crc & 0x1f);
1307
emac_hashlo |= 1 << (crc & 0x1f);
1310
bfin_write_EMAC_HASHHI(emac_hashhi);
1311
bfin_write_EMAC_HASHLO(emac_hashlo);
1315
* This routine will, depending on the values passed to it,
1316
* either make it accept multicast packets, go into
1317
* promiscuous mode (for TCPDUMP and cousins) or accept
1318
* a select set of multicast packets
1320
static void bfin_mac_set_multicast_list(struct net_device *dev)
1324
if (dev->flags & IFF_PROMISC) {
1325
netdev_info(dev, "set promisc mode\n");
1326
sysctl = bfin_read_EMAC_OPMODE();
1328
bfin_write_EMAC_OPMODE(sysctl);
1329
} else if (dev->flags & IFF_ALLMULTI) {
1330
/* accept all multicast */
1331
sysctl = bfin_read_EMAC_OPMODE();
1333
bfin_write_EMAC_OPMODE(sysctl);
1334
} else if (!netdev_mc_empty(dev)) {
1335
/* set up multicast hash table */
1336
sysctl = bfin_read_EMAC_OPMODE();
1338
bfin_write_EMAC_OPMODE(sysctl);
1339
bfin_mac_multicast_hash(dev);
1341
/* clear promisc or multicast mode */
1342
sysctl = bfin_read_EMAC_OPMODE();
1343
sysctl &= ~(RAF | PAM);
1344
bfin_write_EMAC_OPMODE(sysctl);
1348
static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1350
struct bfin_mac_local *lp = netdev_priv(netdev);
1352
if (!netif_running(netdev))
1357
return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1360
return phy_mii_ioctl(lp->phydev, ifr, cmd);
1367
* this puts the device in an inactive state
1369
static void bfin_mac_shutdown(struct net_device *dev)
1371
/* Turn off the EMAC */
1372
bfin_write_EMAC_OPMODE(0x00000000);
1373
/* Turn off the EMAC RX DMA */
1374
bfin_write_DMA1_CONFIG(0x0000);
1375
bfin_write_DMA2_CONFIG(0x0000);
1379
* Open and Initialize the interface
1381
* Set up everything, reset the card, etc..
1383
static int bfin_mac_open(struct net_device *dev)
1385
struct bfin_mac_local *lp = netdev_priv(dev);
1387
pr_debug("%s: %s\n", dev->name, __func__);
1390
* Check that the address is valid. If its not, refuse
1391
* to bring the device up. The user must specify an
1392
* address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1394
if (!is_valid_ether_addr(dev->dev_addr)) {
1395
netdev_warn(dev, "no valid ethernet hw addr\n");
1399
/* initial rx and tx list */
1400
ret = desc_list_init();
1404
phy_start(lp->phydev);
1405
phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
1406
setup_system_regs(dev);
1407
setup_mac_addr(dev->dev_addr);
1410
ret = bfin_mac_enable(lp->phydev);
1413
pr_debug("hardware init finished\n");
1415
netif_start_queue(dev);
1416
netif_carrier_on(dev);
1422
* this makes the board clean up everything that it can
1423
* and not talk to the outside world. Caused by
1424
* an 'ifconfig ethX down'
1426
static int bfin_mac_close(struct net_device *dev)
1428
struct bfin_mac_local *lp = netdev_priv(dev);
1429
pr_debug("%s: %s\n", dev->name, __func__);
1431
netif_stop_queue(dev);
1432
netif_carrier_off(dev);
1434
phy_stop(lp->phydev);
1435
phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1437
/* clear everything */
1438
bfin_mac_shutdown(dev);
1440
/* free the rx/tx buffers */
1446
static const struct net_device_ops bfin_mac_netdev_ops = {
1447
.ndo_open = bfin_mac_open,
1448
.ndo_stop = bfin_mac_close,
1449
.ndo_start_xmit = bfin_mac_hard_start_xmit,
1450
.ndo_set_mac_address = bfin_mac_set_mac_address,
1451
.ndo_tx_timeout = bfin_mac_timeout,
1452
.ndo_set_rx_mode = bfin_mac_set_multicast_list,
1453
.ndo_do_ioctl = bfin_mac_ioctl,
1454
.ndo_validate_addr = eth_validate_addr,
1455
.ndo_change_mtu = eth_change_mtu,
1456
#ifdef CONFIG_NET_POLL_CONTROLLER
1457
.ndo_poll_controller = bfin_mac_poll,
1461
static int __devinit bfin_mac_probe(struct platform_device *pdev)
1463
struct net_device *ndev;
1464
struct bfin_mac_local *lp;
1465
struct platform_device *pd;
1466
struct bfin_mii_bus_platform_data *mii_bus_data;
1469
ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1471
dev_err(&pdev->dev, "Cannot allocate net device!\n");
1475
SET_NETDEV_DEV(ndev, &pdev->dev);
1476
platform_set_drvdata(pdev, ndev);
1477
lp = netdev_priv(ndev);
1480
/* Grab the MAC address in the MAC */
1481
*(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1482
*(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1485
/*todo: how to proble? which is revision_register */
1486
bfin_write_EMAC_ADDRLO(0x12345678);
1487
if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1488
dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1490
goto out_err_probe_mac;
1495
* Is it valid? (Did bootloader initialize it?)
1496
* Grab the MAC from the board somehow
1497
* this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1499
if (!is_valid_ether_addr(ndev->dev_addr))
1500
bfin_get_ether_addr(ndev->dev_addr);
1502
/* If still not valid, get a random one */
1503
if (!is_valid_ether_addr(ndev->dev_addr))
1504
random_ether_addr(ndev->dev_addr);
1506
setup_mac_addr(ndev->dev_addr);
1508
if (!pdev->dev.platform_data) {
1509
dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1511
goto out_err_probe_mac;
1513
pd = pdev->dev.platform_data;
1514
lp->mii_bus = platform_get_drvdata(pd);
1516
dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1518
goto out_err_probe_mac;
1520
lp->mii_bus->priv = ndev;
1521
mii_bus_data = pd->dev.platform_data;
1523
rc = mii_probe(ndev, mii_bus_data->phy_mode);
1525
dev_err(&pdev->dev, "MII Probe failed!\n");
1526
goto out_err_mii_probe;
1529
lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1530
lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1532
/* Fill in the fields of the device structure with ethernet values. */
1535
ndev->netdev_ops = &bfin_mac_netdev_ops;
1536
ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1538
init_timer(&lp->tx_reclaim_timer);
1539
lp->tx_reclaim_timer.data = (unsigned long)lp;
1540
lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1542
spin_lock_init(&lp->lock);
1544
/* now, enable interrupts */
1545
/* register irq handler */
1546
rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1547
IRQF_DISABLED, "EMAC_RX", ndev);
1549
dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1551
goto out_err_request_irq;
1554
rc = register_netdev(ndev);
1556
dev_err(&pdev->dev, "Cannot register net device!\n");
1557
goto out_err_reg_ndev;
1560
bfin_mac_hwtstamp_init(ndev);
1562
/* now, print out the card info, in a short format.. */
1563
netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1568
free_irq(IRQ_MAC_RX, ndev);
1569
out_err_request_irq:
1571
mdiobus_unregister(lp->mii_bus);
1572
mdiobus_free(lp->mii_bus);
1574
platform_set_drvdata(pdev, NULL);
1580
static int __devexit bfin_mac_remove(struct platform_device *pdev)
1582
struct net_device *ndev = platform_get_drvdata(pdev);
1583
struct bfin_mac_local *lp = netdev_priv(ndev);
1585
platform_set_drvdata(pdev, NULL);
1587
lp->mii_bus->priv = NULL;
1589
unregister_netdev(ndev);
1591
free_irq(IRQ_MAC_RX, ndev);
1599
static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1601
struct net_device *net_dev = platform_get_drvdata(pdev);
1602
struct bfin_mac_local *lp = netdev_priv(net_dev);
1605
bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1606
bfin_write_EMAC_WKUP_CTL(MPKE);
1607
enable_irq_wake(IRQ_MAC_WAKEDET);
1609
if (netif_running(net_dev))
1610
bfin_mac_close(net_dev);
1616
static int bfin_mac_resume(struct platform_device *pdev)
1618
struct net_device *net_dev = platform_get_drvdata(pdev);
1619
struct bfin_mac_local *lp = netdev_priv(net_dev);
1622
bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1623
bfin_write_EMAC_WKUP_CTL(0);
1624
disable_irq_wake(IRQ_MAC_WAKEDET);
1626
if (netif_running(net_dev))
1627
bfin_mac_open(net_dev);
1633
#define bfin_mac_suspend NULL
1634
#define bfin_mac_resume NULL
1635
#endif /* CONFIG_PM */
1637
static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1639
struct mii_bus *miibus;
1640
struct bfin_mii_bus_platform_data *mii_bus_pd;
1641
const unsigned short *pin_req;
1644
mii_bus_pd = dev_get_platdata(&pdev->dev);
1646
dev_err(&pdev->dev, "No peripherals in platform data!\n");
1651
* We are setting up a network card,
1652
* so set the GPIO pins to Ethernet mode
1654
pin_req = mii_bus_pd->mac_peripherals;
1655
rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
1657
dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1662
miibus = mdiobus_alloc();
1665
miibus->read = bfin_mdiobus_read;
1666
miibus->write = bfin_mdiobus_write;
1667
miibus->reset = bfin_mdiobus_reset;
1669
miibus->parent = &pdev->dev;
1670
miibus->name = "bfin_mii_bus";
1671
miibus->phy_mask = mii_bus_pd->phy_mask;
1673
snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
1674
miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1676
goto out_err_irq_alloc;
1678
for (i = rc; i < PHY_MAX_ADDR; ++i)
1679
miibus->irq[i] = PHY_POLL;
1681
rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1682
if (rc != mii_bus_pd->phydev_number)
1683
dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1684
mii_bus_pd->phydev_number);
1685
for (i = 0; i < rc; ++i) {
1686
unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1687
if (phyaddr < PHY_MAX_ADDR)
1688
miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1691
"Invalid PHY address %i for phydev %i\n",
1695
rc = mdiobus_register(miibus);
1697
dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1698
goto out_err_mdiobus_register;
1701
platform_set_drvdata(pdev, miibus);
1704
out_err_mdiobus_register:
1707
mdiobus_free(miibus);
1709
peripheral_free_list(pin_req);
1714
static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1716
struct mii_bus *miibus = platform_get_drvdata(pdev);
1717
struct bfin_mii_bus_platform_data *mii_bus_pd =
1718
dev_get_platdata(&pdev->dev);
1720
platform_set_drvdata(pdev, NULL);
1721
mdiobus_unregister(miibus);
1723
mdiobus_free(miibus);
1724
peripheral_free_list(mii_bus_pd->mac_peripherals);
1729
static struct platform_driver bfin_mii_bus_driver = {
1730
.probe = bfin_mii_bus_probe,
1731
.remove = __devexit_p(bfin_mii_bus_remove),
1733
.name = "bfin_mii_bus",
1734
.owner = THIS_MODULE,
1738
static struct platform_driver bfin_mac_driver = {
1739
.probe = bfin_mac_probe,
1740
.remove = __devexit_p(bfin_mac_remove),
1741
.resume = bfin_mac_resume,
1742
.suspend = bfin_mac_suspend,
1744
.name = KBUILD_MODNAME,
1745
.owner = THIS_MODULE,
1749
static int __init bfin_mac_init(void)
1752
ret = platform_driver_register(&bfin_mii_bus_driver);
1754
return platform_driver_register(&bfin_mac_driver);
1758
module_init(bfin_mac_init);
1760
static void __exit bfin_mac_cleanup(void)
1762
platform_driver_unregister(&bfin_mac_driver);
1763
platform_driver_unregister(&bfin_mii_bus_driver);
1766
module_exit(bfin_mac_cleanup);